src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count);
14
15static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
16static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
17static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
18static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
19static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
20static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
21static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
22
23void GBAMemoryInit(struct GBAMemory* memory) {
24 memory->d.load32 = GBALoad32;
25 memory->d.load16 = GBALoad16;
26 memory->d.loadU16 = GBALoadU16;
27 memory->d.load8 = GBALoad8;
28 memory->d.loadU8 = GBALoadU8;
29 memory->d.store32 = GBAStore32;
30 memory->d.store16 = GBAStore16;
31 memory->d.store8 = GBAStore8;
32
33 memory->bios = (uint32_t*) hleBios;
34 memory->fullBios = 0;
35 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
36 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
37 memory->rom = 0;
38 memset(memory->io, 0, sizeof(memory->io));
39 memset(memory->dma, 0, sizeof(memory->dma));
40
41 if (!memory->wram || !memory->iwram) {
42 GBAMemoryDeinit(memory);
43 memory->p->errno = GBA_OUT_OF_MEMORY;
44 memory->p->errstr = GBA_CANNOT_MMAP;
45 }
46
47 int i;
48 for (i = 0; i < 16; ++i) {
49 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
50 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
51 memory->waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
52 memory->waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
53 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
54 memory->waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
55 }
56 for (; i < 256; ++i) {
57 memory->waitstates16[i] = 0;
58 memory->waitstatesSeq16[i] = 0;
59 memory->waitstatesPrefetch16[i] = 0;
60 memory->waitstates32[i] = 0;
61 memory->waitstatesSeq32[i] = 0;
62 memory->waitstatesPrefetch32[i] = 0;
63 }
64
65 memory->activeRegion = 0;
66 memory->d.activeRegion = 0;
67 memory->d.activeMask = 0;
68 memory->d.setActiveRegion = GBASetActiveRegion;
69 memory->d.activePrefetchCycles32 = 0;
70 memory->d.activePrefetchCycles16 = 0;
71 memory->biosPrefetch = 0;
72 memory->d.waitMultiple = GBAWaitMultiple;
73}
74
75void GBAMemoryDeinit(struct GBAMemory* memory) {
76 munmap(memory->wram, SIZE_WORKING_RAM);
77 munmap(memory->iwram, SIZE_WORKING_IRAM);
78 GBASavedataDeinit(&memory->savedata);
79}
80
81static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
82 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
83
84 if (gbaMemory->activeRegion == REGION_BIOS) {
85 gbaMemory->biosPrefetch = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
86 }
87 gbaMemory->activeRegion = address >> BASE_OFFSET;
88 memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[gbaMemory->activeRegion];
89 memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[gbaMemory->activeRegion];
90 memory->activeNonseqCycles32 = gbaMemory->waitstates32[gbaMemory->activeRegion];
91 memory->activeNonseqCycles16 = gbaMemory->waitstates16[gbaMemory->activeRegion];
92 switch (address & ~OFFSET_MASK) {
93 case BASE_BIOS:
94 memory->activeRegion = gbaMemory->bios;
95 memory->activeMask = SIZE_BIOS - 1;
96 break;
97 case BASE_WORKING_RAM:
98 memory->activeRegion = gbaMemory->wram;
99 memory->activeMask = SIZE_WORKING_RAM - 1;
100 break;
101 case BASE_WORKING_IRAM:
102 memory->activeRegion = gbaMemory->iwram;
103 memory->activeMask = SIZE_WORKING_IRAM - 1;
104 break;
105 case BASE_CART0:
106 case BASE_CART0_EX:
107 case BASE_CART1:
108 case BASE_CART1_EX:
109 case BASE_CART2:
110 case BASE_CART2_EX:
111 memory->activeRegion = gbaMemory->rom;
112 memory->activeMask = SIZE_CART0 - 1;
113 break;
114 default:
115 memory->activeRegion = 0;
116 memory->activeMask = 0;
117 break;
118 }
119}
120
121int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
122 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
123 uint32_t value = 0;
124 int wait = 0;
125
126 switch (address & ~OFFSET_MASK) {
127 case BASE_BIOS:
128 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
129 if (address < SIZE_BIOS) {
130 value = gbaMemory->bios[address >> 2];
131 } else {
132 value = 0;
133 }
134 } else {
135 value = gbaMemory->biosPrefetch;
136 }
137 break;
138 case BASE_WORKING_RAM:
139 value = gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
140 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
141 break;
142 case BASE_WORKING_IRAM:
143 value = gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
144 break;
145 case BASE_IO:
146 value = GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
147 break;
148 case BASE_PALETTE_RAM:
149 value = ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2];
150 break;
151 case BASE_VRAM:
152 value = ((int32_t*) gbaMemory->p->video.renderer->vram)[(address & 0x0001FFFF) >> 2];
153 break;
154 case BASE_OAM:
155 value = ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2];
156 break;
157 case BASE_CART0:
158 case BASE_CART0_EX:
159 case BASE_CART1:
160 case BASE_CART1_EX:
161 case BASE_CART2:
162 case BASE_CART2_EX:
163 wait = gbaMemory->waitstates32[address >> BASE_OFFSET];
164 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
165 value = gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
166 }
167 break;
168 case BASE_CART_SRAM:
169 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
170 break;
171 default:
172 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
173 if (gbaMemory->p->cpu.executionMode == MODE_ARM) {
174 value = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
175 } else {
176 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_THUMB * 2, 0);
177 value |= value << 16;
178 }
179 break;
180 }
181
182
183 if (cycleCounter) {
184 *cycleCounter += 2 + wait;
185 }
186 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
187 int rotate = (address & 3) << 3;
188 return (value >> rotate) | (value << (32 - rotate));
189}
190
191uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
192 return GBALoad16(memory, address, cycleCounter);
193}
194
195int16_t GBALoad16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
196 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
197 int16_t value = 0;
198 int wait = 0;
199
200 switch (address & ~OFFSET_MASK) {
201 case BASE_BIOS:
202 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
203 if (address < SIZE_BIOS) {
204 value = ((int16_t*) gbaMemory->bios)[address >> 1];
205 } else {
206 value = 0;
207 }
208 } else {
209 value = gbaMemory->biosPrefetch;
210 }
211 break;
212 case BASE_WORKING_RAM:
213 value = ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
214 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
215 break;
216 case BASE_WORKING_IRAM:
217 value = ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
218 break;
219 case BASE_IO:
220 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
221 break;
222 case BASE_PALETTE_RAM:
223 value = gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
224 break;
225 case BASE_VRAM:
226 value = gbaMemory->p->video.renderer->vram[(address & 0x0001FFFF) >> 1];
227 break;
228 case BASE_OAM:
229 value = gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1];
230 break;
231 case BASE_CART0:
232 case BASE_CART0_EX:
233 case BASE_CART1:
234 case BASE_CART1_EX:
235 case BASE_CART2:
236 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
237 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
238 value = ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
239 }
240 break;
241 case BASE_CART2_EX:
242 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
243 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
244 value = GBASavedataReadEEPROM(&gbaMemory->savedata);
245 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
246 value = ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
247 }
248 break;
249 case BASE_CART_SRAM:
250 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
251 break;
252 default:
253 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
254 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0);
255 break;
256 }
257
258 if (cycleCounter) {
259 *cycleCounter += 2 + wait;
260 }
261 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
262 int rotate = (address & 1) << 3;
263 return (value >> rotate) | ((value << rotate) & 0xFF00);
264}
265
266uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
267 return GBALoad8(memory, address, cycleCounter);
268}
269
270int8_t GBALoad8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
271 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
272 int8_t value = 0;
273 int wait = 0;
274
275 switch (address & ~OFFSET_MASK) {
276 case BASE_BIOS:
277 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
278 if (address < SIZE_BIOS) {
279 value = ((int8_t*) gbaMemory->bios)[address];
280 } else {
281 value = 0;
282 }
283 } else {
284 value = gbaMemory->biosPrefetch;
285 }
286 break;
287 case BASE_WORKING_RAM:
288 value = ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
289 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
290 break;
291 case BASE_WORKING_IRAM:
292 value = ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
293 break;
294 case BASE_IO:
295 value = (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
296 break;
297 case BASE_PALETTE_RAM:
298 value = ((int8_t*) gbaMemory->p->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
299 break;
300 case BASE_VRAM:
301 value = ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x0001FFFF];
302 break;
303 case BASE_OAM:
304 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
305 break;
306 case BASE_CART0:
307 case BASE_CART0_EX:
308 case BASE_CART1:
309 case BASE_CART1_EX:
310 case BASE_CART2:
311 case BASE_CART2_EX:
312 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
313 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
314 value = ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
315 }
316 break;
317 case BASE_CART_SRAM:
318 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
319 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
320 GBASavedataInitSRAM(&gbaMemory->savedata);
321 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
322 value = gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
323 } else if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
324 value = GBASavedataReadFlash(&gbaMemory->savedata, address);
325 }
326 break;
327 default:
328 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
329 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0) >> ((address & 1) << 3);
330 break;
331 }
332
333 if (cycleCounter) {
334 *cycleCounter += 2 + wait;
335 }
336 return value;
337}
338
339void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value, int* cycleCounter) {
340 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
341 int wait = 0;
342
343 switch (address & ~OFFSET_MASK) {
344 case BASE_WORKING_RAM:
345 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
346 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
347 break;
348 case BASE_WORKING_IRAM:
349 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
350 break;
351 case BASE_IO:
352 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
353 break;
354 case BASE_PALETTE_RAM:
355 ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2] = value;
356 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
357 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
358 break;
359 case BASE_VRAM:
360 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
361 ((int32_t*) gbaMemory->p->video.renderer->vram)[(address & 0x0001FFFF) >> 2] = value;
362 }
363 break;
364 case BASE_OAM:
365 ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2] = value;
366 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
367 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
368 break;
369 case BASE_CART0:
370 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
371 break;
372 case BASE_CART_SRAM:
373 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
374 break;
375 default:
376 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
377 break;
378 }
379
380 if (cycleCounter) {
381 *cycleCounter += 1 + wait;
382 }
383}
384
385void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value, int* cycleCounter) {
386 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
387 int wait = 0;
388
389 switch (address & ~OFFSET_MASK) {
390 case BASE_WORKING_RAM:
391 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
392 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
393 break;
394 case BASE_WORKING_IRAM:
395 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
396 break;
397 case BASE_IO:
398 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
399 break;
400 case BASE_PALETTE_RAM:
401 gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1] = value;
402 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
403 break;
404 case BASE_VRAM:
405 if ((address & OFFSET_MASK) < SIZE_VRAM) {
406 gbaMemory->p->video.renderer->vram[(address & 0x0001FFFF) >> 1] = value;
407 }
408 break;
409 case BASE_OAM:
410 gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1] = value;
411 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
412 break;
413 case BASE_CART0:
414 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
415 break;
416 case BASE_CART2_EX:
417 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
418 GBASavedataInitEEPROM(&gbaMemory->savedata);
419 }
420 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
421 break;
422 case BASE_CART_SRAM:
423 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
424 break;
425 default:
426 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
427 break;
428 }
429
430 if (cycleCounter) {
431 *cycleCounter += 1 + wait;
432 }
433}
434
435void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value, int* cycleCounter) {
436 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
437 int wait = 0;
438
439 switch (address & ~OFFSET_MASK) {
440 case BASE_WORKING_RAM:
441 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
442 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
443 break;
444 case BASE_WORKING_IRAM:
445 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
446 break;
447 case BASE_IO:
448 GBAIOWrite8(gbaMemory->p, address & (SIZE_IO - 1), value);
449 break;
450 case BASE_PALETTE_RAM:
451 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
452 break;
453 case BASE_VRAM:
454 if (address >= 0x06018000) {
455 // TODO: check BG mode
456 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
457 break;
458 }
459 ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x1FFFE] = value;
460 ((int8_t*) gbaMemory->p->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
461 break;
462 case BASE_OAM:
463 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
464 break;
465 case BASE_CART0:
466 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
467 break;
468 case BASE_CART_SRAM:
469 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
470 if (address == SAVEDATA_FLASH_BASE) {
471 GBASavedataInitFlash(&gbaMemory->savedata);
472 } else {
473 GBASavedataInitSRAM(&gbaMemory->savedata);
474 }
475 }
476 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
477 GBASavedataWriteFlash(&gbaMemory->savedata, address, value);
478 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
479 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
480 }
481 wait = gbaMemory->waitstates16[REGION_CART_SRAM];
482 break;
483 default:
484 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
485 break;
486 }
487
488 if (cycleCounter) {
489 *cycleCounter += 1 + wait;
490 }
491}
492
493static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count) {
494 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
495 int wait = 1 + gbaMemory->waitstates32[startAddress >> BASE_OFFSET];
496 wait += (1 + gbaMemory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
497 return wait;
498}
499
500void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
501 int sram = parameters & 0x0003;
502 int ws0 = (parameters & 0x000C) >> 2;
503 int ws0seq = (parameters & 0x0010) >> 4;
504 int ws1 = (parameters & 0x0060) >> 5;
505 int ws1seq = (parameters & 0x0080) >> 7;
506 int ws2 = (parameters & 0x0300) >> 8;
507 int ws2seq = (parameters & 0x0400) >> 10;
508 int prefetch = parameters & 0x4000;
509
510 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
511 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
512 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
513 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
514
515 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
516 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
517 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
518
519 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
520 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
521 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
522
523 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
524 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
525 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
526
527 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
528 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
529 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
530
531 if (!prefetch) {
532 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
533 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
534 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
535
536 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
537 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
538 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
539 } else {
540 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
541 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
542 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
543
544 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
545 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
546 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
547 }
548
549 memory->d.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
550 memory->d.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
551 memory->d.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
552 memory->d.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
553}
554
555int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
556 struct GBADMA* dma;
557 int32_t test = INT_MAX;
558
559 dma = &memory->dma[0];
560 dma->nextIRQ -= cycles;
561 if (dma->enable && dma->doIrq && dma->nextIRQ) {
562 if (dma->nextIRQ <= 0) {
563 dma->nextIRQ = INT_MAX;
564 GBARaiseIRQ(memory->p, IRQ_DMA0);
565 } else if (dma->nextIRQ < test) {
566 test = dma->nextIRQ;
567 }
568 }
569
570 dma = &memory->dma[1];
571 dma->nextIRQ -= cycles;
572 if (dma->enable && dma->doIrq && dma->nextIRQ) {
573 if (dma->nextIRQ <= 0) {
574 dma->nextIRQ = INT_MAX;
575 GBARaiseIRQ(memory->p, IRQ_DMA1);
576 } else if (dma->nextIRQ < test) {
577 test = dma->nextIRQ;
578 }
579 }
580
581 dma = &memory->dma[2];
582 dma->nextIRQ -= cycles;
583 if (dma->enable && dma->doIrq && dma->nextIRQ) {
584 if (dma->nextIRQ <= 0) {
585 dma->nextIRQ = INT_MAX;
586 GBARaiseIRQ(memory->p, IRQ_DMA2);
587 } else if (dma->nextIRQ < test) {
588 test = dma->nextIRQ;
589 }
590 }
591
592 dma = &memory->dma[3];
593 dma->nextIRQ -= cycles;
594 if (dma->enable && dma->doIrq && dma->nextIRQ) {
595 if (dma->nextIRQ <= 0) {
596 dma->nextIRQ = INT_MAX;
597 GBARaiseIRQ(memory->p, IRQ_DMA3);
598 } else if (dma->nextIRQ < test) {
599 test = dma->nextIRQ;
600 }
601 }
602
603 return test;
604}
605
606void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
607 memory->dma[dma].source = address & 0xFFFFFFFE;
608}
609
610void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
611 memory->dma[dma].dest = address & 0xFFFFFFFE;
612}
613
614void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
615 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
616}
617
618uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
619 struct GBADMA* currentDma = &memory->dma[dma];
620 int wasEnabled = currentDma->enable;
621 currentDma->packed = control;
622 currentDma->nextIRQ = 0;
623
624 if (currentDma->drq) {
625 GBALog(memory->p, GBA_LOG_STUB, "DRQ not implemented");
626 }
627
628 if (!wasEnabled && currentDma->enable) {
629 currentDma->nextSource = currentDma->source;
630 currentDma->nextDest = currentDma->dest;
631 currentDma->nextCount = currentDma->count;
632 GBAMemoryScheduleDMA(memory, dma, currentDma);
633 }
634 // If the DMA has already occurred, this value might have changed since the function started
635 return currentDma->packed;
636};
637
638void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
639 switch (info->timing) {
640 case DMA_TIMING_NOW:
641 GBAMemoryServiceDMA(memory, number, info);
642 break;
643 case DMA_TIMING_HBLANK:
644 // Handled implicitly
645 break;
646 case DMA_TIMING_VBLANK:
647 // Handled implicitly
648 break;
649 case DMA_TIMING_CUSTOM:
650 switch (number) {
651 case 0:
652 GBALog(memory->p, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
653 break;
654 case 1:
655 case 2:
656 GBAAudioScheduleFifoDma(&memory->p->audio, number, info);
657 break;
658 case 3:
659 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
660 break;
661 }
662 }
663}
664
665void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
666 struct GBADMA* dma;
667 int i;
668 for (i = 0; i < 4; ++i) {
669 dma = &memory->dma[i];
670 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
671 GBAMemoryServiceDMA(memory, i, dma);
672 }
673 }
674}
675
676void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
677 struct GBADMA* dma;
678 int i;
679 for (i = 0; i < 4; ++i) {
680 dma = &memory->dma[i];
681 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
682 GBAMemoryServiceDMA(memory, i, dma);
683 }
684 }
685}
686
687void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
688 if (!info->enable) {
689 // There was a DMA scheduled that got canceled
690 return;
691 }
692
693 uint32_t width = info->width ? 4 : 2;
694 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
695 int destOffset = DMA_OFFSET[info->dstControl] * width;
696 int32_t wordsRemaining = info->nextCount;
697 uint32_t source = info->nextSource;
698 uint32_t dest = info->nextDest;
699 uint32_t sourceRegion = source >> BASE_OFFSET;
700 uint32_t destRegion = dest >> BASE_OFFSET;
701
702 if (width == 4) {
703 int32_t word;
704 source &= 0xFFFFFFFC;
705 dest &= 0xFFFFFFFC;
706 while (wordsRemaining--) {
707 word = memory->d.load32(&memory->d, source, 0);
708 memory->d.store32(&memory->d, dest, word, 0);
709 source += sourceOffset;
710 dest += destOffset;
711 }
712 } else {
713 uint16_t word;
714 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
715 while (wordsRemaining--) {
716 word = GBASavedataReadEEPROM(&memory->savedata);
717 memory->d.store16(&memory->d, dest, word, 0);
718 source += sourceOffset;
719 dest += destOffset;
720 }
721 } else if (destRegion == REGION_CART2_EX) {
722 if (memory->savedata.type == SAVEDATA_NONE) {
723 GBASavedataInitEEPROM(&memory->savedata);
724 }
725 while (wordsRemaining) {
726 word = memory->d.load16(&memory->d, source, 0);
727 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
728 source += sourceOffset;
729 dest += destOffset;
730 --wordsRemaining;
731 }
732 } else {
733 while (wordsRemaining--) {
734 word = memory->d.load16(&memory->d, source, 0);
735 memory->d.store16(&memory->d, dest, word, 0);
736 source += sourceOffset;
737 dest += destOffset;
738 }
739 }
740 }
741
742 if (info->doIrq) {
743 info->nextIRQ = memory->p->cpu.cycles + 2;
744 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
745 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
746 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
747 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
748 }
749
750 info->nextSource = source;
751 info->nextDest = dest;
752 info->nextCount = wordsRemaining;
753
754 if (!info->repeat) {
755 info->enable = 0;
756
757 // Clear the enable bit in memory
758 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
759 } else {
760 info->nextCount = info->count;
761 if (info->dstControl == DMA_INCREMENT_RELOAD) {
762 info->nextDest = info->dest;
763 }
764 GBAMemoryScheduleDMA(memory, number, info);
765 }
766}