include/mgba/internal/arm/emitter-arm.h (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef EMITTER_ARM_H
7#define EMITTER_ARM_H
8
9#include "emitter-inlines.h"
10
11#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
12 EMITTER ## NAME
13
14#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
15 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
16 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
17
18#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
19 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
20 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
21 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
22 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
23 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
24 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
25 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
26 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
27 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
28 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
29 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
30 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
31 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
32 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
33 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
34 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
35
36#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
37 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
38 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
39
40#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, NAME, P, U, W, V) \
41 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## I ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W), V >= 5)), \
42 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## I ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W), V >= 5))
43
44#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
45 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
46 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
47 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
48 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
49 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
50 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
51 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
52 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
53 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
54 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
55 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
56 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
57 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
58 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
59 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
60 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
61
62#define DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, NAME, P, U, W, V) \
63 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSL_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), V >= 5), \
64 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
65 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), V >= 5), \
66 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
67 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ASR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), V >= 5), \
68 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
69 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ROR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), V >= 5), \
70 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
71 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSL_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), V >= 5), \
72 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
73 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), V >= 5), \
74 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
75 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ASR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), V >= 5), \
76 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
77 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ROR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), V >= 5), \
78 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
79
80#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
81 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
82 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
83
84#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, NAME, MODE, W, V) \
85 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## MODE ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W), V >= 5)), \
86 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## MODE ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W), V >= 5))
87
88#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
89 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
90
91// TODO: Support coprocessors
92#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, N, W) \
93 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
94 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
95
96#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2, NAME3) \
97 DO_8(DO_INTERLACE( \
98 DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))), \
99 DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME3)))))
100
101#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
102 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
103
104#define DECLARE_ARM_EMITTER_BLOCK(EMITTER, V) \
105 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
106 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
107 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, STRH, ILL, ILL), \
108 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, LDRH, LDRSB, LDRSH), \
109 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
110 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
111 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, STRHI, ILL, ILL), \
112 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, LDRHI, LDRSBI, LDRSHI), \
113 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
114 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
115 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, STRHU, ILL, ILL), \
116 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, LDRHU, LDRSBU, LDRSHU), \
117 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
118 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
119 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, STRHIU, ILL, ILL), \
120 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, LDRHIU, LDRSBIU, LDRSHIU), \
121 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
122 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
123 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
124 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
125 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
126 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
127 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
128 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
129 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
130 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
131 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
132 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
133 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
134 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
135 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
136 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
137 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
138 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
139 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
140 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
141 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX2), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
142 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
143 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
144 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
145 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
146 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
147 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
148 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
149 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
150 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
151 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
152 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
153 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
154 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
155 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
156 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
157 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
158 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
159 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
160 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
161 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
162 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
163 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
164 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
165 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
166 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
167 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
168 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
169 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
170 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
171 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
172 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
173 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, CLZ), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
174 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
175 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
176 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
177 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
178 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
179 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
180 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
181 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
182 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
183 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
184 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
185 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
186 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
187 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
188 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
189 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
190 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
191 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
192 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
193 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
194 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
195 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
196 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
197 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
198 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
199 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
200 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
201 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
202 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
203 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
204 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
205 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
206 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
207 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
208 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
209 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
210 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
211 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
212 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
213 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
214 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
215 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
216 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
217 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
218 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
219 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
220 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
221 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
222 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
223 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
224 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
225 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
226 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
227 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
228 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
229 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
230 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , , , V), \
231 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
232 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
233 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
234 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
235 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
236 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
237 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
238 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , U, , V), \
239 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
240 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
241 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
242 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
243 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
244 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
245 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
246 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , , V), \
247 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
248 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , W, V), \
249 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
250 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
251 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
252 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
253 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
254 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, , V), \
255 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
256 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, W, V), \
257 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
258 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
259 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
260 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
261 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
262 DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , , , V), \
263 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
264 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
265 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
266 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
267 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
268 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
269 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
270 DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , U, , V), \
271 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
272 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
273 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
274 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
275 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
276 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
277 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
278 DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , , V), \
279 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
280 DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , W, V), \
281 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
282 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
283 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
284 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
285 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
286 DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, , V), \
287 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
288 DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, W, V), \
289 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
290 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
291 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
292 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
293 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
294 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, , V), \
295 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
296 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, W, V), \
297 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
298 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
299 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
300 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
301 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
302 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, , V), \
303 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
304 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, W, V), \
305 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
306 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
307 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
308 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
309 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
310 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, , V), \
311 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
312 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, W, V), \
313 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
314 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
315 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
316 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
317 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
318 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, , V), \
319 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
320 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, W, V), \
321 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
322 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
323 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
324 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
325 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
326 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
327 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
328 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
329 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
330 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
331 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
332 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
333 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
334 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
335 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
336 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
337 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
338 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
339 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
340 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
341 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
342 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
343 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
344 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
345 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
346 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
347 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
348 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
349 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
350 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
351 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
352 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
353 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
354 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
355 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
356 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
357 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
358 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
359 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR, MRC), \
360 DECLARE_ARM_SWI_BLOCK(EMITTER)
361
362#define DECLARE_ARM_F_EMITTER_BLOCK(EMITTER, V) \
363 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
364 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
365 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
366 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
367 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
368 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
369 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
370 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
371 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
372 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
373 DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \
374 DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \
375 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
376 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
377 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
378 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)),
379
380#endif