src/arm/decoder.h (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef ARM_DECODER_H
7#define ARM_DECODER_H
8
9#include "arm.h"
10
11// Bit 0: a register is involved with this operand
12// Bit 1: an immediate is invovled with this operand
13// Bit 2: a memory access is invovled with this operand
14// Bit 3: the destination of this operand is affected by this opcode
15// Bit 4: this operand is shifted by a register
16// Bit 5: this operand is shifted by an immediate
17// Bit 6: a coprocessor register is involved with this command
18#define ARM_OPERAND_NONE 0x00000000
19#define ARM_OPERAND_REGISTER_1 0x00000001
20#define ARM_OPERAND_IMMEDIATE_1 0x00000002
21#define ARM_OPERAND_MEMORY_1 0x00000004
22#define ARM_OPERAND_AFFECTED_1 0x00000008
23#define ARM_OPERAND_SHIFT_REGISTER_1 0x00000010
24#define ARM_OPERAND_SHIFT_IMMEDIATE_1 0x00000020
25#define ARM_OPERAND_COPROCESSOR_REG_1 0x00000040
26#define ARM_OPERAND_1 0x000000FF
27
28#define ARM_OPERAND_REGISTER_2 0x00000100
29#define ARM_OPERAND_IMMEDIATE_2 0x00000200
30#define ARM_OPERAND_MEMORY_2 0x00000400
31#define ARM_OPERAND_AFFECTED_2 0x00000800
32#define ARM_OPERAND_SHIFT_REGISTER_2 0x00001000
33#define ARM_OPERAND_SHIFT_IMMEDIATE_2 0x00002000
34#define ARM_OPERAND_COPROCESSOR_REG_2 0x00004000
35#define ARM_OPERAND_2 0x0000FF00
36
37#define ARM_OPERAND_REGISTER_3 0x00010000
38#define ARM_OPERAND_IMMEDIATE_3 0x00020000
39#define ARM_OPERAND_MEMORY_3 0x00040000
40#define ARM_OPERAND_AFFECTED_3 0x00080000
41#define ARM_OPERAND_SHIFT_REGISTER_3 0x00100000
42#define ARM_OPERAND_SHIFT_IMMEDIATE_3 0x00200000
43#define ARM_OPERAND_COPROCESSOR_REG_3 0x00400000
44#define ARM_OPERAND_3 0x00FF0000
45
46#define ARM_OPERAND_REGISTER_4 0x01000000
47#define ARM_OPERAND_IMMEDIATE_4 0x02000000
48#define ARM_OPERAND_MEMORY_4 0x04000000
49#define ARM_OPERAND_AFFECTED_4 0x08000000
50#define ARM_OPERAND_SHIFT_REGISTER_4 0x10000000
51#define ARM_OPERAND_SHIFT_IMMEDIATE_4 0x20000000
52#define ARM_OPERAND_COPROCESSOR_REG_4 0x40000000
53#define ARM_OPERAND_4 0xFF000000
54
55#define ARM_OPERAND_MEMORY (ARM_OPERAND_MEMORY_1 | ARM_OPERAND_MEMORY_2 | ARM_OPERAND_MEMORY_3 | ARM_OPERAND_MEMORY_4)
56#define ARM_OPERAND_COPROCESSOR (ARM_OPERAND_COPROCESSOR_REG_1 | ARM_OPERAND_COPROCESSOR_REG_2 | ARM_OPERAND_COPROCESSOR_REG_3 | ARM_OPERAND_COPROCESSOR_REG_4)
57
58#define ARM_MEMORY_REGISTER_BASE 0x0001
59#define ARM_MEMORY_IMMEDIATE_OFFSET 0x0002
60#define ARM_MEMORY_REGISTER_OFFSET 0x0004
61#define ARM_MEMORY_SHIFTED_OFFSET 0x0008
62#define ARM_MEMORY_PRE_INCREMENT 0x0010
63#define ARM_MEMORY_POST_INCREMENT 0x0020
64#define ARM_MEMORY_OFFSET_SUBTRACT 0x0040
65#define ARM_MEMORY_WRITEBACK 0x0080
66#define ARM_MEMORY_DECREMENT_AFTER 0x0000
67#define ARM_MEMORY_INCREMENT_AFTER 0x0100
68#define ARM_MEMORY_DECREMENT_BEFORE 0x0200
69#define ARM_MEMORY_INCREMENT_BEFORE 0x0300
70#define ARM_MEMORY_SPSR_SWAP 0x0400
71
72#define ARM_PSR_C 1
73#define ARM_PSR_X 2
74#define ARM_PSR_S 4
75#define ARM_PSR_F 8
76#define ARM_PSR_MASK 0xF
77
78#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x3)
79
80enum ARMCondition {
81 ARM_CONDITION_EQ = 0x0,
82 ARM_CONDITION_NE = 0x1,
83 ARM_CONDITION_CS = 0x2,
84 ARM_CONDITION_CC = 0x3,
85 ARM_CONDITION_MI = 0x4,
86 ARM_CONDITION_PL = 0x5,
87 ARM_CONDITION_VS = 0x6,
88 ARM_CONDITION_VC = 0x7,
89 ARM_CONDITION_HI = 0x8,
90 ARM_CONDITION_LS = 0x9,
91 ARM_CONDITION_GE = 0xA,
92 ARM_CONDITION_LT = 0xB,
93 ARM_CONDITION_GT = 0xC,
94 ARM_CONDITION_LE = 0xD,
95 ARM_CONDITION_AL = 0xE,
96 ARM_CONDITION_NV = 0xF
97};
98
99enum ARMShifterOperation {
100 ARM_SHIFT_NONE = 0,
101 ARM_SHIFT_LSL,
102 ARM_SHIFT_LSR,
103 ARM_SHIFT_ASR,
104 ARM_SHIFT_ROR,
105 ARM_SHIFT_RRX
106};
107
108union ARMOperand {
109 struct {
110 uint8_t reg;
111 uint8_t shifterOp;
112 union {
113 uint8_t shifterReg;
114 uint8_t shifterImm;
115 uint8_t psrBits;
116 };
117 };
118 int32_t immediate;
119};
120
121struct ARMCoprocessor {
122 uint8_t cp : 4;
123 uint8_t op1 : 4;
124 uint8_t op2 : 3;
125};
126
127enum ARMMemoryAccessType {
128 ARM_ACCESS_WORD = 4,
129 ARM_ACCESS_HALFWORD = 2,
130 ARM_ACCESS_SIGNED_HALFWORD = 10,
131 ARM_ACCESS_BYTE = 1,
132 ARM_ACCESS_SIGNED_BYTE = 9,
133 ARM_ACCESS_TRANSLATED_WORD = 20,
134 ARM_ACCESS_TRANSLATED_BYTE = 17
135};
136
137enum ARMBranchType {
138 ARM_BRANCH_NONE = 0,
139 ARM_BRANCH = 1,
140 ARM_BRANCH_INDIRECT = 2,
141 ARM_BRANCH_LINKED = 4
142};
143
144struct ARMMemoryAccess {
145 uint8_t baseReg;
146 uint8_t width;
147 uint16_t format;
148 union ARMOperand offset;
149};
150
151enum ARMMnemonic {
152 ARM_MN_ILL = 0,
153 ARM_MN_ADC,
154 ARM_MN_ADD,
155 ARM_MN_AND,
156 ARM_MN_ASR,
157 ARM_MN_B,
158 ARM_MN_BIC,
159 ARM_MN_BKPT,
160 ARM_MN_BL,
161 ARM_MN_BX,
162 ARM_MN_CDP,
163 ARM_MN_CMN,
164 ARM_MN_CMP,
165 ARM_MN_EOR,
166 ARM_MN_LDC,
167 ARM_MN_LDM,
168 ARM_MN_LDR,
169 ARM_MN_LSL,
170 ARM_MN_LSR,
171 ARM_MN_MCR,
172 ARM_MN_MLA,
173 ARM_MN_MOV,
174 ARM_MN_MRC,
175 ARM_MN_MRS,
176 ARM_MN_MSR,
177 ARM_MN_MUL,
178 ARM_MN_MVN,
179 ARM_MN_NEG,
180 ARM_MN_ORR,
181 ARM_MN_ROR,
182 ARM_MN_RSB,
183 ARM_MN_RSC,
184 ARM_MN_SBC,
185 ARM_MN_SMLAL,
186 ARM_MN_SMULL,
187 ARM_MN_STC,
188 ARM_MN_STM,
189 ARM_MN_STR,
190 ARM_MN_SUB,
191 ARM_MN_SWI,
192 ARM_MN_SWP,
193 ARM_MN_TEQ,
194 ARM_MN_TST,
195 ARM_MN_UMLAL,
196 ARM_MN_UMULL,
197
198 ARM_MN_MAX
199};
200
201enum {
202 ARM_CPSR = 16,
203 ARM_SPSR = 17
204};
205
206struct ARMInstructionInfo {
207 uint32_t opcode;
208 union ARMOperand op1;
209 union ARMOperand op2;
210 union ARMOperand op3;
211 union ARMOperand op4;
212 struct ARMMemoryAccess memory;
213 int operandFormat;
214 unsigned execMode : 1;
215 bool traps : 1;
216 bool affectsCPSR : 1;
217 unsigned branchType : 3;
218 unsigned condition : 4;
219 unsigned mnemonic : 6;
220 unsigned iCycles : 3;
221 unsigned cCycles : 4;
222 unsigned sInstructionCycles : 4;
223 unsigned nInstructionCycles : 4;
224 unsigned sDataCycles : 10;
225 unsigned nDataCycles : 10;
226 struct ARMCoprocessor cp;
227};
228
229void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
230void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info);
231bool ARMDecodeThumbCombine(struct ARMInstructionInfo* info1, struct ARMInstructionInfo* info2,
232 struct ARMInstructionInfo* out);
233int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, int blen);
234
235#endif