all repos — mgba @ 5a2c6d037dcb0d77d96780ced908c733411ee30d

mGBA Game Boy Advance Emulator

src/gb/io.c (view raw)

  1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#include "io.h"
  7
  8#include "gb/gb.h"
  9#include "gb/serialize.h"
 10
 11mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O");
 12
 13const char* const GBIORegisterNames[] = {
 14	[REG_JOYP] = "JOYP",
 15	[REG_SB] = "SB",
 16	[REG_SC] = "SC",
 17	[REG_DIV] = "DIV",
 18	[REG_TIMA] = "TIMA",
 19	[REG_TMA] = "TMA",
 20	[REG_TAC] = "TAC",
 21	[REG_IF] = "IF",
 22	[REG_NR10] = "NR10",
 23	[REG_NR11] = "NR11",
 24	[REG_NR12] = "NR12",
 25	[REG_NR13] = "NR13",
 26	[REG_NR14] = "NR14",
 27	[REG_NR21] = "NR21",
 28	[REG_NR22] = "NR22",
 29	[REG_NR23] = "NR23",
 30	[REG_NR24] = "NR24",
 31	[REG_NR30] = "NR30",
 32	[REG_NR31] = "NR31",
 33	[REG_NR32] = "NR32",
 34	[REG_NR33] = "NR33",
 35	[REG_NR34] = "NR34",
 36	[REG_NR41] = "NR41",
 37	[REG_NR42] = "NR42",
 38	[REG_NR43] = "NR43",
 39	[REG_NR44] = "NR44",
 40	[REG_NR50] = "NR50",
 41	[REG_NR51] = "NR51",
 42	[REG_NR52] = "NR52",
 43	[REG_LCDC] = "LCDC",
 44	[REG_STAT] = "STAT",
 45	[REG_SCY] = "SCY",
 46	[REG_SCX] = "SCX",
 47	[REG_LY] = "LY",
 48	[REG_LYC] = "LYC",
 49	[REG_DMA] = "DMA",
 50	[REG_BGP] = "BGP",
 51	[REG_OBP0] = "OBP0",
 52	[REG_OBP1] = "OBP1",
 53	[REG_WY] = "WY",
 54	[REG_WX] = "WX",
 55	[REG_KEY1] = "KEY1",
 56	[REG_VBK] = "VBK",
 57	[REG_HDMA1] = "HDMA1",
 58	[REG_HDMA2] = "HDMA2",
 59	[REG_HDMA3] = "HDMA3",
 60	[REG_HDMA4] = "HDMA4",
 61	[REG_HDMA5] = "HDMA5",
 62	[REG_RP] = "RP",
 63	[REG_BCPS] = "BCPS",
 64	[REG_BCPD] = "BCPD",
 65	[REG_OCPS] = "OCPS",
 66	[REG_OCPD] = "OCPD",
 67	[REG_SVBK] = "SVBK",
 68	[REG_IE] = "IE",
 69};
 70
 71static const uint8_t _registerMask[] = {
 72	[REG_SC]   = 0x7E, // TODO: GBC differences
 73	[REG_IF]   = 0xE0,
 74	[REG_TAC]  = 0xF8,
 75	[REG_NR10] = 0x80,
 76	[REG_NR11] = 0x3F,
 77	[REG_NR12] = 0x00,
 78	[REG_NR13] = 0xFF,
 79	[REG_NR14] = 0xBF,
 80	[REG_NR21] = 0x3F,
 81	[REG_NR22] = 0x00,
 82	[REG_NR23] = 0xFF,
 83	[REG_NR24] = 0xBF,
 84	[REG_NR30] = 0x7F,
 85	[REG_NR31] = 0xFF,
 86	[REG_NR32] = 0x9F,
 87	[REG_NR33] = 0xFF,
 88	[REG_NR34] = 0xBF,
 89	[REG_NR41] = 0xFF,
 90	[REG_NR42] = 0x00,
 91	[REG_NR43] = 0x00,
 92	[REG_NR44] = 0xBF,
 93	[REG_NR50] = 0x00,
 94	[REG_NR51] = 0x00,
 95	[REG_NR52] = 0x70,
 96	[REG_STAT] = 0x80,
 97	[REG_KEY1] = 0x7E,
 98	[REG_VBK] = 0xFE,
 99	[REG_OCPS] = 0x40,
100	[REG_BCPS] = 0x40,
101	[REG_UNK6C] = 0xFE,
102	[REG_SVBK] = 0xF8,
103	[REG_UNK75] = 0x8F,
104	[REG_IE]   = 0xE0,
105};
106
107void GBIOInit(struct GB* gb) {
108	memset(gb->memory.io, 0, sizeof(gb->memory.io));
109}
110
111void GBIOReset(struct GB* gb) {
112	memset(gb->memory.io, 0, sizeof(gb->memory.io));
113
114	GBIOWrite(gb, REG_TIMA, 0);
115	GBIOWrite(gb, REG_TMA, 0);
116	GBIOWrite(gb, REG_TAC, 0);
117	GBIOWrite(gb, REG_IF, 1);
118	GBIOWrite(gb, REG_NR52, 0xF1);
119	GBIOWrite(gb, REG_NR10, 0x80);
120	GBIOWrite(gb, REG_NR11, 0xBF);
121	GBIOWrite(gb, REG_NR12, 0xF3);
122	GBIOWrite(gb, REG_NR13, 0xF3);
123	GBIOWrite(gb, REG_NR14, 0xBF);
124	GBIOWrite(gb, REG_NR21, 0x3F);
125	GBIOWrite(gb, REG_NR22, 0x00);
126	GBIOWrite(gb, REG_NR24, 0xBF);
127	GBIOWrite(gb, REG_NR30, 0x7F);
128	GBIOWrite(gb, REG_NR31, 0xFF);
129	GBIOWrite(gb, REG_NR32, 0x9F);
130	GBIOWrite(gb, REG_NR34, 0xBF);
131	GBIOWrite(gb, REG_NR41, 0xFF);
132	GBIOWrite(gb, REG_NR42, 0x00);
133	GBIOWrite(gb, REG_NR43, 0x00);
134	GBIOWrite(gb, REG_NR44, 0xBF);
135	GBIOWrite(gb, REG_NR50, 0x77);
136	GBIOWrite(gb, REG_NR51, 0xF3);
137	GBIOWrite(gb, REG_LCDC, 0x91);
138	GBIOWrite(gb, REG_SCY, 0x00);
139	GBIOWrite(gb, REG_SCX, 0x00);
140	GBIOWrite(gb, REG_LYC, 0x00);
141	GBIOWrite(gb, REG_BGP, 0xFC);
142	GBIOWrite(gb, REG_OBP0, 0xFF);
143	GBIOWrite(gb, REG_OBP1, 0xFF);
144	GBIOWrite(gb, REG_WY, 0x00);
145	GBIOWrite(gb, REG_WX, 0x00);
146	GBIOWrite(gb, REG_VBK, 0);
147	GBIOWrite(gb, REG_BCPS, 0);
148	GBIOWrite(gb, REG_OCPS, 0);
149	GBIOWrite(gb, REG_SVBK, 1);
150	GBIOWrite(gb, REG_HDMA1, 0xFF);
151	GBIOWrite(gb, REG_HDMA2, 0xFF);
152	GBIOWrite(gb, REG_HDMA3, 0xFF);
153	GBIOWrite(gb, REG_HDMA4, 0xFF);
154	gb->memory.io[REG_HDMA5] = 0xFF;
155	GBIOWrite(gb, REG_IE, 0x00);
156}
157
158void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
159	switch (address) {
160	case REG_DIV:
161		GBTimerDivReset(&gb->timer);
162		return;
163	case REG_NR10:
164		if (gb->audio.enable) {
165			GBAudioWriteNR10(&gb->audio, value);
166		} else {
167			value = 0;
168		}
169		break;
170	case REG_NR11:
171		if (gb->audio.enable) {
172			GBAudioWriteNR11(&gb->audio, value);
173		} else {
174			if (gb->audio.style == GB_AUDIO_DMG) {
175				GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
176			}
177			value = 0;
178		}
179		break;
180	case REG_NR12:
181		if (gb->audio.enable) {
182			GBAudioWriteNR12(&gb->audio, value);
183		} else {
184			value = 0;
185		}
186		break;
187	case REG_NR13:
188		if (gb->audio.enable) {
189			GBAudioWriteNR13(&gb->audio, value);
190		} else {
191			value = 0;
192		}
193		break;
194	case REG_NR14:
195		if (gb->audio.enable) {
196			GBAudioWriteNR14(&gb->audio, value);
197		} else {
198			value = 0;
199		}
200		break;
201	case REG_NR21:
202		if (gb->audio.enable) {
203			GBAudioWriteNR21(&gb->audio, value);
204		} else {
205			if (gb->audio.style == GB_AUDIO_DMG) {
206				GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
207			}
208			value = 0;
209		}
210		break;
211	case REG_NR22:
212		if (gb->audio.enable) {
213			GBAudioWriteNR22(&gb->audio, value);
214		} else {
215			value = 0;
216		}
217		break;
218	case REG_NR23:
219		if (gb->audio.enable) {
220			GBAudioWriteNR23(&gb->audio, value);
221		} else {
222			value = 0;
223		}
224		break;
225	case REG_NR24:
226		if (gb->audio.enable) {
227			GBAudioWriteNR24(&gb->audio, value);
228		} else {
229			value = 0;
230		}
231		break;
232	case REG_NR30:
233		if (gb->audio.enable) {
234			GBAudioWriteNR30(&gb->audio, value);
235		} else {
236			value = 0;
237		}
238		break;
239	case REG_NR31:
240		if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
241			GBAudioWriteNR31(&gb->audio, value);
242		} else {
243			value = 0;
244		}
245		break;
246	case REG_NR32:
247		if (gb->audio.enable) {
248			GBAudioWriteNR32(&gb->audio, value);
249		} else {
250			value = 0;
251		}
252		break;
253	case REG_NR33:
254		if (gb->audio.enable) {
255			GBAudioWriteNR33(&gb->audio, value);
256		} else {
257			value = 0;
258		}
259		break;
260	case REG_NR34:
261		if (gb->audio.enable) {
262			GBAudioWriteNR34(&gb->audio, value);
263		} else {
264			value = 0;
265		}
266		break;
267	case REG_NR41:
268		if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
269			GBAudioWriteNR41(&gb->audio, value);
270		} else {
271			value = 0;
272		}
273		break;
274	case REG_NR42:
275		if (gb->audio.enable) {
276			GBAudioWriteNR42(&gb->audio, value);
277		} else {
278			value = 0;
279		}
280		break;
281	case REG_NR43:
282		if (gb->audio.enable) {
283			GBAudioWriteNR43(&gb->audio, value);
284		} else {
285			value = 0;
286		}
287		break;
288	case REG_NR44:
289		if (gb->audio.enable) {
290			GBAudioWriteNR44(&gb->audio, value);
291		} else {
292			value = 0;
293		}
294		break;
295	case REG_NR50:
296		if (gb->audio.enable) {
297			GBAudioWriteNR50(&gb->audio, value);
298		} else {
299			value = 0;
300		}
301		break;
302	case REG_NR51:
303		if (gb->audio.enable) {
304			GBAudioWriteNR51(&gb->audio, value);
305		} else {
306			value = 0;
307		}
308		break;
309	case REG_NR52:
310		GBAudioWriteNR52(&gb->audio, value);
311		value &= 0x80;
312		value |= gb->memory.io[REG_NR52] & 0x0F;
313		break;
314	case REG_WAVE_0:
315	case REG_WAVE_1:
316	case REG_WAVE_2:
317	case REG_WAVE_3:
318	case REG_WAVE_4:
319	case REG_WAVE_5:
320	case REG_WAVE_6:
321	case REG_WAVE_7:
322	case REG_WAVE_8:
323	case REG_WAVE_9:
324	case REG_WAVE_A:
325	case REG_WAVE_B:
326	case REG_WAVE_C:
327	case REG_WAVE_D:
328	case REG_WAVE_E:
329	case REG_WAVE_F:
330		if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
331			gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
332		} else if(gb->audio.ch3.readable) {
333			gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
334		}
335		break;
336	case REG_JOYP:
337	case REG_TIMA:
338	case REG_TMA:
339	case REG_LYC:
340		// Handled transparently by the registers
341		break;
342	case REG_TAC:
343		value = GBTimerUpdateTAC(&gb->timer, value);
344		break;
345	case REG_IF:
346		gb->memory.io[REG_IF] = value | 0xE0;
347		GBUpdateIRQs(gb);
348		return;
349	case REG_LCDC:
350		// TODO: handle GBC differences
351		value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
352		GBVideoWriteLCDC(&gb->video, value);
353		break;
354	case REG_DMA:
355		GBMemoryDMA(gb, value << 8);
356		break;
357	case REG_SCY:
358	case REG_SCX:
359	case REG_WY:
360	case REG_WX:
361		GBVideoProcessDots(&gb->video);
362		value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
363		break;
364	case REG_BGP:
365	case REG_OBP0:
366	case REG_OBP1:
367		GBVideoProcessDots(&gb->video);
368		GBVideoWritePalette(&gb->video, address, value);
369		break;
370	case REG_STAT:
371		GBVideoWriteSTAT(&gb->video, value);
372		break;
373	case 0x50:
374		if (gb->memory.romBase != gb->memory.rom) {
375			free(gb->memory.romBase);
376			gb->memory.romBase = gb->memory.rom;
377		}
378		break;
379	case REG_IE:
380		gb->memory.ie = value;
381		GBUpdateIRQs(gb);
382		return;
383	default:
384		if (gb->model >= GB_MODEL_CGB) {
385			switch (address) {
386			case REG_KEY1:
387				value &= 0x1;
388				value |= gb->memory.io[address] & 0x80;
389				break;
390			case REG_VBK:
391				GBVideoSwitchBank(&gb->video, value);
392				break;
393			case REG_HDMA1:
394			case REG_HDMA2:
395			case REG_HDMA3:
396			case REG_HDMA4:
397				// Handled transparently by the registers
398				break;
399			case REG_HDMA5:
400				GBMemoryWriteHDMA5(gb, value);
401				value &= 0x7F;
402				break;
403			case REG_BCPS:
404				gb->video.bcpIndex = value & 0x3F;
405				gb->video.bcpIncrement = value & 0x80;
406				gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
407				break;
408			case REG_BCPD:
409				GBVideoProcessDots(&gb->video);
410				GBVideoWritePalette(&gb->video, address, value);
411				break;
412			case REG_OCPS:
413				gb->video.ocpIndex = value & 0x3F;
414				gb->video.ocpIncrement = value & 0x80;
415				gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
416				break;
417			case REG_OCPD:
418				GBVideoProcessDots(&gb->video);
419				GBVideoWritePalette(&gb->video, address, value);
420				break;
421			case REG_SVBK:
422				GBMemorySwitchWramBank(&gb->memory, value);
423				value = gb->memory.wramCurrentBank;
424				break;
425			default:
426				goto failed;
427			}
428			goto success;
429		}
430		failed:
431		mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
432		if (address >= GB_SIZE_IO) {
433			return;
434		}
435		break;
436	}
437	success:
438	gb->memory.io[address] = value;
439}
440
441static uint8_t _readKeys(struct GB* gb) {
442	uint8_t keys = *gb->keySource;
443	switch (gb->memory.io[REG_JOYP] & 0x30) {
444	case 0x30:
445		keys = 0;
446		break;
447	case 0x20:
448		keys >>= 4;
449		break;
450	case 0x10:
451		break;
452	case 0x00:
453		keys |= keys >> 4;
454		break;
455	}
456	return (0xC0 | (gb->memory.io[REG_JOYP] | 0xF)) ^ (keys & 0xF);
457}
458
459uint8_t GBIORead(struct GB* gb, unsigned address) {
460	switch (address) {
461	case REG_JOYP:
462		return _readKeys(gb);
463	case REG_SB:
464	case REG_SC:
465		// TODO
466		break;
467	case REG_IE:
468		return gb->memory.ie;
469	case REG_WAVE_0:
470	case REG_WAVE_1:
471	case REG_WAVE_2:
472	case REG_WAVE_3:
473	case REG_WAVE_4:
474	case REG_WAVE_5:
475	case REG_WAVE_6:
476	case REG_WAVE_7:
477	case REG_WAVE_8:
478	case REG_WAVE_9:
479	case REG_WAVE_A:
480	case REG_WAVE_B:
481	case REG_WAVE_C:
482	case REG_WAVE_D:
483	case REG_WAVE_E:
484	case REG_WAVE_F:
485		if (gb->audio.playingCh3) {
486			if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
487				return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
488			} else {
489				return 0xFF;
490			}
491		} else {
492			return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
493		}
494		break;
495	case REG_IF:
496	case REG_NR10:
497	case REG_NR11:
498	case REG_NR12:
499	case REG_NR14:
500	case REG_NR21:
501	case REG_NR22:
502	case REG_NR24:
503	case REG_NR30:
504	case REG_NR32:
505	case REG_NR34:
506	case REG_NR41:
507	case REG_NR42:
508	case REG_NR43:
509	case REG_NR44:
510	case REG_NR50:
511	case REG_NR51:
512	case REG_NR52:
513	case REG_DIV:
514	case REG_TIMA:
515	case REG_TMA:
516	case REG_TAC:
517	case REG_STAT:
518	case REG_LCDC:
519	case REG_SCY:
520	case REG_SCX:
521	case REG_LY:
522	case REG_LYC:
523	case REG_BGP:
524	case REG_OBP0:
525	case REG_OBP1:
526	case REG_WY:
527	case REG_WX:
528		// Handled transparently by the registers
529		break;
530	default:
531		if (gb->model >= GB_MODEL_CGB) {
532			switch (address) {
533			case REG_KEY1:
534			case REG_VBK:
535			case REG_HDMA1:
536			case REG_HDMA2:
537			case REG_HDMA3:
538			case REG_HDMA4:
539			case REG_HDMA5:
540			case REG_BCPD:
541			case REG_OCPD:
542			case REG_SVBK:
543				// Handled transparently by the registers
544				goto success;
545			default:
546				break;
547			}
548		}
549		mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
550		return 0xFF;
551	}
552	success:
553	return gb->memory.io[address] | _registerMask[address];
554}
555
556struct GBSerializedState;
557void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
558	memcpy(state->io, gb->memory.io, GB_SIZE_IO);
559	state->ie = gb->memory.ie;
560}
561
562void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
563	memcpy(gb->memory.io, state->io, GB_SIZE_IO);
564	gb->memory.ie = state->ie;
565	gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
566	gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
567	gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
568	gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
569	gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
570}