1#ifndef ARM_DECODER_H
  2#define ARM_DECODER_H
  3
  4#include "arm.h"
  5
  6// Bit 0: a register is involved with this operand
  7// Bit 1: an immediate is invovled with this operand
  8// Bit 2: a memory access is invovled with this operand
  9// Bit 3: the destination of this operand is affected by this opcode
 10// Bit 4: this operand is shifted by a register
 11// Bit 5: this operand is shifted by an immediate
 12#define ARM_OPERAND_NONE                0x00000000
 13#define ARM_OPERAND_REGISTER_1          0x00000001
 14#define ARM_OPERAND_IMMEDIATE_1         0x00000002
 15#define ARM_OPERAND_MEMORY_1            0x00000004
 16#define ARM_OPERAND_AFFECTED_1          0x00000008
 17#define ARM_OPERAND_SHIFT_REGISTER_1    0x00000010
 18#define ARM_OPERAND_SHIFT_IMMEDIATE_1   0x00000020
 19#define ARM_OPERAND_1                   0x000000FF
 20
 21#define ARM_OPERAND_REGISTER_2          0x00000100
 22#define ARM_OPERAND_IMMEDIATE_2         0x00000200
 23#define ARM_OPERAND_MEMORY_2            0x00000400
 24#define ARM_OPERAND_AFFECTED_2          0x00000800
 25#define ARM_OPERAND_SHIFT_REGISTER_2    0x00001000
 26#define ARM_OPERAND_SHIFT_IMMEDIATE_2   0x00002000
 27#define ARM_OPERAND_2                   0x0000FF00
 28
 29#define ARM_OPERAND_REGISTER_3          0x00010000
 30#define ARM_OPERAND_IMMEDIATE_3         0x00020000
 31#define ARM_OPERAND_MEMORY_3            0x00040000
 32#define ARM_OPERAND_AFFECTED_3          0x00080000
 33#define ARM_OPERAND_SHIFT_REGISTER_3    0x00100000
 34#define ARM_OPERAND_SHIFT_IMMEDIATE_3   0x00200000
 35#define ARM_OPERAND_3                   0x00FF0000
 36
 37#define ARM_OPERAND_REGISTER_4          0x01000000
 38#define ARM_OPERAND_IMMEDIATE_4         0x02000000
 39#define ARM_OPERAND_MEMORY_4            0x04000000
 40#define ARM_OPERAND_AFFECTED_4          0x08000000
 41#define ARM_OPERAND_SHIFT_REGISTER_4    0x10000000
 42#define ARM_OPERAND_SHIFT_IMMEDIATE_4   0x20000000
 43#define ARM_OPERAND_4                   0xFF000000
 44
 45
 46#define ARM_MEMORY_REGISTER_BASE     0x0001
 47#define ARM_MEMORY_IMMEDIATE_OFFSET  0x0002
 48#define ARM_MEMORY_REGISTER_OFFSET   0x0004
 49#define ARM_MEMORY_SHIFTED_OFFSET    0x0008
 50#define ARM_MEMORY_PRE_INCREMENT     0x0010
 51#define ARM_MEMORY_POST_INCREMENT    0x0020
 52#define ARM_MEMORY_OFFSET_SUBTRACT   0x0040
 53#define ARM_MEMORY_WRITEBACK         0x0080
 54#define ARM_MEMORY_DECREMENT_AFTER   0x0000
 55#define ARM_MEMORY_INCREMENT_AFTER   0x0100
 56#define ARM_MEMORY_DECREMENT_BEFORE  0x0200
 57#define ARM_MEMORY_INCREMENT_BEFORE  0x0300
 58#define ARM_MEMORY_SPSR_SWAP         0x0400
 59
 60#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x3)
 61
 62enum ARMCondition {
 63	ARM_CONDITION_EQ = 0x0,
 64	ARM_CONDITION_NE = 0x1,
 65	ARM_CONDITION_CS = 0x2,
 66	ARM_CONDITION_CC = 0x3,
 67	ARM_CONDITION_MI = 0x4,
 68	ARM_CONDITION_PL = 0x5,
 69	ARM_CONDITION_VS = 0x6,
 70	ARM_CONDITION_VC = 0x7,
 71	ARM_CONDITION_HI = 0x8,
 72	ARM_CONDITION_LS = 0x9,
 73	ARM_CONDITION_GE = 0xA,
 74	ARM_CONDITION_LT = 0xB,
 75	ARM_CONDITION_GT = 0xC,
 76	ARM_CONDITION_LE = 0xD,
 77	ARM_CONDITION_AL = 0xE,
 78	ARM_CONDITION_NV = 0xF
 79};
 80
 81enum ARMShifterOperation {
 82	ARM_SHIFT_NONE = 0,
 83	ARM_SHIFT_LSL,
 84	ARM_SHIFT_LSR,
 85	ARM_SHIFT_ASR,
 86	ARM_SHIFT_ROR,
 87	ARM_SHIFT_RRX
 88};
 89
 90union ARMOperand {
 91	struct {
 92		uint8_t reg;
 93		uint8_t shifterOp;
 94		union {
 95			uint8_t shifterReg;
 96			uint8_t shifterImm;
 97		};
 98	};
 99	int32_t immediate;
100};
101
102enum ARMMemoryAccessType {
103	ARM_ACCESS_WORD = 4,
104	ARM_ACCESS_HALFWORD = 2,
105	ARM_ACCESS_SIGNED_HALFWORD = 10,
106	ARM_ACCESS_BYTE = 1,
107	ARM_ACCESS_SIGNED_BYTE = 9,
108	ARM_ACCESS_TRANSLATED_WORD = 20,
109	ARM_ACCESS_TRANSLATED_BYTE = 17
110};
111
112enum ARMBranchType {
113	ARM_BRANCH_NONE = 0,
114	ARM_BRANCH = 1,
115	ARM_BRANCH_INDIRECT = 2,
116	ARM_BRANCH_LINKED = 4
117};
118
119struct ARMMemoryAccess {
120	uint8_t baseReg;
121	uint8_t width;
122	uint16_t format;
123	union ARMOperand offset;
124};
125
126enum ARMMnemonic {
127	ARM_MN_ILL = 0,
128	ARM_MN_ADC,
129	ARM_MN_ADD,
130	ARM_MN_AND,
131	ARM_MN_ASR,
132	ARM_MN_B,
133	ARM_MN_BIC,
134	ARM_MN_BKPT,
135	ARM_MN_BL,
136	ARM_MN_BLH,
137	ARM_MN_BX,
138	ARM_MN_CMN,
139	ARM_MN_CMP,
140	ARM_MN_EOR,
141	ARM_MN_LDM,
142	ARM_MN_LDR,
143	ARM_MN_LSL,
144	ARM_MN_LSR,
145	ARM_MN_MLA,
146	ARM_MN_MOV,
147	ARM_MN_MRS,
148	ARM_MN_MSR,
149	ARM_MN_MUL,
150	ARM_MN_MVN,
151	ARM_MN_NEG,
152	ARM_MN_ORR,
153	ARM_MN_ROR,
154	ARM_MN_RSB,
155	ARM_MN_RSC,
156	ARM_MN_SBC,
157	ARM_MN_SMLAL,
158	ARM_MN_SMULL,
159	ARM_MN_STM,
160	ARM_MN_STR,
161	ARM_MN_SUB,
162	ARM_MN_SWI,
163	ARM_MN_SWP,
164	ARM_MN_TEQ,
165	ARM_MN_TST,
166	ARM_MN_UMLAL,
167	ARM_MN_UMULL,
168
169	ARM_MN_MAX
170};
171
172enum {
173	ARM_CPSR = 16,
174	ARM_SPSR = 17
175};
176
177struct ARMInstructionInfo {
178	uint32_t opcode;
179	union ARMOperand op1;
180	union ARMOperand op2;
181	union ARMOperand op3;
182	union ARMOperand op4;
183	struct ARMMemoryAccess memory;
184	int operandFormat;
185	unsigned execMode : 1;
186	bool traps : 1;
187	bool affectsCPSR : 1;
188	unsigned branchType : 3;
189	unsigned condition : 4;
190	unsigned mnemonic : 6;
191	unsigned iCycles : 3;
192	unsigned cCycles : 4;
193	unsigned sInstructionCycles : 4;
194	unsigned nInstructionCycles : 4;
195	unsigned sDataCycles : 10;
196	unsigned nDataCycles : 10;
197};
198
199void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
200void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info);
201int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, int blen);
202
203#endif