src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/io.h>
7
8#include <mgba/internal/gb/gb.h>
9#include <mgba/internal/gb/sio.h>
10#include <mgba/internal/gb/serialize.h>
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
13
14const char* const GBIORegisterNames[] = {
15 [REG_JOYP] = "JOYP",
16 [REG_SB] = "SB",
17 [REG_SC] = "SC",
18 [REG_DIV] = "DIV",
19 [REG_TIMA] = "TIMA",
20 [REG_TMA] = "TMA",
21 [REG_TAC] = "TAC",
22 [REG_IF] = "IF",
23 [REG_NR10] = "NR10",
24 [REG_NR11] = "NR11",
25 [REG_NR12] = "NR12",
26 [REG_NR13] = "NR13",
27 [REG_NR14] = "NR14",
28 [REG_NR21] = "NR21",
29 [REG_NR22] = "NR22",
30 [REG_NR23] = "NR23",
31 [REG_NR24] = "NR24",
32 [REG_NR30] = "NR30",
33 [REG_NR31] = "NR31",
34 [REG_NR32] = "NR32",
35 [REG_NR33] = "NR33",
36 [REG_NR34] = "NR34",
37 [REG_NR41] = "NR41",
38 [REG_NR42] = "NR42",
39 [REG_NR43] = "NR43",
40 [REG_NR44] = "NR44",
41 [REG_NR50] = "NR50",
42 [REG_NR51] = "NR51",
43 [REG_NR52] = "NR52",
44 [REG_LCDC] = "LCDC",
45 [REG_STAT] = "STAT",
46 [REG_SCY] = "SCY",
47 [REG_SCX] = "SCX",
48 [REG_LY] = "LY",
49 [REG_LYC] = "LYC",
50 [REG_DMA] = "DMA",
51 [REG_BGP] = "BGP",
52 [REG_OBP0] = "OBP0",
53 [REG_OBP1] = "OBP1",
54 [REG_WY] = "WY",
55 [REG_WX] = "WX",
56 [REG_KEY1] = "KEY1",
57 [REG_VBK] = "VBK",
58 [REG_HDMA1] = "HDMA1",
59 [REG_HDMA2] = "HDMA2",
60 [REG_HDMA3] = "HDMA3",
61 [REG_HDMA4] = "HDMA4",
62 [REG_HDMA5] = "HDMA5",
63 [REG_RP] = "RP",
64 [REG_BCPS] = "BCPS",
65 [REG_BCPD] = "BCPD",
66 [REG_OCPS] = "OCPS",
67 [REG_OCPD] = "OCPD",
68 [REG_SVBK] = "SVBK",
69 [REG_IE] = "IE",
70};
71
72static const uint8_t _registerMask[] = {
73 [REG_SC] = 0x7E, // TODO: GBC differences
74 [REG_IF] = 0xE0,
75 [REG_TAC] = 0xF8,
76 [REG_NR10] = 0x80,
77 [REG_NR11] = 0x3F,
78 [REG_NR12] = 0x00,
79 [REG_NR13] = 0xFF,
80 [REG_NR14] = 0xBF,
81 [REG_NR21] = 0x3F,
82 [REG_NR22] = 0x00,
83 [REG_NR23] = 0xFF,
84 [REG_NR24] = 0xBF,
85 [REG_NR30] = 0x7F,
86 [REG_NR31] = 0xFF,
87 [REG_NR32] = 0x9F,
88 [REG_NR33] = 0xFF,
89 [REG_NR34] = 0xBF,
90 [REG_NR41] = 0xFF,
91 [REG_NR42] = 0x00,
92 [REG_NR43] = 0x00,
93 [REG_NR44] = 0xBF,
94 [REG_NR50] = 0x00,
95 [REG_NR51] = 0x00,
96 [REG_NR52] = 0x70,
97 [REG_STAT] = 0x80,
98 [REG_KEY1] = 0x7E,
99 [REG_VBK] = 0xFE,
100 [REG_OCPS] = 0x40,
101 [REG_BCPS] = 0x40,
102 [REG_UNK6C] = 0xFE,
103 [REG_SVBK] = 0xF8,
104 [REG_UNK75] = 0x8F,
105 [REG_IE] = 0xE0,
106};
107
108static void _writeSGBBits(struct GB* gb, int bits) {
109 if (!bits) {
110 gb->sgbBit = 0;
111 memset(gb->sgbPacket, 0, sizeof(gb->sgbPacket));
112 }
113 if (bits == gb->currentSgbBits) {
114 return;
115 }
116 gb->currentSgbBits = bits;
117 if (gb->sgbBit == 128 && bits == 2) {
118 GBVideoWriteSGBPacket(&gb->video, gb->sgbPacket);
119 ++gb->sgbBit;
120 }
121 if (gb->sgbBit >= 128) {
122 return;
123 }
124 switch (bits) {
125 case 1:
126 gb->sgbPacket[gb->sgbBit >> 3] |= 1 << (gb->sgbBit & 7);
127 // Fall through
128 case 2:
129 ++gb->sgbBit;
130 default:
131 break;
132 }
133}
134
135void GBIOInit(struct GB* gb) {
136 memset(gb->memory.io, 0, sizeof(gb->memory.io));
137}
138
139void GBIOReset(struct GB* gb) {
140 memset(gb->memory.io, 0, sizeof(gb->memory.io));
141
142 GBIOWrite(gb, REG_TIMA, 0);
143 GBIOWrite(gb, REG_TMA, 0);
144 GBIOWrite(gb, REG_TAC, 0);
145 GBIOWrite(gb, REG_IF, 1);
146 GBIOWrite(gb, REG_NR52, 0xF1);
147 GBIOWrite(gb, REG_NR14, 0xBF);
148 GBIOWrite(gb, REG_NR10, 0x80);
149 GBIOWrite(gb, REG_NR11, 0xBF);
150 GBIOWrite(gb, REG_NR12, 0xF3);
151 GBIOWrite(gb, REG_NR13, 0xF3);
152 GBIOWrite(gb, REG_NR24, 0xBF);
153 GBIOWrite(gb, REG_NR21, 0x3F);
154 GBIOWrite(gb, REG_NR22, 0x00);
155 GBIOWrite(gb, REG_NR34, 0xBF);
156 GBIOWrite(gb, REG_NR30, 0x7F);
157 GBIOWrite(gb, REG_NR31, 0xFF);
158 GBIOWrite(gb, REG_NR32, 0x9F);
159 GBIOWrite(gb, REG_NR44, 0xBF);
160 GBIOWrite(gb, REG_NR41, 0xFF);
161 GBIOWrite(gb, REG_NR42, 0x00);
162 GBIOWrite(gb, REG_NR43, 0x00);
163 GBIOWrite(gb, REG_NR50, 0x77);
164 GBIOWrite(gb, REG_NR51, 0xF3);
165 GBIOWrite(gb, REG_LCDC, 0x91);
166 GBIOWrite(gb, REG_SCY, 0x00);
167 GBIOWrite(gb, REG_SCX, 0x00);
168 GBIOWrite(gb, REG_LYC, 0x00);
169 GBIOWrite(gb, REG_BGP, 0xFC);
170 GBIOWrite(gb, REG_OBP0, 0xFF);
171 GBIOWrite(gb, REG_OBP1, 0xFF);
172 GBIOWrite(gb, REG_WY, 0x00);
173 GBIOWrite(gb, REG_WX, 0x00);
174 if (gb->model >= GB_MODEL_CGB) {
175 GBIOWrite(gb, REG_VBK, 0);
176 GBIOWrite(gb, REG_BCPS, 0);
177 GBIOWrite(gb, REG_OCPS, 0);
178 GBIOWrite(gb, REG_SVBK, 1);
179 GBIOWrite(gb, REG_HDMA1, 0xFF);
180 GBIOWrite(gb, REG_HDMA2, 0xFF);
181 GBIOWrite(gb, REG_HDMA3, 0xFF);
182 GBIOWrite(gb, REG_HDMA4, 0xFF);
183 gb->memory.io[REG_HDMA5] = 0xFF;
184 }
185 GBIOWrite(gb, REG_IE, 0x00);
186}
187
188void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
189 switch (address) {
190 case REG_SB:
191 GBSIOWriteSB(&gb->sio, value);
192 break;
193 case REG_SC:
194 GBSIOWriteSC(&gb->sio, value);
195 break;
196 case REG_DIV:
197 GBTimerDivReset(&gb->timer);
198 return;
199 case REG_NR10:
200 if (gb->audio.enable) {
201 GBAudioWriteNR10(&gb->audio, value);
202 } else {
203 value = 0;
204 }
205 break;
206 case REG_NR11:
207 if (gb->audio.enable) {
208 GBAudioWriteNR11(&gb->audio, value);
209 } else {
210 if (gb->audio.style == GB_AUDIO_DMG) {
211 GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
212 }
213 value = 0;
214 }
215 break;
216 case REG_NR12:
217 if (gb->audio.enable) {
218 GBAudioWriteNR12(&gb->audio, value);
219 } else {
220 value = 0;
221 }
222 break;
223 case REG_NR13:
224 if (gb->audio.enable) {
225 GBAudioWriteNR13(&gb->audio, value);
226 } else {
227 value = 0;
228 }
229 break;
230 case REG_NR14:
231 if (gb->audio.enable) {
232 GBAudioWriteNR14(&gb->audio, value);
233 } else {
234 value = 0;
235 }
236 break;
237 case REG_NR21:
238 if (gb->audio.enable) {
239 GBAudioWriteNR21(&gb->audio, value);
240 } else {
241 if (gb->audio.style == GB_AUDIO_DMG) {
242 GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
243 }
244 value = 0;
245 }
246 break;
247 case REG_NR22:
248 if (gb->audio.enable) {
249 GBAudioWriteNR22(&gb->audio, value);
250 } else {
251 value = 0;
252 }
253 break;
254 case REG_NR23:
255 if (gb->audio.enable) {
256 GBAudioWriteNR23(&gb->audio, value);
257 } else {
258 value = 0;
259 }
260 break;
261 case REG_NR24:
262 if (gb->audio.enable) {
263 GBAudioWriteNR24(&gb->audio, value);
264 } else {
265 value = 0;
266 }
267 break;
268 case REG_NR30:
269 if (gb->audio.enable) {
270 GBAudioWriteNR30(&gb->audio, value);
271 } else {
272 value = 0;
273 }
274 break;
275 case REG_NR31:
276 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
277 GBAudioWriteNR31(&gb->audio, value);
278 } else {
279 value = 0;
280 }
281 break;
282 case REG_NR32:
283 if (gb->audio.enable) {
284 GBAudioWriteNR32(&gb->audio, value);
285 } else {
286 value = 0;
287 }
288 break;
289 case REG_NR33:
290 if (gb->audio.enable) {
291 GBAudioWriteNR33(&gb->audio, value);
292 } else {
293 value = 0;
294 }
295 break;
296 case REG_NR34:
297 if (gb->audio.enable) {
298 GBAudioWriteNR34(&gb->audio, value);
299 } else {
300 value = 0;
301 }
302 break;
303 case REG_NR41:
304 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
305 GBAudioWriteNR41(&gb->audio, value);
306 } else {
307 value = 0;
308 }
309 break;
310 case REG_NR42:
311 if (gb->audio.enable) {
312 GBAudioWriteNR42(&gb->audio, value);
313 } else {
314 value = 0;
315 }
316 break;
317 case REG_NR43:
318 if (gb->audio.enable) {
319 GBAudioWriteNR43(&gb->audio, value);
320 } else {
321 value = 0;
322 }
323 break;
324 case REG_NR44:
325 if (gb->audio.enable) {
326 GBAudioWriteNR44(&gb->audio, value);
327 } else {
328 value = 0;
329 }
330 break;
331 case REG_NR50:
332 if (gb->audio.enable) {
333 GBAudioWriteNR50(&gb->audio, value);
334 } else {
335 value = 0;
336 }
337 break;
338 case REG_NR51:
339 if (gb->audio.enable) {
340 GBAudioWriteNR51(&gb->audio, value);
341 } else {
342 value = 0;
343 }
344 break;
345 case REG_NR52:
346 GBAudioWriteNR52(&gb->audio, value);
347 value &= 0x80;
348 value |= gb->memory.io[REG_NR52] & 0x0F;
349 break;
350 case REG_WAVE_0:
351 case REG_WAVE_1:
352 case REG_WAVE_2:
353 case REG_WAVE_3:
354 case REG_WAVE_4:
355 case REG_WAVE_5:
356 case REG_WAVE_6:
357 case REG_WAVE_7:
358 case REG_WAVE_8:
359 case REG_WAVE_9:
360 case REG_WAVE_A:
361 case REG_WAVE_B:
362 case REG_WAVE_C:
363 case REG_WAVE_D:
364 case REG_WAVE_E:
365 case REG_WAVE_F:
366 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
367 gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
368 } else if(gb->audio.ch3.readable) {
369 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
370 }
371 break;
372 case REG_JOYP:
373 if (gb->model == GB_MODEL_SGB) {
374 _writeSGBBits(gb, (value >> 4) & 3);
375 }
376 break;
377 case REG_TIMA:
378 case REG_TMA:
379 // Handled transparently by the registers
380 break;
381 case REG_TAC:
382 value = GBTimerUpdateTAC(&gb->timer, value);
383 break;
384 case REG_IF:
385 gb->memory.io[REG_IF] = value | 0xE0;
386 GBUpdateIRQs(gb);
387 return;
388 case REG_LCDC:
389 // TODO: handle GBC differences
390 GBVideoProcessDots(&gb->video);
391 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
392 GBVideoWriteLCDC(&gb->video, value);
393 break;
394 case REG_LYC:
395 GBVideoWriteLYC(&gb->video, value);
396 break;
397 case REG_DMA:
398 GBMemoryDMA(gb, value << 8);
399 break;
400 case REG_SCY:
401 case REG_SCX:
402 case REG_WY:
403 case REG_WX:
404 GBVideoProcessDots(&gb->video);
405 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
406 break;
407 case REG_BGP:
408 case REG_OBP0:
409 case REG_OBP1:
410 GBVideoProcessDots(&gb->video);
411 GBVideoWritePalette(&gb->video, address, value);
412 break;
413 case REG_STAT:
414 GBVideoWriteSTAT(&gb->video, value);
415 value = gb->video.stat;
416 break;
417 case 0x50:
418 if (gb->memory.romBase < gb->memory.rom || gb->memory.romBase > &gb->memory.rom[gb->memory.romSize - 1]) {
419 free(gb->memory.romBase);
420 gb->memory.romBase = gb->memory.rom;
421 }
422 break;
423 case REG_IE:
424 gb->memory.ie = value;
425 GBUpdateIRQs(gb);
426 return;
427 default:
428 if (gb->model >= GB_MODEL_CGB) {
429 switch (address) {
430 case REG_KEY1:
431 value &= 0x1;
432 value |= gb->memory.io[address] & 0x80;
433 break;
434 case REG_VBK:
435 GBVideoSwitchBank(&gb->video, value);
436 break;
437 case REG_HDMA1:
438 case REG_HDMA2:
439 case REG_HDMA3:
440 case REG_HDMA4:
441 // Handled transparently by the registers
442 break;
443 case REG_HDMA5:
444 GBMemoryWriteHDMA5(gb, value);
445 value &= 0x7F;
446 break;
447 case REG_BCPS:
448 gb->video.bcpIndex = value & 0x3F;
449 gb->video.bcpIncrement = value & 0x80;
450 gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
451 break;
452 case REG_BCPD:
453 GBVideoProcessDots(&gb->video);
454 GBVideoWritePalette(&gb->video, address, value);
455 return;
456 case REG_OCPS:
457 gb->video.ocpIndex = value & 0x3F;
458 gb->video.ocpIncrement = value & 0x80;
459 gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
460 break;
461 case REG_OCPD:
462 GBVideoProcessDots(&gb->video);
463 GBVideoWritePalette(&gb->video, address, value);
464 return;
465 case REG_SVBK:
466 GBMemorySwitchWramBank(&gb->memory, value);
467 value = gb->memory.wramCurrentBank;
468 break;
469 default:
470 goto failed;
471 }
472 goto success;
473 }
474 failed:
475 mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
476 if (address >= GB_SIZE_IO) {
477 return;
478 }
479 break;
480 }
481 success:
482 gb->memory.io[address] = value;
483}
484
485static uint8_t _readKeys(struct GB* gb) {
486 uint8_t keys = *gb->keySource;
487 switch (gb->memory.io[REG_JOYP] & 0x30) {
488 case 0x30:
489 // TODO: Increment
490 keys = (gb->video.sgbCommandHeader >> 3) == SGB_MLT_REG ? 0xF : 0;
491 break;
492 case 0x20:
493 keys >>= 4;
494 break;
495 case 0x10:
496 break;
497 case 0x00:
498 keys |= keys >> 4;
499 break;
500 }
501 return (0xC0 | (gb->memory.io[REG_JOYP] | 0xF)) ^ (keys & 0xF);
502}
503
504uint8_t GBIORead(struct GB* gb, unsigned address) {
505 switch (address) {
506 case REG_JOYP:
507 return _readKeys(gb);
508 case REG_IE:
509 return gb->memory.ie;
510 case REG_WAVE_0:
511 case REG_WAVE_1:
512 case REG_WAVE_2:
513 case REG_WAVE_3:
514 case REG_WAVE_4:
515 case REG_WAVE_5:
516 case REG_WAVE_6:
517 case REG_WAVE_7:
518 case REG_WAVE_8:
519 case REG_WAVE_9:
520 case REG_WAVE_A:
521 case REG_WAVE_B:
522 case REG_WAVE_C:
523 case REG_WAVE_D:
524 case REG_WAVE_E:
525 case REG_WAVE_F:
526 if (gb->audio.playingCh3) {
527 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
528 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
529 } else {
530 return 0xFF;
531 }
532 } else {
533 return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
534 }
535 break;
536 case REG_SB:
537 case REG_SC:
538 case REG_IF:
539 case REG_NR10:
540 case REG_NR11:
541 case REG_NR12:
542 case REG_NR14:
543 case REG_NR21:
544 case REG_NR22:
545 case REG_NR24:
546 case REG_NR30:
547 case REG_NR32:
548 case REG_NR34:
549 case REG_NR41:
550 case REG_NR42:
551 case REG_NR43:
552 case REG_NR44:
553 case REG_NR50:
554 case REG_NR51:
555 case REG_NR52:
556 case REG_DIV:
557 case REG_TIMA:
558 case REG_TMA:
559 case REG_TAC:
560 case REG_STAT:
561 case REG_LCDC:
562 case REG_SCY:
563 case REG_SCX:
564 case REG_LY:
565 case REG_LYC:
566 case REG_BGP:
567 case REG_OBP0:
568 case REG_OBP1:
569 case REG_WY:
570 case REG_WX:
571 // Handled transparently by the registers
572 break;
573 default:
574 if (gb->model >= GB_MODEL_CGB) {
575 switch (address) {
576 case REG_KEY1:
577 case REG_VBK:
578 case REG_HDMA1:
579 case REG_HDMA2:
580 case REG_HDMA3:
581 case REG_HDMA4:
582 case REG_HDMA5:
583 case REG_BCPS:
584 case REG_BCPD:
585 case REG_OCPS:
586 case REG_OCPD:
587 case REG_SVBK:
588 // Handled transparently by the registers
589 goto success;
590 default:
591 break;
592 }
593 }
594 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
595 return 0xFF;
596 }
597 success:
598 return gb->memory.io[address] | _registerMask[address];
599}
600
601void GBTestKeypadIRQ(struct GB* gb) {
602 if (_readKeys(gb)) {
603 gb->memory.io[REG_IF] |= (1 << GB_IRQ_KEYPAD);
604 GBUpdateIRQs(gb);
605 }
606}
607
608struct GBSerializedState;
609void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
610 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
611 state->ie = gb->memory.ie;
612}
613
614void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
615 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
616 gb->memory.ie = state->ie;
617
618 if (GBAudioEnableGetEnable(*gb->audio.nr52)) {
619 GBIOWrite(gb, REG_NR10, gb->memory.io[REG_NR10]);
620 GBIOWrite(gb, REG_NR11, gb->memory.io[REG_NR11]);
621 GBIOWrite(gb, REG_NR12, gb->memory.io[REG_NR12]);
622 GBIOWrite(gb, REG_NR13, gb->memory.io[REG_NR13]);
623 gb->audio.ch1.control.frequency &= 0xFF;
624 gb->audio.ch1.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR14] << 8);
625 gb->audio.ch1.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR14] << 8);
626 GBIOWrite(gb, REG_NR21, gb->memory.io[REG_NR21]);
627 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR22]);
628 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR23]);
629 gb->audio.ch2.control.frequency &= 0xFF;
630 gb->audio.ch2.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR24] << 8);
631 gb->audio.ch2.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR24] << 8);
632 GBIOWrite(gb, REG_NR30, gb->memory.io[REG_NR30]);
633 GBIOWrite(gb, REG_NR31, gb->memory.io[REG_NR31]);
634 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR32]);
635 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR33]);
636 gb->audio.ch3.rate &= 0xFF;
637 gb->audio.ch3.rate |= GBAudioRegisterControlGetRate(gb->memory.io[REG_NR34] << 8);
638 gb->audio.ch3.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR34] << 8);
639 GBIOWrite(gb, REG_NR41, gb->memory.io[REG_NR41]);
640 GBIOWrite(gb, REG_NR42, gb->memory.io[REG_NR42]);
641 GBIOWrite(gb, REG_NR43, gb->memory.io[REG_NR43]);
642 gb->audio.ch4.stop = GBAudioRegisterNoiseControlGetStop(gb->memory.io[REG_NR44]);
643 GBIOWrite(gb, REG_NR50, gb->memory.io[REG_NR50]);
644 GBIOWrite(gb, REG_NR51, gb->memory.io[REG_NR51]);
645 }
646
647 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
648 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
649 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
650 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
651 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
652 if (gb->model == GB_MODEL_SGB) {
653 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_BGP, state->io[REG_BGP]);
654 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP0, state->io[REG_OBP0]);
655 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP1, state->io[REG_OBP1]);
656 }
657 gb->video.stat = state->io[REG_STAT];
658}