1#ifndef ISA_INLINES_H
 2#define ISA_INLINES_H
 3
 4#include "arm.h"
 5
 6#define UNUSED(V) (void)(V)
 7
 8#define DO_4(DIRECTIVE) \
 9	DIRECTIVE, \
10	DIRECTIVE, \
11	DIRECTIVE, \
12	DIRECTIVE
13
14#define DO_8(DIRECTIVE) \
15	DIRECTIVE, \
16	DIRECTIVE, \
17	DIRECTIVE, \
18	DIRECTIVE, \
19	DIRECTIVE, \
20	DIRECTIVE, \
21	DIRECTIVE, \
22	DIRECTIVE
23
24#define DO_256(DIRECTIVE) \
25	DO_4(DO_8(DO_8(DIRECTIVE)))
26
27#define DO_INTERLACE(LEFT, RIGHT) \
28	LEFT, \
29	RIGHT
30
31#define ARM_COND_EQ (cpu->cpsr.z)
32#define ARM_COND_NE (!cpu->cpsr.z)
33#define ARM_COND_CS (cpu->cpsr.c)
34#define ARM_COND_CC (!cpu->cpsr.c)
35#define ARM_COND_MI (cpu->cpsr.n)
36#define ARM_COND_PL (!cpu->cpsr.n)
37#define ARM_COND_VS (cpu->cpsr.v)
38#define ARM_COND_VC (!cpu->cpsr.v)
39#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
40#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
41#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
42#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
43#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
44#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
45#define ARM_COND_AL 1
46
47#define ARM_SIGN(I) ((I) >> 31)
48#define ARM_ROR(I, ROTATE) ((((uint32_t) (I)) >> ROTATE) | (I << (32 - ROTATE)))
49
50#define ARM_CARRY_FROM(M, N, D) ((ARM_SIGN((M) | (N))) && !(ARM_SIGN(D)))
51#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
52#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
53#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
54
55#define ARM_STUB cpu->board->hitStub(cpu->board, opcode)
56
57#define ARM_WRITE_PC \
58	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM) + WORD_SIZE_ARM; \
59	cpu->memory->setActiveRegion(cpu->memory, cpu->gprs[ARM_PC]); \
60	cpu->memory->loadU16(cpu->memory, cpu->gprs[ARM_PC], &cpu->cycles); \
61	cpu->cycles += 2 + cpu->memory->activePrefetchCycles32;
62
63#define THUMB_WRITE_PC \
64	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB) + WORD_SIZE_THUMB; \
65	cpu->memory->setActiveRegion(cpu->memory, cpu->gprs[ARM_PC]); \
66	cpu->memory->load32(cpu->memory, cpu->gprs[ARM_PC], &cpu->cycles); \
67	cpu->cycles += 2 + cpu->memory->activePrefetchCycles16;
68
69static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
70	return mode != MODE_SYSTEM && mode != MODE_USER;
71}
72
73static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
74	if (executionMode == cpu->executionMode) {
75		return;
76	}
77
78	cpu->executionMode = executionMode;
79	switch (executionMode) {
80	case MODE_ARM:
81		cpu->cpsr.t = 0;
82		break;
83	case MODE_THUMB:
84		cpu->cpsr.t = 1;
85	}
86}
87
88static inline void _ARMReadCPSR(struct ARMCore* cpu) {
89	_ARMSetMode(cpu, cpu->cpsr.t);
90	ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
91}
92
93#endif