src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "ds.h"
7
8#include "arm/decoder.h"
9#include "arm/debugger/debugger.h"
10#include "arm/isa-inlines.h"
11#include "ds/bios.h"
12
13#include "util/crc32.h"
14#include "util/memory.h"
15#include "util/math.h"
16#include "util/vfs.h"
17
18mLOG_DEFINE_CATEGORY(DS, "DS");
19
20const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
21const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
22const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
23
24static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
25static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
26
27enum {
28 DS7_SP_BASE = 0x380FD80,
29 DS7_SP_BASE_IRQ = 0x380FF80,
30 DS7_SP_BASE_SVC = 0x380FFC0,
31
32 DS9_SP_BASE = 0x3002F7C,
33 DS9_SP_BASE_IRQ = 0x3003F80,
34 DS9_SP_BASE_SVC = 0x3003FC0,
35};
36
37static void DSInit(void* cpu, struct mCPUComponent* component);
38
39static void DS7Reset(struct ARMCore* cpu);
40static void DS7TestIRQ(struct ARMCore* cpu);
41static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
42
43static void DS9Reset(struct ARMCore* cpu);
44static void DS9TestIRQ(struct ARMCore* cpu);
45static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
46static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
47
48static void DSProcessEvents(struct ARMCore* cpu);
49static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
50static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
51static void DSBreakpoint(struct ARMCore* cpu, int immediate);
52
53void DSCreate(struct DS* ds) {
54 ds->d.id = DS_COMPONENT_MAGIC;
55 ds->d.init = DSInit;
56 ds->d.deinit = NULL;
57 ds->arm7 = NULL;
58 ds->arm9 = NULL;
59}
60
61static void DSInit(void* cpu, struct mCPUComponent* component) {
62 struct DS* ds = (struct DS*) component;
63 struct ARMCore* core = cpu;
64 if (!ds->arm7) {
65 // The ARM7 must get initialized first
66 ds->arm7 = core;
67 ds->debugger = 0;
68 ds->sync = 0;
69 return;
70 }
71 ds->arm9 = cpu;
72
73 ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
74
75 DS7InterruptHandlerInit(&ds->arm7->irqh);
76 DS9InterruptHandlerInit(&ds->arm9->irqh);
77 DSMemoryInit(ds);
78
79 ds->video.p = ds;
80
81 ds->springIRQ7 = 0;
82 ds->springIRQ9 = 0;
83 ds->keySource = NULL;
84 ds->rtcSource = NULL;
85 ds->rumble = NULL;
86
87 ds->romVf = NULL;
88
89 ds->keyCallback = NULL;
90}
91
92void DSUnloadROM(struct DS* ds) {
93 if (ds->romVf) {
94 ds->romVf->close(ds->romVf);
95 ds->romVf = NULL;
96 }
97}
98
99void DSDestroy(struct DS* ds) {
100 DSUnloadROM(ds);
101 DSMemoryDeinit(ds);
102}
103
104void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
105 irqh->reset = DS7Reset;
106 irqh->processEvents = DSProcessEvents;
107 irqh->swi16 = DS7Swi16;
108 irqh->swi32 = DS7Swi32;
109 irqh->hitIllegal = DSIllegal;
110 irqh->readCPSR = DS7TestIRQ;
111 irqh->writeCP15 = NULL;
112 irqh->hitStub = DSHitStub;
113 irqh->bkpt16 = DSBreakpoint;
114 irqh->bkpt32 = DSBreakpoint;
115}
116
117void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
118 irqh->reset = DS9Reset;
119 irqh->processEvents = DSProcessEvents;
120 irqh->swi16 = NULL;
121 irqh->swi32 = NULL;
122 irqh->hitIllegal = DSIllegal;
123 irqh->readCPSR = DS9TestIRQ;
124 irqh->writeCP15 = DS9WriteCP15;
125 irqh->hitStub = DSHitStub;
126 irqh->bkpt16 = DSBreakpoint;
127 irqh->bkpt32 = DSBreakpoint;
128}
129
130void DS7Reset(struct ARMCore* cpu) {
131 ARMSetPrivilegeMode(cpu, MODE_IRQ);
132 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
133 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
134 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
135 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
136 cpu->gprs[ARM_SP] = DS7_SP_BASE;
137
138 struct DS* ds = (struct DS*) cpu->master;
139 DSMemoryReset(ds);
140
141 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
142 if (header) {
143 // TODO: Error check
144 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
145 uint32_t base = header->arm7Base - DS_BASE_RAM;
146 uint32_t* basePointer = &ds->memory.ram[base >> 2];
147 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
148 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
149 }
150 cpu->gprs[12] = header->arm7Entry;
151 cpu->gprs[ARM_LR] = header->arm7Entry;
152 cpu->gprs[ARM_PC] = header->arm7Entry;
153 int currentCycles = 0;
154 ARM_WRITE_PC;
155
156 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
157 }
158}
159
160void DS9Reset(struct ARMCore* cpu) {
161 ARMSetPrivilegeMode(cpu, MODE_IRQ);
162 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
163 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
164 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
165 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
166 cpu->gprs[ARM_SP] = DS9_SP_BASE;
167
168 struct DS* ds = (struct DS*) cpu->master;
169 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
170 if (header) {
171 // TODO: Error check
172 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
173 uint32_t base = header->arm9Base - DS_BASE_RAM;
174 uint32_t* basePointer = &ds->memory.ram[base >> 2];
175 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
176 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
177 }
178 cpu->gprs[12] = header->arm9Entry;
179 cpu->gprs[ARM_LR] = header->arm9Entry;
180 cpu->gprs[ARM_PC] = header->arm9Entry;
181 int currentCycles = 0;
182 ARM_WRITE_PC;
183
184 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
185 }
186}
187
188static void DSProcessEvents(struct ARMCore* cpu) {
189 struct DS* ds = (struct DS*) cpu->master;
190
191 if (ds->springIRQ7) {
192 ARMRaiseIRQ(cpu);
193 ds->springIRQ7 = 0;
194 }
195
196 do {
197 int32_t cycles = cpu->nextEvent;
198 int32_t nextEvent = INT_MAX;
199#ifndef NDEBUG
200 if (cycles < 0) {
201 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
202 }
203#endif
204
205 cpu->cycles -= cycles;
206 cpu->nextEvent = nextEvent;
207
208 if (cpu->halted) {
209 cpu->cycles = cpu->nextEvent;
210 }
211 } while (cpu->cycles >= cpu->nextEvent);
212}
213
214void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
215 ds->debugger = (struct ARMDebugger*) debugger->platform;
216}
217
218void DSDetachDebugger(struct DS* ds) {
219 ds->debugger = NULL;
220 ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
221 ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
222 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
223 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
224}
225
226bool DSLoadROM(struct DS* ds, struct VFile* vf) {
227 DSUnloadROM(ds);
228 ds->romVf = vf;
229 // TODO: error check
230 return true;
231}
232
233bool DSIsROM(struct VFile* vf) {
234 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
235 return false;
236 }
237 uint8_t signature[sizeof(DS_ROM_MAGIC)];
238 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
239 return false;
240 }
241 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
242}
243
244bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
245 size_t size = vf->size(vf);
246 void* data = NULL;
247 uint32_t crc;
248 if (size == DS7_SIZE_BIOS) {
249 data = vf->map(vf, size, MAP_READ);
250 } else if (size == 0x1000) {
251 data = vf->map(vf, size, MAP_READ);
252 }
253 if (!data) {
254 return false;
255 }
256 crc = doCrc32(data, size);
257 if (crc == DS7_BIOS_CHECKSUM) {
258 ds->bios7Vf = vf;
259 ds->memory.bios7 = data;
260 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
261 } else if (crc == DS9_BIOS_CHECKSUM) {
262 ds->bios9Vf = vf;
263 ds->memory.bios9 = data;
264 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
265 } else {
266 mLOG(DS, WARN, "BIOS checksum incorrect");
267 vf->unmap(vf, data, size);
268 return false;
269 }
270 return true;
271}
272
273void DSGetGameCode(struct DS* ds, char* out) {
274 memset(out, 0, 8);
275 if (!ds->romVf) {
276 return;
277 }
278
279 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
280 memcpy(out, "NTR-", 4);
281 memcpy(&out[4], &cart->id, 4);
282 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
283}
284
285void DSGetGameTitle(struct DS* ds, char* out) {
286 memset(out, 0, 12);
287 if (!ds->romVf) {
288 return;
289 }
290
291 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
292 memcpy(out, &cart->title, 4);
293 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
294}
295
296void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
297 struct DS* ds = (struct DS*) cpu->master;
298 if (ds->debugger) {
299 struct mDebuggerEntryInfo info = {
300 .address = _ARMPCAddress(cpu),
301 .opcode = opcode
302 };
303 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
304 }
305 // TODO: More sensible category?
306 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
307}
308
309void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
310 struct DS* ds = (struct DS*) cpu->master;
311 if (ds->debugger) {
312 struct mDebuggerEntryInfo info = {
313 .address = _ARMPCAddress(cpu),
314 .opcode = opcode
315 };
316 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
317 } else {
318 ARMRaiseUndefined(cpu);
319 }
320}
321
322void DSBreakpoint(struct ARMCore* cpu, int immediate) {
323 struct DS* ds = (struct DS*) cpu->master;
324 if (immediate >= CPU_COMPONENT_MAX) {
325 return;
326 }
327 switch (immediate) {
328 case CPU_COMPONENT_DEBUGGER:
329 if (ds->debugger) {
330 struct mDebuggerEntryInfo info = {
331 .address = _ARMPCAddress(cpu)
332 };
333 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
334 }
335 break;
336 default:
337 break;
338 }
339}
340
341void DS7TestIRQ(struct ARMCore* cpu) {
342 struct DS* ds = (struct DS*) cpu->master;
343 if (0) {
344 ds->springIRQ7 = 1;
345 cpu->nextEvent = cpu->cycles;
346 }
347}
348
349void DS9TestIRQ(struct ARMCore* cpu) {
350 struct DS* ds = (struct DS*) cpu->master;
351 if (0) {
352 ds->springIRQ9 = 1;
353 cpu->nextEvent = cpu->cycles;
354 }
355}
356
357static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
358 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
359}
360
361static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
362 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
363 switch (opcode2) {
364 case 0:
365 cpu->cp15.r2.d = value;
366 break;
367 case 1:
368 cpu->cp15.r2.i = value;
369 break;
370 default:
371 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
372 break;
373 }
374}
375
376static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
377 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
378 switch (opcode2) {
379 case 0:
380 cpu->cp15.r3.d = value;
381 break;
382 default:
383 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
384 break;
385 }
386}
387
388static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
389 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
390}
391
392static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
393 cpu->cp15.r6.region[crm] = value;
394 uint32_t base = ARMProtectionGetBase(value) << 12;
395 uint32_t size = 2 << ARMProtectionGetSize(value);
396 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
397}
398
399static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
400 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
401}
402
403static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
404 uint32_t base = ARMTCMControlGetBase(value) << 12;
405 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
406 mLOG(DS, STUB, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
407 switch (opcode2) {
408 case 0:
409 cpu->cp15.r9.d = value;
410 break;
411 case 1:
412 cpu->cp15.r9.i = value;
413 break;
414 default:
415 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
416 break;
417 }
418}
419
420void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
421 switch (crn) {
422 default:
423 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
424 break;
425 case 0:
426 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
427 ARMRaiseUndefined(cpu);
428 break;
429 case 1:
430 _writeSysControl(cpu, crm, opcode2, value);
431 break;
432 case 2:
433 _writeCacheControl(cpu, crm, opcode2, value);
434 break;
435 case 3:
436 _writeWriteBufferControl(cpu, crm, opcode2, value);
437 break;
438 case 5:
439 _writeAccessControl(cpu, crm, opcode2, value);
440 break;
441 case 6:
442 _writeRegionConfiguration(cpu, crm, opcode2, value);
443 break;
444 case 7:
445 _writeCache(cpu, crm, opcode2, value);
446 break;
447 case 9:
448 _writeTCMControl(cpu, crm, opcode2, value);
449 break;
450 }}