1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef DS_MEMORY_H
  7#define DS_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "arm/arm.h"
 12#include "core/log.h"
 13
 14enum DSMemoryRegion {
 15	DS7_REGION_BIOS = 0x0,
 16	DS9_REGION_ITCM = 0x0,
 17	DS9_REGION_ITCM_MIRROR = 0x1,
 18	DS_REGION_RAM = 0x2,
 19	DS_REGION_WORKING_RAM = 0x3,
 20	DS_REGION_IO = 0x4,
 21	DS9_REGION_PALETTE_RAM = 0x5,
 22	DS_REGION_VRAM = 0x6,
 23	DS9_REGION_OAM = 0x7,
 24	DS_REGION_SLOT2 = 0x8,
 25	DS_REGION_SLOT2_EX = 0x9,
 26	DS_REGION_SLOT2_SRAM = 0xA,
 27	DS9_REGION_BIOS = 0xFF,
 28};
 29
 30enum DSMemoryBase {
 31	DS7_BASE_BIOS = 0x00000000,
 32	DS9_BASE_ITCM = 0x00000000,
 33	DS_BASE_RAM = 0x02000000,
 34	DS_BASE_WORKING_RAM = 0x03000000,
 35	DS7_BASE_WORKING_RAM = 0x03800000,
 36	DS_BASE_IO = 0x04000000,
 37	DS9_BASE_PALETTE_RAM = 0x05000000,
 38	DS_BASE_VRAM = 0x06000000,
 39	DS9_BASE_OAM = 0x07000000,
 40	DS_BASE_SLOT2 = 0x08000000,
 41	DS_BASE_SLOT2_EX = 0x09000000,
 42	DS9_BASE_BIOS = 0xFFFF0000,
 43};
 44
 45enum {
 46	DS9_SIZE_ITCM = 0x00008000,
 47	DS9_SIZE_DTCM = 0x00004000,
 48	DS7_SIZE_BIOS = 0x00004000,
 49	DS9_SIZE_BIOS = 0x00008000,
 50	DS_SIZE_RAM = 0x00400000,
 51	DS_SIZE_WORKING_RAM = 0x00008000,
 52	DS7_SIZE_WORKING_RAM = 0x00010000,
 53	DS9_SIZE_PALETTE_RAM = 0x00000800,
 54	DS9_SIZE_OAM = 0x00000800,
 55	DS_SIZE_SLOT2 = 0x02000000,
 56	DS_SIZE_SLOT2_SRAM = 0x00010000,
 57};
 58
 59enum {
 60	DS_OFFSET_MASK = 0x00FFFFFF,
 61	DS_BASE_OFFSET = 24
 62};
 63
 64enum DSDMAControl {
 65	DS_DMA_INCREMENT = 0,
 66	DS_DMA_DECREMENT = 1,
 67	DS_DMA_FIXED = 2,
 68	DS_DMA_INCREMENT_RELOAD = 3
 69};
 70
 71enum DSDMATiming {
 72	DS_DMA_TIMING_NOW = 0,
 73	DS_DMA_TIMING_VBLANK = 1,
 74	DS_DMA_TIMING_HBLANK = 2,
 75	DS7_DMA_TIMING_SLOT1 = 2,
 76	DS_DMA_TIMING_DISPLAY_START = 3,
 77	DS7_DMA_TIMING_CUSTOM = 3,
 78	DS_DMA_TIMING_MEMORY_DISPLAY = 4,
 79	DS9_DMA_TIMING_SLOT1 = 5,
 80	DS_DMA_TIMING_SLOT2 = 6,
 81	DS_DMA_TIMING_GEOM_FIFO = 7,
 82};
 83
 84mLOG_DECLARE_CATEGORY(DS_MEM);
 85
 86DECL_BITFIELD(DSDMARegister, uint16_t);
 87DECL_BITS(DSDMARegister, DestControl, 5, 2);
 88DECL_BITS(DSDMARegister, SrcControl, 7, 2);
 89DECL_BIT(DSDMARegister, Repeat, 9);
 90DECL_BIT(DSDMARegister, Width, 10);
 91DECL_BITS(DSDMARegister, Timing7, 12, 2);
 92DECL_BITS(DSDMARegister, Timing9, 11, 3);
 93DECL_BIT(DSDMARegister, DoIRQ, 14);
 94DECL_BIT(DSDMARegister, Enable, 15);
 95
 96struct DSDMA {
 97	DSDMARegister reg;
 98
 99	uint32_t source;
100	uint32_t dest;
101	int32_t count;
102	uint32_t nextSource;
103	uint32_t nextDest;
104	int32_t nextCount;
105	int32_t nextEvent;
106};
107
108struct DSMemory {
109	uint32_t* bios7;
110	uint32_t* bios9;
111	uint32_t* itcm;
112	uint32_t* dtcm;
113	uint32_t* ram;
114	uint32_t* wram;
115	uint32_t* wram7;
116	uint32_t* rom;
117
118	size_t romSize;
119	size_t wramSize7;
120	size_t wramSize9;
121
122	char waitstatesSeq32[256];
123	char waitstatesSeq16[256];
124	char waitstatesNonseq32[256];
125	char waitstatesNonseq16[256];
126	char waitstatesPrefetchSeq32[16];
127	char waitstatesPrefetchSeq16[16];
128	char waitstatesPrefetchNonseq32[16];
129	char waitstatesPrefetchNonseq16[16];
130	int activeRegion7;
131	int activeRegion9;
132
133	struct DSDMA dma7[4];
134	struct DSDMA dma9[4];
135	int activeDMA7;
136	int activeDMA9;
137	int32_t nextDMA;
138	int32_t eventDiff;
139};
140
141struct DS;
142void DSMemoryInit(struct DS* ds);
143void DSMemoryDeinit(struct DS* ds);
144
145void DSMemoryReset(struct DS* ds);
146
147uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
148uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
149uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
150
151void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
152void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
153void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
154
155uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
156                         int* cycleCounter);
157uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
158                          int* cycleCounter);
159
160uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
161uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
162uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
163
164void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
165void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
166void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
167
168uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
169                         int* cycleCounter);
170uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
171                          int* cycleCounter);
172
173#endif