src/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
14 // TODO
15}
16
17static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
18 int rotate = (opcode & 0x00000F00) >> 7;
19 int immediate = opcode & 0x000000FF;
20 if (!rotate) {
21 cpu->shifterOperand = immediate;
22 cpu->shifterCarryOut = cpu->cpsr.c;
23 } else {
24 cpu->shifterOperand = ARM_ROR(immediate, rotate);
25 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
26 }
27}
28
29static const ARMInstruction _armTable[0x1000];
30
31static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
32 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
33 *opcodeOut = opcode;
34 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
35}
36
37void ARMStep(struct ARMCore* cpu) {
38 // TODO
39 uint32_t opcode;
40 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
41 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
42
43 int condition = opcode >> 28;
44 if (condition == 0xE) {
45 instruction(cpu, opcode);
46 return;
47 } else {
48 switch (condition) {
49 case 0x0:
50 if (!ARM_COND_EQ) {
51 return;
52 }
53 break;
54 case 0x1:
55 if (!ARM_COND_NE) {
56 return;
57 }
58 break;
59 case 0x2:
60 if (!ARM_COND_CS) {
61 return;
62 }
63 break;
64 case 0x3:
65 if (!ARM_COND_CC) {
66 return;
67 }
68 break;
69 case 0x4:
70 if (!ARM_COND_MI) {
71 return;
72 }
73 break;
74 case 0x5:
75 if (!ARM_COND_PL) {
76 return;
77 }
78 break;
79 case 0x6:
80 if (!ARM_COND_VS) {
81 return;
82 }
83 break;
84 case 0x7:
85 if (!ARM_COND_VC) {
86 return;
87 }
88 break;
89 case 0x8:
90 if (!ARM_COND_HI) {
91 return;
92 }
93 break;
94 case 0x9:
95 if (!ARM_COND_LS) {
96 return;
97 }
98 break;
99 case 0xA:
100 if (!ARM_COND_GE) {
101 return;
102 }
103 break;
104 case 0xB:
105 if (!ARM_COND_LT) {
106 return;
107 }
108 break;
109 case 0xC:
110 if (!ARM_COND_GT) {
111 return;
112 }
113 break;
114 case 0xD:
115 if (!ARM_COND_GE) {
116 return;
117 }
118 break;
119 default:
120 break;
121 }
122 }
123 instruction(cpu, opcode);
124}
125
126// Instruction definitions
127// Beware pre-processor antics
128
129#define ARM_WRITE_PC \
130 cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM) + WORD_SIZE_ARM; \
131 cpu->memory->setActiveRegion(cpu->memory, cpu->gprs[ARM_PC]);
132
133#define ARM_ADDITION_S(M, N, D) \
134 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
135 cpu->cpsr = cpu->spsr; \
136 _ARMReadCPSR(cpu); \
137 } else { \
138 cpu->cpsr.n = ARM_SIGN(D); \
139 cpu->cpsr.z = !(D); \
140 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
141 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
142 }
143
144#define ARM_SUBTRACTION_S(M, N, D) \
145 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
146 cpu->cpsr = cpu->spsr; \
147 _ARMReadCPSR(cpu); \
148 } else { \
149 cpu->cpsr.n = ARM_SIGN(D); \
150 cpu->cpsr.z = !(D); \
151 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
152 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
153 }
154
155#define ARM_NEUTRAL_S(M, N, D) \
156 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
157 cpu->cpsr = cpu->spsr; \
158 _ARMReadCPSR(cpu); \
159 } else { \
160 cpu->cpsr.n = ARM_SIGN(D); \
161 cpu->cpsr.z = !(D); \
162 cpu->cpsr.c = cpu->shifterCarryOut; \
163 }
164
165#define ADDR_MODE_2_ADDRESS (address)
166#define ADDR_MODE_2_RN (cpu->gprs[rn])
167#define ADDR_MODE_2_RM (cpu->gprs[rm])
168#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
169#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
170#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
171#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
172#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
173#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
174#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
175
176#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
177#define ADDR_MODE_3_RN ADDR_MODE_2_RN
178#define ADDR_MODE_3_RM ADDR_MODE_2_RM
179#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
180#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
181#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
182
183#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
184 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
185 BODY; \
186 }
187
188#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
189 DEFINE_INSTRUCTION_ARM(NAME, \
190 int rd = (opcode >> 12) & 0xF; \
191 int rn = (opcode >> 16) & 0xF; \
192 UNUSED(rn); \
193 SHIFTER(cpu, opcode); \
194 BODY; \
195 S_BODY; \
196 POST_BODY; \
197 if (rd == ARM_PC) { \
198 ARM_WRITE_PC; \
199 })
200
201#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
202 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
203 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
204 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
205 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
206
207#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY, POST_BODY) \
208 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, _barrelShift, BODY, POST_BODY) \
209 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY) \
210
211#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
212 DEFINE_INSTRUCTION_ARM(NAME, \
213 uint32_t address; \
214 int rn = (opcode >> 16) & 0xF; \
215 int rd = (opcode >> 12) & 0xF; \
216 int rm = opcode & 0xF; \
217 UNUSED(rm); \
218 address = ADDRESS; \
219 BODY; \
220 WRITEBACK;)
221
222#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
223 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
224 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
225 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
226 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
227 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
228 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
229
230#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
231 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
232 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
233 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
234 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
235 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
236 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
237 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
238 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
239 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
240 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
241
242#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
243 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
244 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
245 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
246 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
247 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
248 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
249 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
250 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
251 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
252 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
253 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
254 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
255
256#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
257 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
258 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
259
260#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
261 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
262 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
263 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
264 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
265 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
266 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
267
268// TODO
269#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
270 DEFINE_INSTRUCTION_ARM(NAME, \
271 BODY;)
272
273#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
274 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
275 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DAW, , , BODY) \
276 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , , BODY) \
277 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DBW, , , BODY) \
278 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , , BODY) \
279 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IAW, , , BODY) \
280 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , , BODY) \
281 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IBW, , , BODY) \
282 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, S_PRE, S_POST, BODY) \
283 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DAW, S_PRE, S_POST, BODY) \
284 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, S_PRE, S_POST, BODY) \
285 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DBW, S_PRE, S_POST, BODY) \
286 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, S_PRE, S_POST, BODY) \
287 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IAW, S_PRE, S_POST, BODY) \
288 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, S_PRE, S_POST, BODY) \
289 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IBW, S_PRE, S_POST, BODY)
290
291// Begin ALU definitions
292
293DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
294 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
295
296DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
297 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
298 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
299
300DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
301 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
302
303DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
304 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
305
306DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
307 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
308
309DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
310 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
311
312DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
313 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
314
315DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
316 cpu->gprs[rd] = cpu->shifterOperand;, )
317
318DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
319 cpu->gprs[rd] = ~cpu->shifterOperand;, )
320
321DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
322 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
323
324DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
325 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
326
327DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
328 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
329 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
330
331DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
332 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
333 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
334
335DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
336 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
337
338DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
339 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
340
341DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
342 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
343
344// End ALU definitions
345
346// Begin multiply definitions
347
348DEFINE_INSTRUCTION_ARM(MLA,)
349DEFINE_INSTRUCTION_ARM(MLAS,)
350DEFINE_INSTRUCTION_ARM(MUL,)
351DEFINE_INSTRUCTION_ARM(MULS,)
352DEFINE_INSTRUCTION_ARM(SMLAL,)
353DEFINE_INSTRUCTION_ARM(SMLALS,)
354DEFINE_INSTRUCTION_ARM(SMULL,)
355DEFINE_INSTRUCTION_ARM(SMULLS,)
356DEFINE_INSTRUCTION_ARM(UMLAL,)
357DEFINE_INSTRUCTION_ARM(UMLALS,)
358DEFINE_INSTRUCTION_ARM(UMULL,)
359DEFINE_INSTRUCTION_ARM(UMULLS,)
360
361// End multiply definitions
362
363// Begin load/store definitions
364
365DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
366DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
367DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
368DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
369DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
370DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
371DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
372DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
373
374DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, \
375 enum PrivilegeMode priv = cpu->privilegeMode; \
376 ARMSetPrivilegeMode(cpu, MODE_USER); \
377 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); \
378 ARMSetPrivilegeMode(cpu, priv);)
379
380DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, \
381 enum PrivilegeMode priv = cpu->privilegeMode; \
382 ARMSetPrivilegeMode(cpu, MODE_USER); \
383 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); \
384 ARMSetPrivilegeMode(cpu, priv);)
385
386DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, \
387 enum PrivilegeMode priv = cpu->privilegeMode; \
388 ARMSetPrivilegeMode(cpu, MODE_USER); \
389 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]); \
390 ARMSetPrivilegeMode(cpu, priv);)
391
392DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, \
393 enum PrivilegeMode priv = cpu->privilegeMode; \
394 ARMSetPrivilegeMode(cpu, MODE_USER); \
395 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]); \
396 ARMSetPrivilegeMode(cpu, priv);)
397
398DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,)
399DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,)
400
401DEFINE_INSTRUCTION_ARM(SWP,)
402DEFINE_INSTRUCTION_ARM(SWPB,)
403
404// End load/store definitions
405
406// Begin branch definitions
407
408DEFINE_INSTRUCTION_ARM(B, \
409 int32_t offset = opcode << 8; \
410 offset >>= 6; \
411 cpu->gprs[ARM_PC] += offset; \
412 ARM_WRITE_PC;)
413
414DEFINE_INSTRUCTION_ARM(BL,)
415DEFINE_INSTRUCTION_ARM(BX,)
416
417// End branch definitions
418
419// TODO
420DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
421
422DEFINE_INSTRUCTION_ARM(MSR, \
423 int c = opcode & 0x00010000; \
424 int f = opcode & 0x00080000; \
425 int32_t operand; \
426 if (opcode & 0x02000000) { \
427 int rotate = (opcode & 0x00000F00) >> 8; \
428 operand = ARM_ROR(opcode & 0x000000FF, rotate); \
429 } else { \
430 operand = cpu->gprs[opcode & 0x0000000F]; \
431 } \
432 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0); \
433 if (opcode & 0x00400000) { \
434 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK; \
435 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask); \
436 } else { \
437 if (mask & PSR_USER_MASK) { \
438 cpu->cpsr.n = operand & 0x80000000; \
439 cpu->cpsr.z = operand & 0x40000000; \
440 cpu->cpsr.c = operand & 0x20000000; \
441 cpu->cpsr.v = operand & 0x10000000; \
442 } \
443 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) { \
444 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010)); \
445 cpu->cpsr.priv = cpu->privilegeMode; \
446 cpu->cpsr.i = operand & 0x00000080; \
447 cpu->cpsr.f = operand & 0x00000040; \
448 } \
449 })
450
451DEFINE_INSTRUCTION_ARM(MRS,)
452DEFINE_INSTRUCTION_ARM(MSRI,)
453DEFINE_INSTRUCTION_ARM(MRSI,)
454DEFINE_INSTRUCTION_ARM(SWI,)
455
456#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
457 EMITTER ## NAME
458
459#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
460 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
461 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
462
463#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
464 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU)), \
465 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
466 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
467 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
468 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
469 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
470 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
471 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
472 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
473
474#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
475 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
476 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
477
478#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
479 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
480 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
481 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
482 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
483 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
484 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
485 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
486 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
487 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
488 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
489 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
490 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
491 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
492 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
493 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
494 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
495
496#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
497 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
498 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
499
500#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
501 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
502
503// TODO: Support coprocessors
504#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
505 DO_8(0), \
506 DO_8(0)
507
508#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
509 DO_8(DO_8(DO_INTERLACE(0, 0))), \
510 DO_8(DO_8(DO_INTERLACE(0, 0)))
511
512#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
513 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
514
515#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
516 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
517 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
518 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
519 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
520 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
521 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
522 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
523 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
524 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
525 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
526 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
527 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
528 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
529 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
530 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
531 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
532 DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWP, STRHP, ILL, ILL), \
533 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
534 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
535 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
536 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
537 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
538 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
539 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
540 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
541 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
542 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
543 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
544 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
545 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
546 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
547 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
548 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
549 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
550 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
551 DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWPB, STRHIP, ILL, ILL), \
552 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
553 DECLARE_ARM_ALU_BLOCK(EMITTER, MSR, ILL, STRHIPW, ILL, ILL), \
554 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
555 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
556 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
557 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
558 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
559 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
560 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
561 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
562 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
563 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
564 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
565 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
566 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
567 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
568 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
569 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
570 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
571 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
572 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
573 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
574 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
575 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
576 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
577 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
578 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
579 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
580 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
581 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
582 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
583 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
584 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
585 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
586 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
587 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
588 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
589 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
590 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
591 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
592 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
593 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
594 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
595 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
596 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
597 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
598 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
599 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
600 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
601 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
602 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
603 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
604 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
605 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
606 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
607 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
608 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
609 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
610 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
611 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
612 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
613 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
614 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
615 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
616 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
617 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
618 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
619 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
620 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
621 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
622 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
623 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
624 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
625 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
626 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
627 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
628 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
629 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
630 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
631 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
632 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
633 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
634 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
635 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
636 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
637 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
638 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
639 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
640 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
641 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
642 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
643 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
644 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
645 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
646 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
647 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
648 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
649 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
650 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
651 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
652 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
653 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
654 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
655 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
656 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
657 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
658 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
659 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
660 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
661 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
662 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
663 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
664 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
665 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
666 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
667 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
668 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
669 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
670 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
671 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
672 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
673 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
674 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
675 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
676 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
677 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
678 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
679 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
680 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
681 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
682 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
683 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
684 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
685 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
686 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
687 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
688 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
689 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
690 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
691 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
692 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
693 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
694 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
695 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
696 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
697 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
698 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
699 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
700 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
701 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
702 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
703 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
704 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
705 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
706 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
707 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
708 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
709 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
710 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
711 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
712 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
713 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
714 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
715 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
716 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
717 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
718 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
719 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
720 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
721 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
722 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
723 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
724 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
725 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
726 DECLARE_ARM_SWI_BLOCK(EMITTER)
727
728static const ARMInstruction _armTable[0x1000] = {
729 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
730};