src/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
14 int rm = opcode & 0x0000000F;
15 int immediate = (opcode & 0x00000F80) >> 7;
16 if (!immediate) {
17 cpu->shifterOperand = cpu->gprs[rm];
18 cpu->shifterCarryOut = cpu->cpsr.c;
19 } else {
20 cpu->shifterOperand = cpu->gprs[rm] << immediate;
21 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (32 - immediate));
22 }
23}
24
25static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
26 int rm = opcode & 0x0000000F;
27 ARM_STUB;
28}
29
30static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
31 int rm = opcode & 0x0000000F;
32 int immediate = (opcode & 0x00000F80) >> 7;
33 if (immediate) {
34 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
35 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
36 } else {
37 cpu->shifterOperand = 0;
38 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
39 }
40}
41
42static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
43 int rm = opcode & 0x0000000F;
44 ARM_STUB;
45}
46
47static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
48 int rm = opcode & 0x0000000F;
49 int immediate = (opcode & 0x00000F80) >> 7;
50 if (immediate) {
51 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
52 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
53 } else {
54 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
55 cpu->shifterOperand = cpu->shifterCarryOut >> 31; // Ensure sign extension
56 }
57}
58
59static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
60 int rm = opcode & 0x0000000F;
61 ARM_STUB;
62}
63
64static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
65 int rm = opcode & 0x0000000F;
66 int immediate = (opcode & 0x00000F80) >> 7;
67 ARM_STUB;
68}
69
70static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
71 int rm = opcode & 0x0000000F;
72 ARM_STUB;
73}
74
75static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
76 int rotate = (opcode & 0x00000F00) >> 7;
77 int immediate = opcode & 0x000000FF;
78 if (!rotate) {
79 cpu->shifterOperand = immediate;
80 cpu->shifterCarryOut = cpu->cpsr.c;
81 } else {
82 cpu->shifterOperand = ARM_ROR(immediate, rotate);
83 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
84 }
85}
86
87static const ARMInstruction _armTable[0x1000];
88
89static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
90 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
91 *opcodeOut = opcode;
92 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
93}
94
95void ARMStep(struct ARMCore* cpu) {
96 // TODO
97 uint32_t opcode;
98 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
99 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
100
101 int condition = opcode >> 28;
102 if (condition == 0xE) {
103 instruction(cpu, opcode);
104 return;
105 } else {
106 switch (condition) {
107 case 0x0:
108 if (!ARM_COND_EQ) {
109 return;
110 }
111 break;
112 case 0x1:
113 if (!ARM_COND_NE) {
114 return;
115 }
116 break;
117 case 0x2:
118 if (!ARM_COND_CS) {
119 return;
120 }
121 break;
122 case 0x3:
123 if (!ARM_COND_CC) {
124 return;
125 }
126 break;
127 case 0x4:
128 if (!ARM_COND_MI) {
129 return;
130 }
131 break;
132 case 0x5:
133 if (!ARM_COND_PL) {
134 return;
135 }
136 break;
137 case 0x6:
138 if (!ARM_COND_VS) {
139 return;
140 }
141 break;
142 case 0x7:
143 if (!ARM_COND_VC) {
144 return;
145 }
146 break;
147 case 0x8:
148 if (!ARM_COND_HI) {
149 return;
150 }
151 break;
152 case 0x9:
153 if (!ARM_COND_LS) {
154 return;
155 }
156 break;
157 case 0xA:
158 if (!ARM_COND_GE) {
159 return;
160 }
161 break;
162 case 0xB:
163 if (!ARM_COND_LT) {
164 return;
165 }
166 break;
167 case 0xC:
168 if (!ARM_COND_GT) {
169 return;
170 }
171 break;
172 case 0xD:
173 if (!ARM_COND_GE) {
174 return;
175 }
176 break;
177 default:
178 break;
179 }
180 }
181 instruction(cpu, opcode);
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187#define ARM_ADDITION_S(M, N, D) \
188 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
189 cpu->cpsr = cpu->spsr; \
190 _ARMReadCPSR(cpu); \
191 } else { \
192 cpu->cpsr.n = ARM_SIGN(D); \
193 cpu->cpsr.z = !(D); \
194 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
195 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
196 }
197
198#define ARM_SUBTRACTION_S(M, N, D) \
199 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
200 cpu->cpsr = cpu->spsr; \
201 _ARMReadCPSR(cpu); \
202 } else { \
203 cpu->cpsr.n = ARM_SIGN(D); \
204 cpu->cpsr.z = !(D); \
205 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
206 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
207 }
208
209#define ARM_NEUTRAL_S(M, N, D) \
210 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
211 cpu->cpsr = cpu->spsr; \
212 _ARMReadCPSR(cpu); \
213 } else { \
214 cpu->cpsr.n = ARM_SIGN(D); \
215 cpu->cpsr.z = !(D); \
216 cpu->cpsr.c = cpu->shifterCarryOut; \
217 }
218
219#define ADDR_MODE_2_ADDRESS (address)
220#define ADDR_MODE_2_RN (cpu->gprs[rn])
221#define ADDR_MODE_2_RM (cpu->gprs[rm])
222#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
223#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
224#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
225#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
226#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
227#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
228#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
229
230#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
231#define ADDR_MODE_3_RN ADDR_MODE_2_RN
232#define ADDR_MODE_3_RM ADDR_MODE_2_RM
233#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
234#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
235#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
236
237#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
238 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
239 BODY; \
240 }
241
242#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
243 DEFINE_INSTRUCTION_ARM(NAME, \
244 int rd = (opcode >> 12) & 0xF; \
245 int rn = (opcode >> 16) & 0xF; \
246 UNUSED(rn); \
247 SHIFTER(cpu, opcode); \
248 BODY; \
249 S_BODY; \
250 POST_BODY; \
251 if (rd == ARM_PC) { \
252 ARM_WRITE_PC; \
253 })
254
255#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
256 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY, POST_BODY) \
257 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
258 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY, POST_BODY) \
259 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
260 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY, POST_BODY) \
261 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
262 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY, POST_BODY) \
263 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
264 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY, POST_BODY) \
265 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
266 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY, POST_BODY) \
267 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
268 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY, POST_BODY) \
269 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
270 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY, POST_BODY) \
271 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
272 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
273 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
274
275#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY, POST_BODY) \
276 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
277 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
278 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
279 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
280 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
281 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
282 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
283 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
284 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY)
285
286#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
287 DEFINE_INSTRUCTION_ARM(NAME, \
288 uint32_t address; \
289 int rn = (opcode >> 16) & 0xF; \
290 int rd = (opcode >> 12) & 0xF; \
291 int rm = opcode & 0xF; \
292 UNUSED(rm); \
293 address = ADDRESS; \
294 BODY; \
295 WRITEBACK;)
296
297#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
298 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
299 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
300 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
301 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
302 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
303 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
304
305#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
306 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
307 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
308 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
309 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
310 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
311 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
312 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
313 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
314 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
315 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
316
317#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
318 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
319 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
320 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
321 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
322 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
323 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
324 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
325 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
326 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
327 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
328 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
329 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
330
331#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
332 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
333 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
334
335#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
336 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
337 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
338 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
339 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
340 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
341 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
342
343// TODO
344#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
345 DEFINE_INSTRUCTION_ARM(NAME, \
346 BODY;)
347
348#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
349 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
350 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DAW, , , BODY) \
351 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , , BODY) \
352 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DBW, , , BODY) \
353 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , , BODY) \
354 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IAW, , , BODY) \
355 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , , BODY) \
356 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IBW, , , BODY) \
357 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, S_PRE, S_POST, BODY) \
358 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DAW, S_PRE, S_POST, BODY) \
359 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, S_PRE, S_POST, BODY) \
360 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DBW, S_PRE, S_POST, BODY) \
361 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, S_PRE, S_POST, BODY) \
362 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IAW, S_PRE, S_POST, BODY) \
363 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, S_PRE, S_POST, BODY) \
364 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IBW, S_PRE, S_POST, BODY)
365
366// Begin ALU definitions
367
368DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
369 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
370
371DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
372 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
373 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
374
375DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
376 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
377
378DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
379 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
380
381DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
382 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
383
384DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
385 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
386
387DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
388 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
389
390DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
391 cpu->gprs[rd] = cpu->shifterOperand;, )
392
393DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
394 cpu->gprs[rd] = ~cpu->shifterOperand;, )
395
396DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
397 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
398
399DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
400 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
401
402DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
403 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
404 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
405
406DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
407 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
408 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
409
410DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
411 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
412
413DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
414 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
415
416DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
417 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
418
419// End ALU definitions
420
421// Begin multiply definitions
422
423DEFINE_INSTRUCTION_ARM(MLA, ARM_STUB)
424DEFINE_INSTRUCTION_ARM(MLAS, ARM_STUB)
425DEFINE_INSTRUCTION_ARM(MUL, ARM_STUB)
426DEFINE_INSTRUCTION_ARM(MULS, ARM_STUB)
427DEFINE_INSTRUCTION_ARM(SMLAL, ARM_STUB)
428DEFINE_INSTRUCTION_ARM(SMLALS, ARM_STUB)
429DEFINE_INSTRUCTION_ARM(SMULL, ARM_STUB)
430DEFINE_INSTRUCTION_ARM(SMULLS, ARM_STUB)
431DEFINE_INSTRUCTION_ARM(UMLAL, ARM_STUB)
432DEFINE_INSTRUCTION_ARM(UMLALS, ARM_STUB)
433DEFINE_INSTRUCTION_ARM(UMULL, ARM_STUB)
434DEFINE_INSTRUCTION_ARM(UMULLS, ARM_STUB)
435
436// End multiply definitions
437
438// Begin load/store definitions
439
440DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
441DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
442DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
443DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
444DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
445DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
446DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
447DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
448
449DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, \
450 enum PrivilegeMode priv = cpu->privilegeMode; \
451 ARMSetPrivilegeMode(cpu, MODE_USER); \
452 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); \
453 ARMSetPrivilegeMode(cpu, priv);)
454
455DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, \
456 enum PrivilegeMode priv = cpu->privilegeMode; \
457 ARMSetPrivilegeMode(cpu, MODE_USER); \
458 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); \
459 ARMSetPrivilegeMode(cpu, priv);)
460
461DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, \
462 enum PrivilegeMode priv = cpu->privilegeMode; \
463 ARMSetPrivilegeMode(cpu, MODE_USER); \
464 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]); \
465 ARMSetPrivilegeMode(cpu, priv);)
466
467DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, \
468 enum PrivilegeMode priv = cpu->privilegeMode; \
469 ARMSetPrivilegeMode(cpu, MODE_USER); \
470 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]); \
471 ARMSetPrivilegeMode(cpu, priv);)
472
473DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM, ARM_STUB)
474DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, ARM_STUB)
475
476DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
477DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
478
479// End load/store definitions
480
481// Begin branch definitions
482
483DEFINE_INSTRUCTION_ARM(B, \
484 int32_t offset = opcode << 8; \
485 offset >>= 6; \
486 cpu->gprs[ARM_PC] += offset; \
487 ARM_WRITE_PC;)
488
489DEFINE_INSTRUCTION_ARM(BL, ARM_STUB)
490DEFINE_INSTRUCTION_ARM(BX, \
491 int rm = opcode & 0x0000000F; \
492 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001); \
493 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE; \
494 if (cpu->executionMode == MODE_THUMB) { \
495 THUMB_WRITE_PC;
496 } else { \
497 ARM_WRITE_PC; \
498 })
499
500// End branch definitions
501
502// Begin miscellaneous definitions
503
504DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
505DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
506
507DEFINE_INSTRUCTION_ARM(MSR, \
508 int c = opcode & 0x00010000; \
509 int f = opcode & 0x00080000; \
510 int32_t operand; \
511 if (opcode & 0x02000000) { \
512 int rotate = (opcode & 0x00000F00) >> 8; \
513 operand = ARM_ROR(opcode & 0x000000FF, rotate); \
514 } else { \
515 operand = cpu->gprs[opcode & 0x0000000F]; \
516 } \
517 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0); \
518 if (opcode & 0x00400000) { \
519 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK; \
520 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask); \
521 } else { \
522 if (mask & PSR_USER_MASK) { \
523 cpu->cpsr.n = operand & 0x80000000; \
524 cpu->cpsr.z = operand & 0x40000000; \
525 cpu->cpsr.c = operand & 0x20000000; \
526 cpu->cpsr.v = operand & 0x10000000; \
527 } \
528 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) { \
529 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010)); \
530 cpu->cpsr.priv = cpu->privilegeMode; \
531 cpu->cpsr.i = operand & 0x00000080; \
532 cpu->cpsr.f = operand & 0x00000040; \
533 } \
534 })
535
536DEFINE_INSTRUCTION_ARM(MRS, ARM_STUB)
537DEFINE_INSTRUCTION_ARM(MSRI, ARM_STUB)
538DEFINE_INSTRUCTION_ARM(MRSI, ARM_STUB)
539DEFINE_INSTRUCTION_ARM(SWI, ARM_STUB)
540
541#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
542 EMITTER ## NAME
543
544#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
545 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
546 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
547
548#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
549 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
550 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
551 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
552 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
553 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
554 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
555 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
556 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
557 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
558 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
559 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
560 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
561 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
562 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
563 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
564 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
565
566#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
567 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
568 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
569
570#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
571 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
572 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
573 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
574 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
575 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
576 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
577 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
578 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
579 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
580 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
581 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
582 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
583 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
584 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
585 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
586 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
587
588#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
589 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
590 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
591
592#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
593 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
594
595// TODO: Support coprocessors
596#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
597 DO_8(0), \
598 DO_8(0)
599
600#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
601 DO_8(DO_8(DO_INTERLACE(0, 0))), \
602 DO_8(DO_8(DO_INTERLACE(0, 0)))
603
604#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
605 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
606
607#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
608 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
609 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
610 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
611 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
612 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
613 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
614 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
615 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
616 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
617 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
618 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
619 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
620 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
621 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
622 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
623 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
624 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
625 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
626 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
627 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
628 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
629 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
630 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
631 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
632 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
633 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
634 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
635 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
636 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
637 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
638 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
639 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
640 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
641 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
642 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
643 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
644 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
645 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
646 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
647 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
648 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
649 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
650 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
651 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
652 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
653 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
654 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
655 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
656 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
657 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
658 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
659 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
660 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
661 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
662 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
663 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
664 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
665 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
666 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
667 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
668 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
669 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
670 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
671 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
672 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
673 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
674 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
675 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
676 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
677 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
678 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
679 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
680 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
681 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
682 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
683 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
684 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
685 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
686 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
687 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
688 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
689 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
690 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
691 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
692 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
693 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
694 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
695 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
696 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
697 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
698 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
699 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
700 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
701 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
702 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
703 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
704 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
705 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
706 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
707 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
708 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
709 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
710 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
711 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
712 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
713 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
714 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
715 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
716 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
717 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
718 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
719 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
720 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
721 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
722 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
723 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
724 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
725 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
726 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
727 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
728 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
729 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
730 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
731 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
732 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
733 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
734 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
735 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
736 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
737 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
738 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
739 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
740 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
741 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
742 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
743 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
744 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
745 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
746 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
747 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
748 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
749 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
750 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
751 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
752 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
753 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
754 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
755 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
756 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
757 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
758 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
759 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
760 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
761 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
762 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
763 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
764 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
765 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
766 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
767 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
768 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
769 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
770 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
771 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
772 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
773 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
774 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
775 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
776 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
777 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
778 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
779 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
780 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
781 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
782 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
783 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
784 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
785 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
786 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
787 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
788 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
789 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
790 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
791 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
792 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
793 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
794 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
795 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
796 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
797 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
798 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
799 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
800 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
801 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
802 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
803 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
804 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
805 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
806 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
807 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
808 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
809 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
810 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
811 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
812 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
813 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
814 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
815 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
816 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
817 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
818 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
819 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
820 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
821 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
822 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
823 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
824 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
825 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
826 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
827 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
828 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
829 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
830 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
831 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
832 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
833 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
834 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
835 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
836 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
837 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
838 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
839 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
840 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
841 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
842 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
843 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
844 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
845 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
846 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
847 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
848 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
849 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
850 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
851 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
852 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
853 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
854 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
855 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
856 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
857 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
858 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
859 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
860 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
861 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
862 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
863 DECLARE_ARM_SWI_BLOCK(EMITTER)
864
865static const ARMInstruction _armTable[0x1000] = {
866 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
867};