src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "ds.h"
7
8#include "arm/decoder.h"
9#include "arm/debugger/debugger.h"
10#include "arm/isa-inlines.h"
11#include "ds/bios.h"
12
13#include "util/crc32.h"
14#include "util/memory.h"
15#include "util/math.h"
16#include "util/vfs.h"
17
18mLOG_DEFINE_CATEGORY(DS, "DS");
19
20const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
21const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
22const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
23
24static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
25static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
26
27enum {
28 DS7_SP_BASE = 0x380FD80,
29 DS7_SP_BASE_IRQ = 0x380FF80,
30 DS7_SP_BASE_SVC = 0x380FFC0,
31
32 DS9_SP_BASE = 0x3002F7C,
33 DS9_SP_BASE_IRQ = 0x3003F80,
34 DS9_SP_BASE_SVC = 0x3003FC0,
35};
36
37static void DSInit(void* cpu, struct mCPUComponent* component);
38
39static void DS7Reset(struct ARMCore* cpu);
40static void DS7TestIRQ(struct ARMCore* cpu);
41static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
42
43static void DS9Reset(struct ARMCore* cpu);
44static void DS9TestIRQ(struct ARMCore* cpu);
45static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
46static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
47
48static void DSProcessEvents(struct ARMCore* cpu);
49static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
50static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
51static void DSBreakpoint(struct ARMCore* cpu, int immediate);
52
53void DSCreate(struct DS* ds) {
54 ds->d.id = DS_COMPONENT_MAGIC;
55 ds->d.init = DSInit;
56 ds->d.deinit = NULL;
57 ds->arm7 = NULL;
58 ds->arm9 = NULL;
59}
60
61static void DSInit(void* cpu, struct mCPUComponent* component) {
62 struct DS* ds = (struct DS*) component;
63 struct ARMCore* core = cpu;
64 if (!ds->arm7) {
65 // The ARM7 must get initialized first
66 ds->arm7 = core;
67 ds->debugger = 0;
68 ds->sync = 0;
69 return;
70 }
71 ds->arm9 = cpu;
72
73 ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
74
75 DS7InterruptHandlerInit(&ds->arm7->irqh);
76 DS9InterruptHandlerInit(&ds->arm9->irqh);
77 DSMemoryInit(ds);
78
79 ds->video.p = ds;
80
81 ds->springIRQ7 = 0;
82 ds->springIRQ9 = 0;
83 ds->keySource = NULL;
84 ds->rtcSource = NULL;
85 ds->rumble = NULL;
86
87 ds->romVf = NULL;
88
89 ds->keyCallback = NULL;
90}
91
92void DSUnloadROM(struct DS* ds) {
93 if (ds->romVf) {
94 ds->romVf->close(ds->romVf);
95 ds->romVf = NULL;
96 }
97}
98
99void DSDestroy(struct DS* ds) {
100 DSUnloadROM(ds);
101 DSMemoryDeinit(ds);
102}
103
104void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
105 irqh->reset = DS7Reset;
106 irqh->processEvents = DSProcessEvents;
107 irqh->swi16 = NULL;
108 irqh->swi32 = NULL;
109 irqh->hitIllegal = DSIllegal;
110 irqh->readCPSR = DS7TestIRQ;
111 irqh->writeCP15 = NULL;
112 irqh->hitStub = DSHitStub;
113 irqh->bkpt16 = DSBreakpoint;
114 irqh->bkpt32 = DSBreakpoint;
115}
116
117void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
118 irqh->reset = DS9Reset;
119 irqh->processEvents = DSProcessEvents;
120 irqh->swi16 = NULL;
121 irqh->swi32 = NULL;
122 irqh->hitIllegal = DSIllegal;
123 irqh->readCPSR = DS9TestIRQ;
124 irqh->writeCP15 = DS9WriteCP15;
125 irqh->hitStub = DSHitStub;
126 irqh->bkpt16 = DSBreakpoint;
127 irqh->bkpt32 = DSBreakpoint;
128}
129
130void DS7Reset(struct ARMCore* cpu) {
131 ARMSetPrivilegeMode(cpu, MODE_IRQ);
132 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
133 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
134 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
135 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
136 cpu->gprs[ARM_SP] = DS7_SP_BASE;
137
138 struct DS* ds = (struct DS*) cpu->master;
139 DSMemoryReset(ds);
140
141 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
142 if (header) {
143 // TODO: Error check
144 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
145 uint32_t base = header->arm7Base - DS_BASE_RAM;
146 uint32_t* basePointer = &ds->memory.ram[base >> 2];
147 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
148 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
149 }
150 cpu->gprs[12] = header->arm7Entry;
151 cpu->gprs[ARM_LR] = header->arm7Entry;
152 cpu->gprs[ARM_PC] = header->arm7Entry;
153 int currentCycles = 0;
154 ARM_WRITE_PC;
155
156 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
157 }
158}
159
160void DS9Reset(struct ARMCore* cpu) {
161 ARMSetPrivilegeMode(cpu, MODE_IRQ);
162 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
163 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
164 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
165 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
166 cpu->gprs[ARM_SP] = DS9_SP_BASE;
167
168 struct DS* ds = (struct DS*) cpu->master;
169 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
170 if (header) {
171 // TODO: Error check
172 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
173 uint32_t base = header->arm9Base - DS_BASE_RAM;
174 uint32_t* basePointer = &ds->memory.ram[base >> 2];
175 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
176 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
177 }
178 cpu->gprs[12] = header->arm9Entry;
179 cpu->gprs[ARM_LR] = header->arm9Entry;
180 cpu->gprs[ARM_PC] = header->arm9Entry;
181 int currentCycles = 0;
182 ARM_WRITE_PC;
183
184 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
185 }
186}
187
188static void DSProcessEvents(struct ARMCore* cpu) {
189 struct DS* ds = (struct DS*) cpu->master;
190
191 if (ds->springIRQ7) {
192 ARMRaiseIRQ(cpu);
193 ds->springIRQ7 = 0;
194 }
195
196 do {
197 int32_t cycles = cpu->nextEvent;
198 int32_t nextEvent = INT_MAX;
199#ifndef NDEBUG
200 if (cycles < 0) {
201 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
202 }
203#endif
204
205 cpu->cycles -= cycles;
206 cpu->nextEvent = nextEvent;
207
208 if (cpu->halted) {
209 cpu->cycles = cpu->nextEvent;
210 }
211 } while (cpu->cycles >= cpu->nextEvent);
212}
213
214void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
215 ds->debugger = (struct ARMDebugger*) debugger->platform;
216 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
217 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
218 ARMHotplugAttach(ds->arm7, CPU_COMPONENT_DEBUGGER);
219 ARMHotplugAttach(ds->arm9, CPU_COMPONENT_DEBUGGER);
220}
221
222
223void DSDetachDebugger(struct DS* ds) {
224 ds->debugger = NULL;
225 ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
226 ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
227 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
228 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
229}
230
231bool DSLoadROM(struct DS* ds, struct VFile* vf) {
232 DSUnloadROM(ds);
233 ds->romVf = vf;
234 // TODO: error check
235 return true;
236}
237
238bool DSIsROM(struct VFile* vf) {
239 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
240 return false;
241 }
242 uint8_t signature[sizeof(DS_ROM_MAGIC)];
243 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
244 return false;
245 }
246 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
247}
248
249bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
250 size_t size = vf->size(vf);
251 void* data = NULL;
252 uint32_t crc;
253 if (size == DS7_SIZE_BIOS) {
254 data = vf->map(vf, size, MAP_READ);
255 } else if (size == 0x1000) {
256 data = vf->map(vf, size, MAP_READ);
257 }
258 if (!data) {
259 return false;
260 }
261 crc = doCrc32(data, size);
262 if (crc == DS7_BIOS_CHECKSUM) {
263 ds->bios7Vf = vf;
264 ds->memory.bios7 = data;
265 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
266 } else if (crc == DS9_BIOS_CHECKSUM) {
267 ds->bios9Vf = vf;
268 ds->memory.bios9 = data;
269 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
270 } else {
271 mLOG(DS, WARN, "BIOS checksum incorrect");
272 vf->unmap(vf, data, size);
273 return false;
274 }
275 return true;
276}
277
278void DSGetGameCode(struct DS* ds, char* out) {
279 memset(out, 0, 8);
280 if (!ds->romVf) {
281 return;
282 }
283
284 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
285 memcpy(out, "NTR-", 4);
286 memcpy(&out[4], &cart->id, 4);
287 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
288}
289
290void DSGetGameTitle(struct DS* ds, char* out) {
291 memset(out, 0, 12);
292 if (!ds->romVf) {
293 return;
294 }
295
296 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
297 memcpy(out, &cart->title, 4);
298 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
299}
300
301void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
302 struct DS* ds = (struct DS*) cpu->master;
303 if (ds->debugger) {
304 struct mDebuggerEntryInfo info = {
305 .address = _ARMPCAddress(cpu),
306 .opcode = opcode
307 };
308 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
309 }
310 // TODO: More sensible category?
311 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
312}
313
314void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
315 struct DS* ds = (struct DS*) cpu->master;
316 if (ds->debugger) {
317 struct mDebuggerEntryInfo info = {
318 .address = _ARMPCAddress(cpu),
319 .opcode = opcode
320 };
321 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
322 } else {
323 ARMRaiseUndefined(cpu);
324 }
325}
326
327void DSBreakpoint(struct ARMCore* cpu, int immediate) {
328 struct DS* ds = (struct DS*) cpu->master;
329 if (immediate >= CPU_COMPONENT_MAX) {
330 return;
331 }
332 switch (immediate) {
333 case CPU_COMPONENT_DEBUGGER:
334 if (ds->debugger) {
335 struct mDebuggerEntryInfo info = {
336 .address = _ARMPCAddress(cpu)
337 };
338 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
339 }
340 break;
341 default:
342 break;
343 }
344}
345
346void DS7TestIRQ(struct ARMCore* cpu) {
347 struct DS* ds = (struct DS*) cpu->master;
348 if (0) {
349 ds->springIRQ7 = 1;
350 cpu->nextEvent = cpu->cycles;
351 }
352}
353
354void DS9TestIRQ(struct ARMCore* cpu) {
355 struct DS* ds = (struct DS*) cpu->master;
356 if (0) {
357 ds->springIRQ9 = 1;
358 cpu->nextEvent = cpu->cycles;
359 }
360}
361
362static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
363 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
364}
365
366static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
367 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
368 switch (opcode2) {
369 case 0:
370 cpu->cp15.r2.d = value;
371 break;
372 case 1:
373 cpu->cp15.r2.i = value;
374 break;
375 default:
376 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
377 break;
378 }
379}
380
381static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
382 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
383 switch (opcode2) {
384 case 0:
385 cpu->cp15.r3.d = value;
386 break;
387 default:
388 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
389 break;
390 }
391}
392
393static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
394 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
395}
396
397static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
398 cpu->cp15.r6.region[crm] = value;
399 uint32_t base = ARMProtectionGetBase(value) << 12;
400 uint32_t size = 2 << ARMProtectionGetSize(value);
401 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
402}
403
404static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
405 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
406}
407
408static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
409 uint32_t base = ARMTCMControlGetBase(value) << 12;
410 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
411 mLOG(DS, STUB, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
412 switch (opcode2) {
413 case 0:
414 cpu->cp15.r9.d = value;
415 break;
416 case 1:
417 cpu->cp15.r9.i = value;
418 break;
419 default:
420 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
421 break;
422 }
423}
424
425void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
426 switch (crn) {
427 default:
428 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
429 break;
430 case 0:
431 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
432 ARMRaiseUndefined(cpu);
433 break;
434 case 1:
435 _writeSysControl(cpu, crm, opcode2, value);
436 break;
437 case 2:
438 _writeCacheControl(cpu, crm, opcode2, value);
439 break;
440 case 3:
441 _writeWriteBufferControl(cpu, crm, opcode2, value);
442 break;
443 case 5:
444 _writeAccessControl(cpu, crm, opcode2, value);
445 break;
446 case 6:
447 _writeRegionConfiguration(cpu, crm, opcode2, value);
448 break;
449 case 7:
450 _writeCache(cpu, crm, opcode2, value);
451 break;
452 case 9:
453 _writeTCMControl(cpu, crm, opcode2, value);
454 break;
455 }}