1#ifndef GBA_MEMORY_H
  2#define GBA_MEMORY_H
  3
  4#include "arm.h"
  5
  6enum GBAMemoryRegion {
  7	REGION_BIOS = 0x0,
  8	REGION_WORKING_RAM = 0x2,
  9	REGION_WORKING_IRAM = 0x3,
 10	REGION_IO = 0x4,
 11	REGION_PALETTE_RAM = 0x5,
 12	REGION_VRAM = 0x6,
 13	REGION_OAM = 0x7,
 14	REGION_CART0 = 0x8,
 15	REGION_CART0_EX = 0x9,
 16	REGION_CART1 = 0xA,
 17	REGION_CART1_EX = 0xB,
 18	REGION_CART2 = 0xC,
 19	REGION_CART2_EX = 0xD,
 20	REGION_CART_SRAM = 0xE
 21};
 22
 23enum GBAMemoryBase {
 24	BASE_BIOS = 0x00000000,
 25	BASE_WORKING_RAM = 0x02000000,
 26	BASE_WORKING_IRAM = 0x03000000,
 27	BASE_IO = 0x04000000,
 28	BASE_PALETTE_RAM = 0x05000000,
 29	BASE_VRAM = 0x06000000,
 30	BASE_OAM = 0x07000000,
 31	BASE_CART0 = 0x08000000,
 32	BASE_CART0_EX = 0x09000000,
 33	BASE_CART1 = 0x0A000000,
 34	BASE_CART1_EX = 0x0B000000,
 35	BASE_CART2 = 0x0C000000,
 36	BASE_CART2_EX = 0x0D000000,
 37	BASE_CART_SRAM = 0x0E000000
 38};
 39
 40enum {
 41	SIZE_BIOS = 0x00004000,
 42	SIZE_WORKING_RAM = 0x00040000,
 43	SIZE_WORKING_IRAM = 0x00008000,
 44	SIZE_IO = 0x00000400,
 45	SIZE_PALETTE_RAM = 0x00000400,
 46	SIZE_VRAM = 0x00018000,
 47	SIZE_OAM = 0x00000400,
 48	SIZE_CART0 = 0x02000000,
 49	SIZE_CART1 = 0x02000000,
 50	SIZE_CART2 = 0x02000000,
 51	SIZE_CART_SRAM = 0x00008000,
 52	SIZE_CART_FLASH512 = 0x00010000,
 53	SIZE_CART_FLASH1M = 0x00020000,
 54	SIZE_CART_EEPROM = 0x00002000
 55};
 56
 57enum {
 58	OFFSET_MASK = 0x00FFFFFF,
 59	BASE_OFFSET = 24
 60};
 61
 62enum DMAControl {
 63	DMA_INCREMENT = 0,
 64	DMA_DECREMENT = 1,
 65	DMA_FIXED = 2,
 66	DMA_INCREMENT_RELOAD = 3
 67};
 68
 69enum DMATiming {
 70	DMA_TIMING_NOW = 0,
 71	DMA_TIMING_VBLANK = 1,
 72	DMA_TIMING_HBLANK = 2,
 73	DMA_TIMING_CUSTOM = 3
 74};
 75
 76struct GBADMA {
 77	union {
 78		struct {
 79			int : 5;
 80			enum DMAControl dstControl : 2;
 81			enum DMAControl srcControl : 2;
 82			unsigned repeat : 1;
 83			unsigned width : 1;
 84			unsigned drq : 1;
 85			enum DMATiming timing : 2;
 86			unsigned doIrq : 1;
 87			unsigned enable : 1;
 88		};
 89		uint16_t packed;
 90	};
 91
 92	uint32_t source;
 93	uint32_t dest;
 94	int32_t count;
 95	uint32_t nextSource;
 96	uint32_t nextDest;
 97	int32_t nextCount;
 98	int32_t nextIRQ;
 99};
100
101struct GBAMemory {
102	struct ARMMemory d;
103	struct GBA* p;
104
105	uint32_t* bios;
106	uint32_t* wram;
107	uint32_t* iwram;
108	uint32_t* rom;
109	uint16_t io[SIZE_IO >> 1];
110
111	char waitstates32[256];
112	char waitstates16[256];
113	char waitstatesSeq32[256];
114	char waitstatesSeq16[256];
115	int activeRegion;
116
117	struct GBADMA dma[4];
118};
119
120int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles);
121
122int32_t GBALoad32(struct ARMMemory* memory, uint32_t address);
123int16_t GBALoad16(struct ARMMemory* memory, uint32_t address);
124uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address);
125int8_t GBALoad8(struct ARMMemory* memory, uint32_t address);
126uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address);
127
128void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value);
129void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value);
130void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value);
131
132void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters);
133
134void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address);
135void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address);
136void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count);
137void GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control);
138
139void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info);
140void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info);
141void GBAMemoryRunHblankDMAs(struct GBAMemory* memory);
142void GBAMemoryRunVblankDMAs(struct GBAMemory* memory);
143
144#endif