src/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
24
25#define THUMB_SUBTRACTION_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D); \
28 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
29 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
30
31#define THUMB_NEUTRAL_S(M, N, D) \
32 cpu->cpsr.n = ARM_SIGN(D); \
33 cpu->cpsr.z = !(D);
34
35#define THUMB_ADDITION(D, M, N) \
36 int n = N; \
37 int m = M; \
38 D = M + N; \
39 THUMB_ADDITION_S(m, n, D)
40
41#define APPLY(F, ...) F(__VA_ARGS__)
42
43#define COUNT_1(EMITTER, PREFIX, ...) \
44 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
45 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
46
47#define COUNT_2(EMITTER, PREFIX, ...) \
48 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
49 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
50 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
51
52#define COUNT_3(EMITTER, PREFIX, ...) \
53 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
54 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
55 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
56 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
57 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
58
59#define COUNT_4(EMITTER, PREFIX, ...) \
60 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
61 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
62 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
63 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
64 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
65 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
66 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
67 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
68 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
69
70#define COUNT_5(EMITTER, PREFIX, ...) \
71 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
72 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
73 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
74 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
75 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
76 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
77 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
78 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
79 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
80 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
81 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
82 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
83 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
84 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
85 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
86 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
87 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
88
89#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
90 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
91 BODY; \
92 }
93
94#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
95 DEFINE_INSTRUCTION_THUMB(NAME, \
96 int immediate = IMMEDIATE; \
97 int rd = opcode & 0x0007; \
98 int rm = (opcode >> 3) & 0x0007; \
99 BODY;)
100
101#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
102 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
103
104DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
105 if (!immediate) { \
106 cpu->gprs[rd] = cpu->gprs[rm]; \
107 } else { \
108 cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \
109 cpu->gprs[rd] = cpu->gprs[rm] << immediate; \
110 } \
111 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
112
113DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
114 if (!immediate) { \
115 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]); \
116 cpu->gprs[rd] = 0; \
117 } else { \
118 cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); \
119 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate; \
120 } \
121 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
122
123DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
124
125DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
126DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
127DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
128DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
129DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, ARM_STUB)
130DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd]))
131
132#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
133 DEFINE_INSTRUCTION_THUMB(NAME, \
134 int rm = RM; \
135 int rd = opcode & 0x0007; \
136 int rn = (opcode >> 3) & 0x0007; \
137 BODY;)
138
139#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
140 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
141
142DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
143DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
144
145#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
146 DEFINE_INSTRUCTION_THUMB(NAME, \
147 int immediate = IMMEDIATE; \
148 int rd = opcode & 0x0007; \
149 int rn = (opcode >> 3) & 0x0007; \
150 BODY;)
151
152#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
153 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
154
155DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
156
157DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
158
159#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
160 DEFINE_INSTRUCTION_THUMB(NAME, \
161 int rd = RD; \
162 int immediate = opcode & 0x00FF; \
163 BODY;)
164
165#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
166 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
167
168DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
169
170
171DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
172DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
173DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
174
175#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
176 DEFINE_INSTRUCTION_THUMB(NAME, \
177 int rd = opcode & 0x0007; \
178 int rn = (opcode >> 3) & 0x0007; \
179 BODY;)
180
181DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, ARM_STUB)
182DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, ARM_STUB)
183DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
184DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, ARM_STUB)
185DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, ARM_STUB)
186DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
187DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
188DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
189DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
190DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
191DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
192DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
193DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, ARM_STUB)
194DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
195DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
196DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
197
198#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
199 DEFINE_INSTRUCTION_THUMB(NAME, \
200 int rd = opcode & 0x0007 | H1; \
201 int rm = (opcode >> 3) & 0x0007 | H2; \
202 BODY;)
203
204#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
205 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
206 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
207 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
208 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
209
210DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, ARM_STUB)
211DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, ARM_STUB)
212DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
213
214#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
215 DEFINE_INSTRUCTION_THUMB(NAME, \
216 int rd = RD; \
217 int immediate = (opcode & 0x00FF) << 2; \
218 BODY;)
219
220#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
221 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
222
223DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_PC] + immediate))
224DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate))
225DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd]))
226
227DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
228DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
229
230#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
231 DEFINE_INSTRUCTION_THUMB(NAME, \
232 int rm = RM; \
233 BODY;)
234
235#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
236 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
237
238DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
239DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
240DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
241DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
242DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
243DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
244DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
245DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
246
247#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
248 DEFINE_INSTRUCTION_THUMB(NAME, \
249 int rn = (opcode >> 8) & 0x000F; \
250 int rs = RS; \
251 int32_t address = ADDRESS; \
252 int m; \
253 int i; \
254 PRE_BODY; \
255 for LOOP { \
256 if (rs & m) { \
257 BODY; \
258 address OP 4; \
259 } \
260 } \
261 POST_BODY; \
262 WRITEBACK;)
263
264#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
265 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
266
267DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
268 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
269 if (!((1 << rn) & rs)) { \
270 cpu->gprs[rn] = address; \
271 })
272
273DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
274 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
275 cpu->gprs[rn] = address)
276
277#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
278 DEFINE_INSTRUCTION_THUMB(B ## COND, \
279 if (ARM_COND_ ## COND) { \
280 int8_t immediate = opcode; \
281 cpu->gprs[ARM_PC] += immediate << 1; \
282 THUMB_WRITE_PC; \
283 })
284
285DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
286DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
287DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
288DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
289DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
290DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
291DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
292DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
293DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
294DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
295DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
296DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
297DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
298DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
299
300DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
301DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
302
303DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
304 opcode & 0x00FF, \
305 cpu->gprs[ARM_SP], \
306 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
307 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
308 +=, \
309 , , \
310 cpu->gprs[ARM_SP] = address)
311
312DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
313 opcode & 0x00FF, \
314 cpu->gprs[ARM_SP], \
315 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
316 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
317 +=, \
318 , \
319 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
320 address += 4;, \
321 cpu->gprs[ARM_SP] = address)
322
323DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
324 opcode & 0x00FF, \
325 cpu->gprs[ARM_SP] - 4, \
326 (m = 0x80, i = 7; m; m >>= 1, --i), \
327 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
328 -=, \
329 , , \
330 cpu->gprs[ARM_SP] = address + 4)
331
332DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
333 opcode & 0x00FF, \
334 cpu->gprs[ARM_SP] - 4, \
335 (m = 0x80, i = 7; m; m >>= 1, --i), \
336 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
337 -=, \
338 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
339 address -= 4;, \
340 , \
341 cpu->gprs[ARM_SP] = address + 4)
342
343DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
344DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
345DEFINE_INSTRUCTION_THUMB(B, ARM_STUB)
346DEFINE_INSTRUCTION_THUMB(BL1, \
347 int16_t immediate = (opcode & 0x07FF) << 5; \
348 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
349
350DEFINE_INSTRUCTION_THUMB(BL2, \
351 uint16_t immediate = (opcode & 0x07FF) << 1; \
352 uint32_t pc = cpu->gprs[ARM_PC]; \
353 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
354 cpu->gprs[ARM_LR] = pc - 1; \
355 THUMB_WRITE_PC;)
356
357DEFINE_INSTRUCTION_THUMB(BX, ARM_STUB)
358DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
359
360#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
361 EMITTER ## NAME
362
363#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
364 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
365 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
366 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
367 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
368
369#define DUMMY(X, ...) X,
370#define DUMMY_4(...) \
371 DUMMY(__VA_ARGS__) \
372 DUMMY(__VA_ARGS__) \
373 DUMMY(__VA_ARGS__) \
374 DUMMY(__VA_ARGS__)
375
376#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
377 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
378 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
379 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
380 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
381 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
382 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
383 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
384 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
385 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
386 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
387 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
388 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
389 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
390 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
391 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
392 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
393 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
394 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
395 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
396 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
397 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
398 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
399 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
400 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
401 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
402 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
403 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
404 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
405 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
406 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
407 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
408 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
409 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
410 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
411 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
412 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
413 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
414 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
415 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
416 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
417 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
418 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
419 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
420 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
421 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
422 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
423 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
424 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
425 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
426 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
427 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
428 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
429 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
430 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
431 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
432 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
433 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
434 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
435 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
436 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
437 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
438 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
439 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
440 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
441 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
442 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
443 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
444 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
445 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
446 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
447 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
448 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
449 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
450 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
451 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
452 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
453 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
454 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
455 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
456 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
457 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
458 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
459 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
460 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
461 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
462 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
463 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
464 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
465 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
466 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
467 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
468
469static const ThumbInstruction _thumbTable[0x400] = {
470 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
471};