src/arm/decoder-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/decoder.h>
7
8#include <mgba/internal/arm/decoder-inlines.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define ADDR_MODE_1_SHIFT(OP) \
13 info->op3.reg = opcode & 0x0000000F; \
14 info->op3.shifterOp = ARM_SHIFT_ ## OP; \
15 info->operandFormat |= ARM_OPERAND_REGISTER_3; \
16 if (opcode & 0x00000010) { \
17 info->op3.shifterReg = (opcode >> 8) & 0xF; \
18 ++info->iCycles; \
19 info->operandFormat |= ARM_OPERAND_SHIFT_REGISTER_3; \
20 } else { \
21 info->op3.shifterImm = (opcode >> 7) & 0x1F; \
22 info->operandFormat |= ARM_OPERAND_SHIFT_IMMEDIATE_3; \
23 }
24
25#define ADDR_MODE_1_LSL \
26 ADDR_MODE_1_SHIFT(LSL) \
27 if (!info->op3.shifterImm) { \
28 info->operandFormat &= ~ARM_OPERAND_SHIFT_IMMEDIATE_3; \
29 info->op3.shifterOp = ARM_SHIFT_NONE; \
30 }
31
32#define ADDR_MODE_1_LSR ADDR_MODE_1_SHIFT(LSR)
33#define ADDR_MODE_1_ASR ADDR_MODE_1_SHIFT(ASR)
34#define ADDR_MODE_1_ROR \
35 ADDR_MODE_1_SHIFT(ROR) \
36 if (!info->op3.shifterImm) { \
37 info->op3.shifterOp = ARM_SHIFT_RRX; \
38 }
39
40#define ADDR_MODE_1_IMM \
41 int rotate = (opcode & 0x00000F00) >> 7; \
42 int immediate = opcode & 0x000000FF; \
43 info->op3.immediate = ROR(immediate, rotate); \
44 info->operandFormat |= ARM_OPERAND_IMMEDIATE_3;
45
46#define ADDR_MODE_2_SHIFT(OP) \
47 info->memory.format |= ARM_MEMORY_REGISTER_OFFSET | ARM_MEMORY_SHIFTED_OFFSET; \
48 info->memory.offset.shifterOp = ARM_SHIFT_ ## OP; \
49 info->memory.offset.shifterImm = (opcode >> 7) & 0x1F; \
50 info->memory.offset.reg = opcode & 0x0000000F;
51
52#define ADDR_MODE_2_LSL \
53 ADDR_MODE_2_SHIFT(LSL) \
54 if (!info->memory.offset.shifterImm) { \
55 info->memory.format &= ~ARM_MEMORY_SHIFTED_OFFSET; \
56 info->memory.offset.shifterOp = ARM_SHIFT_NONE; \
57 }
58
59#define ADDR_MODE_2_LSR ADDR_MODE_2_SHIFT(LSR) \
60 if (!info->memory.offset.shifterImm) { \
61 info->memory.offset.shifterImm = 32; \
62 }
63
64#define ADDR_MODE_2_ASR ADDR_MODE_2_SHIFT(ASR) \
65 if (!info->memory.offset.shifterImm) { \
66 info->memory.offset.shifterImm = 32; \
67 }
68
69#define ADDR_MODE_2_ROR \
70 ADDR_MODE_2_SHIFT(ROR) \
71 if (!info->memory.offset.shifterImm) { \
72 info->memory.offset.shifterOp = ARM_SHIFT_RRX; \
73 }
74
75#define ADDR_MODE_2_IMM \
76 info->memory.format |= ARM_MEMORY_IMMEDIATE_OFFSET; \
77 info->memory.offset.immediate = opcode & 0x00000FFF;
78
79#define ADDR_MODE_3_REG \
80 info->memory.format |= ARM_MEMORY_REGISTER_OFFSET; \
81 info->memory.offset.reg = opcode & 0x0000000F;
82
83#define ADDR_MODE_3_IMM \
84 info->memory.format |= ARM_MEMORY_IMMEDIATE_OFFSET; \
85 info->memory.offset.immediate = (opcode & 0x0000000F) | ((opcode & 0x00000F00) >> 4);
86
87#define DEFINE_DECODER_ARM(NAME, MNEMONIC, BODY) \
88 static void _ARMDecode ## NAME (uint32_t opcode, struct ARMInstructionInfo* info) { \
89 UNUSED(opcode); \
90 info->mnemonic = ARM_MN_ ## MNEMONIC; \
91 BODY; \
92 }
93
94#define DEFINE_ALU_DECODER_EX_ARM(NAME, MNEMONIC, S, SHIFTER, OTHER_AFFECTED, SKIPPED) \
95 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
96 info->op1.reg = (opcode >> 12) & 0xF; \
97 info->op2.reg = (opcode >> 16) & 0xF; \
98 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
99 OTHER_AFFECTED | \
100 ARM_OPERAND_REGISTER_2; \
101 info->affectsCPSR = S; \
102 SHIFTER; \
103 if (SKIPPED == 1) { \
104 info->op1 = info->op2; \
105 info->op2 = info->op3; \
106 info->operandFormat >>= 8; \
107 } else if (SKIPPED == 2) { \
108 info->op2 = info->op3; \
109 info->operandFormat |= info->operandFormat >> 8; \
110 info->operandFormat &= ~ARM_OPERAND_3; \
111 } \
112 if (info->op1.reg == ARM_PC && (OTHER_AFFECTED & ARM_OPERAND_AFFECTED_1)) { \
113 info->branchType = ARM_BRANCH_INDIRECT; \
114 })
115
116#define DEFINE_ALU_DECODER_ARM(NAME, SKIPPED) \
117 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 0, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
118 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
119 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 0, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
120 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
121 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 0, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
122 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
123 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 0, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
124 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
125 DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 0, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED) \
126 DEFINE_ALU_DECODER_EX_ARM(NAME ## SI, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED)
127
128#define DEFINE_ALU_DECODER_S_ONLY_ARM(NAME) \
129 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_NONE, 1) \
130 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_NONE, 1) \
131 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_NONE, 1) \
132 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_NONE, 1) \
133 DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_NONE, 1)
134
135#define DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S, OTHER_AFFECTED) \
136 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
137 info->op1.reg = (opcode >> 16) & 0xF; \
138 info->op2.reg = opcode & 0xF; \
139 info->op3.reg = (opcode >> 8) & 0xF; \
140 info->op4.reg = (opcode >> 12) & 0xF; \
141 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
142 ARM_OPERAND_AFFECTED_1 | \
143 ARM_OPERAND_REGISTER_2 | \
144 ARM_OPERAND_REGISTER_3 | \
145 OTHER_AFFECTED; \
146 info->affectsCPSR = S; \
147 if (info->op1.reg == ARM_PC) { \
148 info->branchType = ARM_BRANCH_INDIRECT; \
149 })
150
151#define DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S) \
152 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
153 info->op1.reg = (opcode >> 12) & 0xF; \
154 info->op2.reg = (opcode >> 16) & 0xF; \
155 info->op3.reg = opcode & 0xF; \
156 info->op4.reg = (opcode >> 8) & 0xF; \
157 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
158 ARM_OPERAND_AFFECTED_1 | \
159 ARM_OPERAND_REGISTER_2 | \
160 ARM_OPERAND_AFFECTED_2 | \
161 ARM_OPERAND_REGISTER_3 | \
162 ARM_OPERAND_REGISTER_4; \
163 info->affectsCPSR = S; \
164 if (info->op1.reg == ARM_PC) { \
165 info->branchType = ARM_BRANCH_INDIRECT; \
166 })
167
168#define DEFINE_MULTIPLY_DECODER_ARM(NAME, OTHER_AFFECTED) \
169 DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0, OTHER_AFFECTED) \
170 DEFINE_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1, OTHER_AFFECTED)
171
172#define DEFINE_LONG_MULTIPLY_DECODER_ARM(NAME) \
173 DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0) \
174 DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1)
175
176#define DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, ADDRESSING_MODE, ADDRESSING_DECODING, CYCLES, TYPE, OTHER_AFFECTED) \
177 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
178 info->op1.reg = (opcode >> 12) & 0xF; \
179 info->memory.baseReg = (opcode >> 16) & 0xF; \
180 info->memory.width = TYPE; \
181 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
182 OTHER_AFFECTED | \
183 ARM_OPERAND_MEMORY_2; \
184 info->memory.format = ARM_MEMORY_REGISTER_BASE | ADDRESSING_MODE; \
185 ADDRESSING_DECODING; \
186 if (info->op1.reg == ARM_PC && (OTHER_AFFECTED & ARM_OPERAND_AFFECTED_1)) { \
187 info->branchType = ARM_BRANCH_INDIRECT; \
188 } \
189 if ((info->memory.format & (ARM_MEMORY_WRITEBACK | ARM_MEMORY_REGISTER_OFFSET)) == (ARM_MEMORY_WRITEBACK | ARM_MEMORY_REGISTER_OFFSET) && \
190 info->memory.offset.reg == ARM_PC) { \
191 info->branchType = ARM_BRANCH_INDIRECT; \
192 } \
193 CYCLES;)
194
195#define DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, TYPE, FORMAT, OTHER_AFFECTED) \
196 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
197 ARM_MEMORY_POST_INCREMENT | \
198 ARM_MEMORY_WRITEBACK | \
199 ARM_MEMORY_OFFSET_SUBTRACT | \
200 ARM_MEMORY_ ## FORMAT, \
201 ADDRESSING_MODE, FORMAT ## _CYCLES, ARM_ACCESS_ ## TYPE, OTHER_AFFECTED) \
202 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
203 ARM_MEMORY_POST_INCREMENT | \
204 ARM_MEMORY_WRITEBACK | \
205 ARM_MEMORY_ ## FORMAT, \
206 ADDRESSING_MODE, FORMAT ## _CYCLES, ARM_ACCESS_ ## TYPE, OTHER_AFFECTED) \
207 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## P, MNEMONIC, \
208 ARM_MEMORY_OFFSET_SUBTRACT | \
209 ARM_MEMORY_ ## FORMAT, \
210 ADDRESSING_MODE, FORMAT ## _CYCLES, ARM_ACCESS_ ## TYPE, OTHER_AFFECTED) \
211 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PW, MNEMONIC, \
212 ARM_MEMORY_PRE_INCREMENT | \
213 ARM_MEMORY_WRITEBACK | \
214 ARM_MEMORY_OFFSET_SUBTRACT | \
215 ARM_MEMORY_ ## FORMAT, \
216 ADDRESSING_MODE, FORMAT ## _CYCLES, ARM_ACCESS_ ## TYPE, OTHER_AFFECTED) \
217 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PU, MNEMONIC, \
218 ARM_MEMORY_ ## FORMAT, \
219 ADDRESSING_MODE, FORMAT ## _CYCLES, ARM_ACCESS_ ## TYPE, OTHER_AFFECTED) \
220 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PUW, MNEMONIC, \
221 ARM_MEMORY_WRITEBACK | \
222 ARM_MEMORY_ ## FORMAT, \
223 ADDRESSING_MODE, FORMAT ## _CYCLES, ARM_ACCESS_ ## TYPE, OTHER_AFFECTED) \
224
225#define DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(NAME, MNEMONIC, FORMAT, TYPE, OTHER_AFFECTED) \
226 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, TYPE, FORMAT, OTHER_AFFECTED) \
227 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, TYPE, FORMAT, OTHER_AFFECTED) \
228 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, TYPE, FORMAT, OTHER_AFFECTED) \
229 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, TYPE, FORMAT, OTHER_AFFECTED) \
230 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, TYPE, FORMAT, OTHER_AFFECTED)
231
232#define DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(NAME, MNEMONIC, FORMAT, TYPE, OTHER_AFFECTED) \
233 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDR_MODE_3_REG, TYPE, FORMAT, OTHER_AFFECTED) \
234 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_3_IMM, TYPE, FORMAT, OTHER_AFFECTED)
235
236#define DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, TYPE, FORMAT, OTHER_AFFECTED) \
237 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
238 ARM_MEMORY_POST_INCREMENT | \
239 ARM_MEMORY_WRITEBACK | \
240 ARM_MEMORY_OFFSET_SUBTRACT | \
241 ARM_MEMORY_ ## FORMAT, \
242 ADDRESSING_MODE, FORMAT ## _CYCLES, ARM_ACCESS_ ## TYPE, OTHER_AFFECTED) \
243 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
244 ARM_MEMORY_POST_INCREMENT | \
245 ARM_MEMORY_WRITEBACK | \
246 ARM_MEMORY_ ## FORMAT, \
247 ADDRESSING_MODE, FORMAT ## _CYCLES, ARM_ACCESS_ ## TYPE, OTHER_AFFECTED)
248
249#define DEFINE_LOAD_STORE_T_DECODER_ARM(NAME, MNEMONIC, FORMAT, TYPE, OTHER_AFFECTED) \
250 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, TYPE, FORMAT, OTHER_AFFECTED) \
251 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, TYPE, FORMAT, OTHER_AFFECTED) \
252 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, TYPE, FORMAT, OTHER_AFFECTED) \
253 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, TYPE, FORMAT, OTHER_AFFECTED) \
254 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, TYPE, FORMAT, OTHER_AFFECTED)
255
256#define DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME, MNEMONIC, DIRECTION, FORMAT) \
257 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
258 info->memory.baseReg = (opcode >> 16) & 0xF; \
259 info->op1.immediate = opcode & 0x0000FFFF; \
260 if (info->op1.immediate & (1 << ARM_PC)) { \
261 info->branchType = ARM_BRANCH_INDIRECT; \
262 } \
263 info->operandFormat = ARM_OPERAND_MEMORY_1; \
264 info->memory.format = ARM_MEMORY_REGISTER_BASE | \
265 FORMAT | \
266 ARM_MEMORY_ ## DIRECTION;)
267
268
269#define DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(NAME, FORMAT) \
270 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DA, NAME, DECREMENT_AFTER, ARM_MEMORY_ ## FORMAT) \
271 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK | ARM_MEMORY_ ## FORMAT) \
272 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DB, NAME, DECREMENT_BEFORE, ARM_MEMORY_ ## FORMAT) \
273 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK | ARM_MEMORY_ ## FORMAT) \
274 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IA, NAME, INCREMENT_AFTER, ARM_MEMORY_ ## FORMAT) \
275 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK | ARM_MEMORY_ ## FORMAT) \
276 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IB, NAME, INCREMENT_BEFORE, ARM_MEMORY_ ## FORMAT) \
277 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK | ARM_MEMORY_ ## FORMAT) \
278 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDA, NAME, DECREMENT_AFTER, ARM_MEMORY_SPSR_SWAP | ARM_MEMORY_ ## FORMAT) \
279 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP | ARM_MEMORY_ ## FORMAT) \
280 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDB, NAME, DECREMENT_BEFORE, ARM_MEMORY_SPSR_SWAP | ARM_MEMORY_ ## FORMAT) \
281 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP | ARM_MEMORY_ ## FORMAT) \
282 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIA, NAME, INCREMENT_AFTER, ARM_MEMORY_SPSR_SWAP | ARM_MEMORY_ ## FORMAT) \
283 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP | ARM_MEMORY_ ## FORMAT) \
284 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIB, NAME, INCREMENT_BEFORE, ARM_MEMORY_SPSR_SWAP | ARM_MEMORY_ ## FORMAT) \
285 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP | ARM_MEMORY_ ## FORMAT)
286
287#define DEFINE_SWP_DECODER_ARM(NAME, TYPE) \
288 DEFINE_DECODER_ARM(NAME, SWP, \
289 info->memory.baseReg = (opcode >> 16) & 0xF; \
290 info->op1.reg = (opcode >> 12) & 0xF; \
291 info->op2.reg = opcode & 0xF; \
292 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
293 ARM_OPERAND_AFFECTED_1 | \
294 ARM_OPERAND_REGISTER_2 | \
295 ARM_OPERAND_MEMORY_3 | ARM_OPERAND_AFFECTED_3; \
296 info->memory.format = ARM_MEMORY_REGISTER_BASE | ARM_MEMORY_SWAP; \
297 info->memory.width = TYPE;)
298
299DEFINE_ALU_DECODER_ARM(ADD, 0)
300DEFINE_ALU_DECODER_ARM(ADC, 0)
301DEFINE_ALU_DECODER_ARM(AND, 0)
302DEFINE_ALU_DECODER_ARM(BIC, 0)
303DEFINE_ALU_DECODER_S_ONLY_ARM(CMN)
304DEFINE_ALU_DECODER_S_ONLY_ARM(CMP)
305DEFINE_ALU_DECODER_ARM(EOR, 0)
306DEFINE_ALU_DECODER_ARM(MOV, 2)
307DEFINE_ALU_DECODER_ARM(MVN, 2)
308DEFINE_ALU_DECODER_ARM(ORR, 0)
309DEFINE_ALU_DECODER_ARM(RSB, 0)
310DEFINE_ALU_DECODER_ARM(RSC, 0)
311DEFINE_ALU_DECODER_ARM(SBC, 0)
312DEFINE_ALU_DECODER_ARM(SUB, 0)
313DEFINE_ALU_DECODER_S_ONLY_ARM(TEQ)
314DEFINE_ALU_DECODER_S_ONLY_ARM(TST)
315
316// TOOD: Estimate cycles
317DEFINE_MULTIPLY_DECODER_ARM(MLA, ARM_OPERAND_REGISTER_4)
318DEFINE_MULTIPLY_DECODER_ARM(MUL, ARM_OPERAND_NONE)
319
320DEFINE_LONG_MULTIPLY_DECODER_ARM(SMLAL)
321DEFINE_LONG_MULTIPLY_DECODER_ARM(SMULL)
322DEFINE_LONG_MULTIPLY_DECODER_ARM(UMLAL)
323DEFINE_LONG_MULTIPLY_DECODER_ARM(UMULL)
324
325// Begin load/store definitions
326
327DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDR, LDR, LOAD, WORD, ARM_OPERAND_AFFECTED_1)
328DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDRB, LDR, LOAD, BYTE, ARM_OPERAND_AFFECTED_1)
329DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRH, LDR, LOAD, HALFWORD, ARM_OPERAND_AFFECTED_1)
330DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSB, LDR, LOAD, SIGNED_BYTE, ARM_OPERAND_AFFECTED_1)
331DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSH, LDR, LOAD, SIGNED_HALFWORD, ARM_OPERAND_AFFECTED_1)
332DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STR, STR, STORE, WORD, ARM_OPERAND_AFFECTED_2)
333DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STRB, STR, STORE, BYTE, ARM_OPERAND_AFFECTED_2)
334DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(STRH, STR, STORE, HALFWORD, ARM_OPERAND_AFFECTED_2)
335
336DEFINE_LOAD_STORE_T_DECODER_ARM(LDRBT, LDR, LOAD, TRANSLATED_BYTE, ARM_OPERAND_AFFECTED_1)
337DEFINE_LOAD_STORE_T_DECODER_ARM(LDRT, LDR, LOAD, TRANSLATED_WORD, ARM_OPERAND_AFFECTED_1)
338DEFINE_LOAD_STORE_T_DECODER_ARM(STRBT, STR, STORE, TRANSLATED_BYTE, ARM_OPERAND_AFFECTED_2)
339DEFINE_LOAD_STORE_T_DECODER_ARM(STRT, STR, STORE, TRANSLATED_WORD, ARM_OPERAND_AFFECTED_2)
340
341DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(LDM, LOAD)
342DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(STM, STORE)
343
344DEFINE_SWP_DECODER_ARM(SWP, ARM_ACCESS_WORD)
345DEFINE_SWP_DECODER_ARM(SWPB, ARM_ACCESS_BYTE)
346
347// End load/store definitions
348
349// Begin branch definitions
350
351DEFINE_DECODER_ARM(B, B,
352 int32_t offset = opcode << 8;
353 info->op1.immediate = offset >> 6;
354 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
355 info->branchType = ARM_BRANCH;)
356
357DEFINE_DECODER_ARM(BL, BL,
358 int32_t offset = opcode << 8;
359 info->op1.immediate = offset >> 6;
360 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
361 info->branchType = ARM_BRANCH_LINKED;)
362
363DEFINE_DECODER_ARM(BX, BX,
364 info->op1.reg = opcode & 0x0000000F;
365 info->operandFormat = ARM_OPERAND_REGISTER_1;
366 info->branchType = ARM_BRANCH_INDIRECT;)
367
368// End branch definitions
369
370// Begin coprocessor definitions
371
372DEFINE_DECODER_ARM(CDP, ILL, info->operandFormat = ARM_OPERAND_NONE;)
373DEFINE_DECODER_ARM(LDC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
374DEFINE_DECODER_ARM(STC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
375DEFINE_DECODER_ARM(MCR, ILL, info->operandFormat = ARM_OPERAND_NONE;)
376DEFINE_DECODER_ARM(MRC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
377
378// Begin miscellaneous definitions
379
380DEFINE_DECODER_ARM(BKPT, BKPT,
381 info->operandFormat = ARM_OPERAND_NONE;
382 info->traps = 1;) // Not strictly in ARMv4T, but here for convenience
383DEFINE_DECODER_ARM(ILL, ILL,
384 info->operandFormat = ARM_OPERAND_NONE;
385 info->traps = 1;) // Illegal opcode
386
387DEFINE_DECODER_ARM(MSR, MSR,
388 info->affectsCPSR = 1;
389 info->op1.reg = ARM_CPSR;
390 info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
391 info->op2.reg = opcode & 0x0000000F;
392 info->operandFormat = ARM_OPERAND_REGISTER_1 |
393 ARM_OPERAND_AFFECTED_1 |
394 ARM_OPERAND_REGISTER_2;)
395
396DEFINE_DECODER_ARM(MSRR, MSR,
397 info->op1.reg = ARM_SPSR;
398 info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
399 info->op2.reg = opcode & 0x0000000F;
400 info->operandFormat = ARM_OPERAND_REGISTER_1 |
401 ARM_OPERAND_AFFECTED_1 |
402 ARM_OPERAND_REGISTER_2;)
403
404DEFINE_DECODER_ARM(MRS, MRS,
405 info->affectsCPSR = 1;
406 info->op1.reg = (opcode >> 12) & 0xF;
407 info->op2.reg = ARM_CPSR;
408 info->op2.psrBits = 0;
409 info->operandFormat = ARM_OPERAND_REGISTER_1 |
410 ARM_OPERAND_AFFECTED_1 |
411 ARM_OPERAND_REGISTER_2;)
412
413DEFINE_DECODER_ARM(MRSR, MRS,
414 info->op1.reg = (opcode >> 12) & 0xF;
415 info->op2.reg = ARM_SPSR;
416 info->op2.psrBits = 0;
417 info->operandFormat = ARM_OPERAND_REGISTER_1 |
418 ARM_OPERAND_AFFECTED_1 |
419 ARM_OPERAND_REGISTER_2;)
420
421DEFINE_DECODER_ARM(MSRI, MSR,
422 int rotate = (opcode & 0x00000F00) >> 7;
423 int32_t operand = ROR(opcode & 0x000000FF, rotate);
424 info->affectsCPSR = 1;
425 info->op1.reg = ARM_CPSR;
426 info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
427 info->op2.immediate = operand;
428 info->operandFormat = ARM_OPERAND_REGISTER_1 |
429 ARM_OPERAND_AFFECTED_1 |
430 ARM_OPERAND_IMMEDIATE_2;)
431
432DEFINE_DECODER_ARM(MSRRI, MSR,
433 int rotate = (opcode & 0x00000F00) >> 7;
434 int32_t operand = ROR(opcode & 0x000000FF, rotate);
435 info->op1.reg = ARM_SPSR;
436 info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
437 info->op2.immediate = operand;
438 info->operandFormat = ARM_OPERAND_REGISTER_1 |
439 ARM_OPERAND_AFFECTED_1 |
440 ARM_OPERAND_IMMEDIATE_2;)
441
442DEFINE_DECODER_ARM(SWI, SWI,
443 info->op1.immediate = opcode & 0xFFFFFF;
444 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
445 info->traps = 1;)
446
447typedef void (*ARMDecoder)(uint32_t opcode, struct ARMInstructionInfo* info);
448
449static const ARMDecoder _armDecoderTable[0x1000] = {
450 DECLARE_ARM_EMITTER_BLOCK(_ARMDecode)
451};
452
453void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info) {
454 memset(info, 0, sizeof(*info));
455 info->execMode = MODE_ARM;
456 info->opcode = opcode;
457 info->branchType = ARM_BRANCH_NONE;
458 info->condition = opcode >> 28;
459 info->sInstructionCycles = 1;
460 ARMDecoder decoder = _armDecoderTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
461 decoder(opcode, info);
462}