src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count);
14
15static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
16static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 4, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
17static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
18static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
19static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
20static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
21static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
22
23void GBAMemoryInit(struct GBAMemory* memory) {
24 memory->d.load32 = GBALoad32;
25 memory->d.load16 = GBALoad16;
26 memory->d.loadU16 = GBALoadU16;
27 memory->d.load8 = GBALoad8;
28 memory->d.loadU8 = GBALoadU8;
29 memory->d.store32 = GBAStore32;
30 memory->d.store16 = GBAStore16;
31 memory->d.store8 = GBAStore8;
32
33 memory->bios = (uint32_t*) hleBios;
34 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
35 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
36 memory->rom = 0;
37 memset(memory->io, 0, sizeof(memory->io));
38 memset(memory->dma, 0, sizeof(memory->dma));
39
40 if (!memory->wram || !memory->iwram) {
41 GBAMemoryDeinit(memory);
42 memory->p->errno = GBA_OUT_OF_MEMORY;
43 memory->p->errstr = GBA_CANNOT_MMAP;
44 }
45
46 GBASavedataInit(&memory->savedata, "test.sav");
47
48 int i;
49 for (i = 0; i < 16; ++i) {
50 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
51 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
52 memory->waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
53 memory->waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
54 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
55 memory->waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
56 }
57 for (; i < 256; ++i) {
58 memory->waitstates16[i] = 0;
59 memory->waitstatesSeq16[i] = 0;
60 memory->waitstatesPrefetch16[i] = 0;
61 memory->waitstates32[i] = 0;
62 memory->waitstatesSeq32[i] = 0;
63 memory->waitstatesPrefetch32[i] = 0;
64 }
65
66 memory->activeRegion = 0;
67 memory->d.activeRegion = 0;
68 memory->d.activeMask = 0;
69 memory->d.setActiveRegion = GBASetActiveRegion;
70 memory->d.activePrefetchCycles32 = 0;
71 memory->d.activePrefetchCycles16 = 0;
72 memory->d.waitMultiple = GBAWaitMultiple;
73}
74
75void GBAMemoryDeinit(struct GBAMemory* memory) {
76 munmap(memory->wram, SIZE_WORKING_RAM);
77 munmap(memory->iwram, SIZE_WORKING_IRAM);
78 GBASavedataDeinit(&memory->savedata);
79}
80
81static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
82 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
83
84 gbaMemory->activeRegion = address >> BASE_OFFSET;
85 memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[gbaMemory->activeRegion];
86 memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[gbaMemory->activeRegion];
87 memory->activeNonseqCycles32 = gbaMemory->waitstates32[gbaMemory->activeRegion];
88 memory->activeNonseqCycles16 = gbaMemory->waitstates16[gbaMemory->activeRegion];
89 switch (address & ~OFFSET_MASK) {
90 case BASE_BIOS:
91 memory->activeRegion = gbaMemory->bios;
92 memory->activeMask = SIZE_BIOS - 1;
93 break;
94 case BASE_WORKING_RAM:
95 memory->activeRegion = gbaMemory->wram;
96 memory->activeMask = SIZE_WORKING_RAM - 1;
97 break;
98 case BASE_WORKING_IRAM:
99 memory->activeRegion = gbaMemory->iwram;
100 memory->activeMask = SIZE_WORKING_IRAM - 1;
101 break;
102 case BASE_CART0:
103 case BASE_CART0_EX:
104 case BASE_CART1:
105 case BASE_CART1_EX:
106 case BASE_CART2:
107 case BASE_CART2_EX:
108 memory->activeRegion = gbaMemory->rom;
109 memory->activeMask = SIZE_CART0 - 1;
110 break;
111 default:
112 memory->activeRegion = 0;
113 memory->activeMask = 0;
114 break;
115 }
116 gbaMemory->p->cpu.cycles += 1 + (gbaMemory->p->cpu.executionMode == MODE_ARM ? gbaMemory->waitstates32[address >> BASE_OFFSET] : gbaMemory->waitstates16[address >> BASE_OFFSET]);
117}
118
119int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
120 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
121 uint32_t value = 0;
122 int wait = 0;
123
124 switch (address & ~OFFSET_MASK) {
125 case BASE_BIOS:
126 break;
127 case BASE_WORKING_RAM:
128 value = gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
129 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
130 break;
131 case BASE_WORKING_IRAM:
132 value = gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
133 break;
134 case BASE_IO:
135 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1)) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
136 break;
137 case BASE_PALETTE_RAM:
138 value = ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2];
139 break;
140 case BASE_VRAM:
141 value = ((int32_t*) gbaMemory->p->video.renderer->vram)[(address & 0x0001FFFF) >> 2];
142 break;
143 case BASE_OAM:
144 value = ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2];
145 break;
146 case BASE_CART0:
147 case BASE_CART0_EX:
148 case BASE_CART1:
149 case BASE_CART1_EX:
150 case BASE_CART2:
151 case BASE_CART2_EX:
152 wait = gbaMemory->waitstates32[address >> BASE_OFFSET];
153 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
154 value = gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
155 }
156 break;
157 case BASE_CART_SRAM:
158 break;
159 default:
160 break;
161 }
162
163
164 if (cycleCounter) {
165 *cycleCounter += 2 + wait;
166 }
167 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
168 int rotate = (address & 3) << 3;
169 return (value >> rotate) | (value << (32 - rotate));
170}
171
172uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
173 return GBALoad16(memory, address, cycleCounter);
174}
175
176int16_t GBALoad16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
177 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
178 int16_t value = 0;
179 int wait = 0;
180
181 switch (address & ~OFFSET_MASK) {
182 case BASE_BIOS:
183 break;
184 case BASE_WORKING_RAM:
185 value = ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
186 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
187 break;
188 case BASE_WORKING_IRAM:
189 value = ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
190 break;
191 case BASE_IO:
192 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
193 break;
194 case BASE_PALETTE_RAM:
195 value = gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
196 break;
197 case BASE_VRAM:
198 value = gbaMemory->p->video.renderer->vram[(address & 0x0001FFFF) >> 1];
199 break;
200 case BASE_OAM:
201 value = gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1];
202 break;
203 case BASE_CART0:
204 case BASE_CART0_EX:
205 case BASE_CART1:
206 case BASE_CART1_EX:
207 case BASE_CART2:
208 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
209 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
210 value = ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
211 }
212 break;
213 case BASE_CART2_EX:
214 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
215 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
216 value = GBASavedataReadEEPROM(&gbaMemory->savedata);
217 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
218 value = ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
219 }
220 break;
221 case BASE_CART_SRAM:
222 break;
223 default:
224 break;
225 }
226
227 if (cycleCounter) {
228 *cycleCounter += 2 + wait;
229 }
230 return value;
231}
232
233uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
234 return GBALoad8(memory, address, cycleCounter);
235}
236
237int8_t GBALoad8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
238 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
239 int8_t value = 0;
240 int wait = 0;
241
242 switch (address & ~OFFSET_MASK) {
243 case BASE_BIOS:
244 break;
245 case BASE_WORKING_RAM:
246 value = ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
247 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
248 break;
249 case BASE_WORKING_IRAM:
250 value = ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
251 break;
252 case BASE_IO:
253 value = (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
254 break;
255 case BASE_PALETTE_RAM:
256 break;
257 case BASE_VRAM:
258 break;
259 case BASE_OAM:
260 break;
261 case BASE_CART0:
262 case BASE_CART0_EX:
263 case BASE_CART1:
264 case BASE_CART1_EX:
265 case BASE_CART2:
266 case BASE_CART2_EX:
267 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
268 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
269 value = ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
270 }
271 break;
272 case BASE_CART_SRAM:
273 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
274 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
275 GBASavedataInitSRAM(&gbaMemory->savedata);
276 }
277 value = gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
278 default:
279 break;
280 }
281
282 if (cycleCounter) {
283 *cycleCounter += 2 + wait;
284 }
285 return value;
286}
287
288void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value, int* cycleCounter) {
289 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
290 int wait = 0;
291
292 switch (address & ~OFFSET_MASK) {
293 case BASE_WORKING_RAM:
294 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
295 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
296 break;
297 case BASE_WORKING_IRAM:
298 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
299 break;
300 case BASE_IO:
301 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
302 break;
303 case BASE_PALETTE_RAM:
304 ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2] = value;
305 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
306 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
307 break;
308 case BASE_VRAM:
309 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
310 ((int32_t*) gbaMemory->p->video.renderer->vram)[(address & 0x0001FFFF) >> 2] = value;
311 }
312 break;
313 case BASE_OAM:
314 ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2] = value;
315 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
316 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
317 break;
318 case BASE_CART0:
319 break;
320 case BASE_CART_SRAM:
321 break;
322 default:
323 break;
324 }
325
326 if (cycleCounter) {
327 *cycleCounter += 1 + wait;
328 }
329}
330
331void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value, int* cycleCounter) {
332 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
333 int wait = 0;
334
335 switch (address & ~OFFSET_MASK) {
336 case BASE_WORKING_RAM:
337 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
338 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
339 break;
340 case BASE_WORKING_IRAM:
341 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
342 break;
343 case BASE_IO:
344 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
345 break;
346 case BASE_PALETTE_RAM:
347 gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1] = value;
348 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
349 break;
350 case BASE_VRAM:
351 if ((address & OFFSET_MASK) < SIZE_VRAM) {
352 gbaMemory->p->video.renderer->vram[(address & 0x0001FFFF) >> 1] = value;
353 }
354 break;
355 case BASE_OAM:
356 gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1] = value;
357 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
358 break;
359 case BASE_CART0:
360 break;
361 case BASE_CART2_EX:
362 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
363 GBASavedataInitEEPROM(&gbaMemory->savedata);
364 }
365 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
366 break;
367 case BASE_CART_SRAM:
368 break;
369 default:
370 break;
371 }
372
373 if (cycleCounter) {
374 *cycleCounter += 1 + wait;
375 }
376}
377
378void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value, int* cycleCounter) {
379 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
380 int wait = 0;
381
382 switch (address & ~OFFSET_MASK) {
383 case BASE_WORKING_RAM:
384 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
385 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
386 break;
387 case BASE_WORKING_IRAM:
388 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
389 break;
390 case BASE_IO:
391 GBAIOWrite8(gbaMemory->p, address & (SIZE_IO - 1), value);
392 break;
393 case BASE_PALETTE_RAM:
394 break;
395 case BASE_VRAM:
396 break;
397 case BASE_OAM:
398 break;
399 case BASE_CART0:
400 break;
401 case BASE_CART_SRAM:
402 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
403 if (address == SAVEDATA_FLASH_BASE) {
404 GBASavedataInitFlash(&gbaMemory->savedata);
405 } else {
406 GBASavedataInitSRAM(&gbaMemory->savedata);
407 }
408 }
409 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
410 GBASavedataWriteFlash(&gbaMemory->savedata, value);
411 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
412 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
413 }
414 wait = gbaMemory->waitstates16[REGION_CART_SRAM];
415 break;
416 default:
417 break;
418 }
419
420 if (cycleCounter) {
421 *cycleCounter += 1 + wait;
422 }
423}
424
425static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count) {
426 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
427 int wait = 1 + gbaMemory->waitstates32[startAddress >> BASE_OFFSET];
428 wait += (1 + gbaMemory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
429 return wait;
430}
431
432void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
433 int sram = parameters & 0x0003;
434 int ws0 = (parameters & 0x000C) >> 2;
435 int ws0seq = (parameters & 0x0010) >> 4;
436 int ws1 = (parameters & 0x0060) >> 5;
437 int ws1seq = (parameters & 0x0080) >> 7;
438 int ws2 = (parameters & 0x0300) >> 8;
439 int ws2seq = (parameters & 0x0400) >> 10;
440 int prefetch = parameters & 0x4000;
441
442 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
443 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
444 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
445 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
446
447 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
448 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
449 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
450
451 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
452 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
453 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
454
455 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
456 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
457 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
458
459 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
460 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
461 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
462
463 if (!prefetch) {
464 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
465 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
466 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
467
468 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
469 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
470 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
471 } else {
472 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
473 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
474 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
475
476 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
477 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
478 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
479 }
480
481 memory->d.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
482 memory->d.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
483 memory->d.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
484 memory->d.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
485}
486
487int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
488 struct GBADMA* dma;
489 int32_t test = INT_MAX;
490
491 dma = &memory->dma[0];
492 dma->nextIRQ -= cycles;
493 if (dma->enable && dma->doIrq && dma->nextIRQ) {
494 if (dma->nextIRQ <= 0) {
495 dma->nextIRQ = INT_MAX;
496 GBARaiseIRQ(memory->p, IRQ_DMA0);
497 } else if (dma->nextIRQ < test) {
498 test = dma->nextIRQ;
499 }
500 }
501
502 dma = &memory->dma[1];
503 dma->nextIRQ -= cycles;
504 if (dma->enable && dma->doIrq && dma->nextIRQ) {
505 if (dma->nextIRQ <= 0) {
506 dma->nextIRQ = INT_MAX;
507 GBARaiseIRQ(memory->p, IRQ_DMA1);
508 } else if (dma->nextIRQ < test) {
509 test = dma->nextIRQ;
510 }
511 }
512
513 dma = &memory->dma[2];
514 dma->nextIRQ -= cycles;
515 if (dma->enable && dma->doIrq && dma->nextIRQ) {
516 if (dma->nextIRQ <= 0) {
517 dma->nextIRQ = INT_MAX;
518 GBARaiseIRQ(memory->p, IRQ_DMA2);
519 } else if (dma->nextIRQ < test) {
520 test = dma->nextIRQ;
521 }
522 }
523
524 dma = &memory->dma[3];
525 dma->nextIRQ -= cycles;
526 if (dma->enable && dma->doIrq && dma->nextIRQ) {
527 if (dma->nextIRQ <= 0) {
528 dma->nextIRQ = INT_MAX;
529 GBARaiseIRQ(memory->p, IRQ_DMA3);
530 } else if (dma->nextIRQ < test) {
531 test = dma->nextIRQ;
532 }
533 }
534
535 return test;
536}
537
538void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
539 memory->dma[dma].source = address & 0xFFFFFFFE;
540}
541
542void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
543 memory->dma[dma].dest = address & 0xFFFFFFFE;
544}
545
546void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
547 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
548}
549
550uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
551 struct GBADMA* currentDma = &memory->dma[dma];
552 int wasEnabled = currentDma->enable;
553 currentDma->packed = control;
554 currentDma->nextIRQ = 0;
555
556 if (currentDma->drq) {
557 GBALog(GBA_LOG_STUB, "DRQ not implemented");
558 }
559
560 if (!wasEnabled && currentDma->enable) {
561 currentDma->nextSource = currentDma->source;
562 currentDma->nextDest = currentDma->dest;
563 currentDma->nextCount = currentDma->count;
564 GBAMemoryScheduleDMA(memory, dma, currentDma);
565 }
566 // If the DMA has already occurred, this value might have changed since the function started
567 return currentDma->packed;
568};
569
570void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
571 switch (info->timing) {
572 case DMA_TIMING_NOW:
573 GBAMemoryServiceDMA(memory, number, info);
574 break;
575 case DMA_TIMING_HBLANK:
576 // Handled implicitly
577 break;
578 case DMA_TIMING_VBLANK:
579 // Handled implicitly
580 break;
581 case DMA_TIMING_CUSTOM:
582 switch (number) {
583 case 0:
584 GBALog(GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
585 break;
586 case 1:
587 case 2:
588 //this.cpu.irq.audio.scheduleFIFODma(number, info);
589 break;
590 case 3:
591 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
592 break;
593 }
594 }
595}
596
597void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
598 struct GBADMA* dma;
599 int i;
600 for (i = 0; i < 4; ++i) {
601 dma = &memory->dma[i];
602 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
603 GBAMemoryServiceDMA(memory, i, dma);
604 }
605 }
606}
607
608void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
609 struct GBADMA* dma;
610 int i;
611 for (i = 0; i < 4; ++i) {
612 dma = &memory->dma[i];
613 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
614 GBAMemoryServiceDMA(memory, i, dma);
615 }
616 }
617}
618
619void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
620 if (!info->enable) {
621 // There was a DMA scheduled that got canceled
622 return;
623 }
624
625 uint32_t width = info->width ? 4 : 2;
626 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
627 int destOffset = DMA_OFFSET[info->dstControl] * width;
628 int32_t wordsRemaining = info->nextCount;
629 uint32_t source = info->nextSource;
630 uint32_t dest = info->nextDest;
631 uint32_t sourceRegion = source >> BASE_OFFSET;
632 uint32_t destRegion = dest >> BASE_OFFSET;
633
634 if (width == 4) {
635 int32_t word;
636 source &= 0xFFFFFFFC;
637 dest &= 0xFFFFFFFC;
638 while (wordsRemaining--) {
639 word = GBALoad32(&memory->d, source, 0);
640 GBAStore32(&memory->d, dest, word, 0);
641 source += sourceOffset;
642 dest += destOffset;
643 }
644 } else {
645 uint16_t word;
646 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
647 while (wordsRemaining--) {
648 word = GBASavedataReadEEPROM(&memory->savedata);
649 GBAStore16(&memory->d, dest, word, 0);
650 source += sourceOffset;
651 dest += destOffset;
652 }
653 } else if (destRegion == REGION_CART2_EX) {
654 if (memory->savedata.type != SAVEDATA_EEPROM) {
655 GBASavedataInitEEPROM(&memory->savedata);
656 }
657 while (wordsRemaining) {
658 word = GBALoadU16(&memory->d, source, 0);
659 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
660 source += sourceOffset;
661 dest += destOffset;
662 --wordsRemaining;
663 }
664 } else {
665 while (wordsRemaining--) {
666 word = GBALoadU16(&memory->d, source, 0);
667 GBAStore16(&memory->d, dest, word, 0);
668 source += sourceOffset;
669 dest += destOffset;
670 }
671 }
672 }
673
674 if (info->doIrq) {
675 info->nextIRQ = memory->p->cpu.cycles + 2;
676 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
677 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
678 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
679 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
680 }
681
682 info->nextSource = source;
683 info->nextDest = dest;
684 info->nextCount = wordsRemaining;
685
686 if (!info->repeat) {
687 info->enable = 0;
688
689 // Clear the enable bit in memory
690 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
691 } else {
692 info->nextCount = info->count;
693 if (info->dstControl == DMA_INCREMENT_RELOAD) {
694 info->nextDest = info->dest;
695 }
696 GBAMemoryScheduleDMA(memory, number, info);
697 }
698}