src/arm.c (view raw)
1#include "arm.h"
2
3#define ARM_SIGN(I) ((I) >> 31)
4#define ARM_ROR(I, ROTATE) (((I) >> ROTATE) | (I << (32 - ROTATE)))
5
6static inline void _ARMSetMode(struct ARMCore*, enum ExecutionMode);
7static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
8static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
9
10static inline void _ARMReadCPSR(struct ARMCore* cpu) {
11 _ARMSetMode(cpu, cpu->cpsr.t);
12}
13
14static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
15 return mode != MODE_SYSTEM && mode != MODE_USER;
16}
17
18// Addressing mode 1
19static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
20 // TODO
21}
22
23static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
24 int rotate = (opcode & 0x00000F00) >> 7;
25 int immediate = opcode & 0x000000FF;
26 if (!rotate) {
27 cpu->shifterOperand = immediate;
28 cpu->shifterCarryOut = cpu->cpsr.c;
29 } else {
30 cpu->shifterOperand = ARM_ROR(immediate, rotate);
31 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
32 }
33}
34
35static const ARMInstruction _armTable[0x10000];
36
37static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
38 if (executionMode == cpu->executionMode) {
39 return;
40 }
41
42 cpu->executionMode = executionMode;
43 switch (executionMode) {
44 case MODE_ARM:
45 cpu->cpsr.t = 0;
46 cpu->instructionWidth = WORD_SIZE_ARM;
47 cpu->loadInstruction = _ARMLoadInstructionARM;
48 break;
49 case MODE_THUMB:
50 cpu->cpsr.t = 1;
51 cpu->instructionWidth = WORD_SIZE_THUMB;
52 cpu->loadInstruction = _ARMLoadInstructionThumb;
53 }
54}
55
56static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
57 uint32_t opcode = memory->load32(memory, address);
58 *opcodeOut = opcode;
59 return _armTable[((opcode >> 16) & 0xFFF0) | ((opcode >> 4) & 0x000F)];
60}
61
62static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
63 uint16_t opcode = memory->loadU16(memory, address);
64 *opcodeOut = opcode;
65 return 0;
66}
67
68void ARMInit(struct ARMCore* cpu) {
69 int i;
70 for (i = 0; i < 16; ++i) {
71 cpu->gprs[i] = 0;
72 }
73
74 cpu->cpsr.packed = MODE_SYSTEM;
75 cpu->spsr.packed = 0;
76
77 cpu->cyclesToEvent = 0;
78
79 cpu->shifterOperand = 0;
80 cpu->shifterCarryOut = 0;
81
82 cpu->memory = 0;
83 cpu->board = 0;
84
85 cpu->executionMode = MODE_THUMB;
86 _ARMSetMode(cpu, MODE_ARM);
87}
88
89void ARMAssociateMemory(struct ARMCore* cpu, struct ARMMemory* memory) {
90 cpu->memory = memory;
91}
92
93void ARMStep(struct ARMCore* cpu) {
94 // TODO
95 uint32_t opcode;
96 ARMInstruction instruction = cpu->loadInstruction(cpu->memory, cpu->gprs[ARM_PC] - cpu->instructionWidth, &opcode);
97 cpu->gprs[ARM_PC] += cpu->instructionWidth;
98 instruction(cpu, opcode);
99}
100
101// Instruction definitions
102// Beware pre-processor antics
103
104#define ARM_CARRY_FROM(M, N, D) ((ARM_SIGN((M) | (N))) && !(ARM_SIGN(D)))
105#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
106#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
107#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
108
109#define ARM_COND_EQ (cpu->cpsr.z)
110#define ARM_COND_NE (!cpu->cpsr.z)
111#define ARM_COND_CS (cpu->cpsr.c)
112#define ARM_COND_CC (!cpu->cpsr.c)
113#define ARM_COND_MI (cpu->cpsr.n)
114#define ARM_COND_PL (!cpu->cpsr.n)
115#define ARM_COND_VS (cpu->cpsr.v)
116#define ARM_COND_VC (!cpu->cpsr.v)
117#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
118#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
119#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
120#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
121#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
122#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
123#define ARM_COND_AL 1
124
125#define ARM_ADDITION_S(M, N, D) \
126 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
127 cpu->cpsr = cpu->spsr; \
128 _ARMReadCPSR(cpu); \
129 } else { \
130 cpu->cpsr.n = ARM_SIGN(D); \
131 cpu->cpsr.z = !(D); \
132 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
133 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
134 }
135
136#define ARM_SUBTRACTION_S(M, N, D) \
137 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
138 cpu->cpsr = cpu->spsr; \
139 _ARMReadCPSR(cpu); \
140 } else { \
141 cpu->cpsr.n = ARM_SIGN(D); \
142 cpu->cpsr.z = !(D); \
143 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
144 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
145 }
146
147#define ARM_NEUTRAL_S(M, N, D) \
148 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
149 cpu->cpsr = cpu->spsr; \
150 _ARMReadCPSR(cpu); \
151 } else { \
152 cpu->cpsr.n = ARM_SIGN(D); \
153 cpu->cpsr.z = !(D); \
154 cpu->cpsr.c = cpu->shifterCarryOut; \
155 }
156
157#define ADDR_MODE_2_ADDRESS (address)
158#define ADDR_MODE_2_RN (cpu->gprs[rn])
159#define ADDR_MODE_2_RM (cpu->gprs[rm])
160#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
161#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
162#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
163#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
164#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
165#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
166#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
167
168#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
169#define ADDR_MODE_3_RN ADDR_MODE_2_RN
170#define ADDR_MODE_3_RM ADDR_MODE_2_RM
171#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
172#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
173#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
174
175#define DEFINE_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, BODY) \
176 static void _ARMInstruction ## NAME ## COND (struct ARMCore* cpu, uint32_t opcode) { \
177 if (!COND_BODY) { \
178 return; \
179 } \
180 BODY; \
181 }
182
183#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
184 DEFINE_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, BODY) \
185 DEFINE_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, BODY) \
186 DEFINE_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, BODY) \
187 DEFINE_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, BODY) \
188 DEFINE_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, BODY) \
189 DEFINE_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, BODY) \
190 DEFINE_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, BODY) \
191 DEFINE_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, BODY) \
192 DEFINE_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, BODY) \
193 DEFINE_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, BODY) \
194 DEFINE_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, BODY) \
195 DEFINE_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, BODY) \
196 DEFINE_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, BODY) \
197 DEFINE_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, BODY) \
198 DEFINE_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, BODY)
199
200#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
201 DEFINE_INSTRUCTION_ARM(NAME, \
202 int rd = (opcode >> 12) & 0xF; \
203 int rn = (opcode >> 16) & 0xF; \
204 SHIFTER(cpu, opcode); \
205 BODY; \
206 S_BODY; \
207 POST_BODY;)
208
209#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
210 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
211 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
212 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
213 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
214
215#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
216 DEFINE_INSTRUCTION_ARM(NAME, \
217 uint32_t address; \
218 int rn = (opcode >> 16) & 0xF; \
219 int rd = (opcode >> 12) & 0xF; \
220 int rm = opcode & 0xF; \
221 address = ADDRESS; \
222 BODY; \
223 WRITEBACK;)
224
225#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
226 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
227 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
228 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
229 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
230 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
231 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
232
233
234#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
235 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
236 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
237 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
238 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
239 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
240 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
241 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
242 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
243 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
244 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
245
246#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
247 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
248 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
249 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
250 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
251 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
252 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
253 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
254 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
255 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
256 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
257 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
258 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
259
260// TODO
261#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
262 DEFINE_INSTRUCTION_ARM(NAME, \
263 BODY;)
264
265#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
266 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
267 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DAW, , , BODY) \
268 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , , BODY) \
269 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DBW, , , BODY) \
270 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , , BODY) \
271 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IAW, , , BODY) \
272 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , , BODY) \
273 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IBW, , , BODY) \
274 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, S_PRE, S_POST, BODY) \
275 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DAW, S_PRE, S_POST, BODY) \
276 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, S_PRE, S_POST, BODY) \
277 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DBW, S_PRE, S_POST, BODY) \
278 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, S_PRE, S_POST, BODY) \
279 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IAW, S_PRE, S_POST, BODY) \
280 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, S_PRE, S_POST, BODY) \
281 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IBW, S_PRE, S_POST, BODY)
282
283// Begin ALU definitions
284
285DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
286 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
287
288DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
289 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
290 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
291
292DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
293 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
294
295DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
296 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
297
298DEFINE_ALU_INSTRUCTION_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
299 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
300
301DEFINE_ALU_INSTRUCTION_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
302 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
303
304DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
305 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
306
307DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
308 cpu->gprs[rd] = cpu->shifterOperand;, )
309
310DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
311 cpu->gprs[rd] = ~cpu->shifterOperand;, )
312
313DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
314 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
315
316DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
317 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
318
319DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
320 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
321 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
322
323DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
324 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
325 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
326
327DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
328 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
329
330DEFINE_ALU_INSTRUCTION_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
331 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
332
333DEFINE_ALU_INSTRUCTION_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
334 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
335
336// End ALU definitions
337
338// Begin multiply definitions
339
340DEFINE_INSTRUCTION_ARM(MLA,)
341DEFINE_INSTRUCTION_ARM(MLAS,)
342DEFINE_INSTRUCTION_ARM(MUL,)
343DEFINE_INSTRUCTION_ARM(MULS,)
344DEFINE_INSTRUCTION_ARM(SMLAL,)
345DEFINE_INSTRUCTION_ARM(SMLALS,)
346DEFINE_INSTRUCTION_ARM(SMULL,)
347DEFINE_INSTRUCTION_ARM(SMULLS,)
348DEFINE_INSTRUCTION_ARM(UMLAL,)
349DEFINE_INSTRUCTION_ARM(UMLALS,)
350DEFINE_INSTRUCTION_ARM(UMULL,)
351DEFINE_INSTRUCTION_ARM(UMULLS,)
352
353// End multiply definitions
354
355// Begin load/store definitions
356
357DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
358DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
359DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRBT,)
360DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
361DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
362DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
363DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRT,)
364DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
365DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
366DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRBT,)
367DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
368DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRT,)
369
370DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,)
371DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,)
372
373DEFINE_INSTRUCTION_ARM(SWP,)
374DEFINE_INSTRUCTION_ARM(SWPB,)
375
376// End load/store definitions
377
378// Begin branch definitions
379
380DEFINE_INSTRUCTION_ARM(B, \
381 int32_t offset = opcode << 8; \
382 offset >>= 6; \
383 cpu->gprs[ARM_PC] += offset)
384
385DEFINE_INSTRUCTION_ARM(BL,)
386DEFINE_INSTRUCTION_ARM(BX,)
387
388// End branch definitions
389
390// TODO
391DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
392DEFINE_INSTRUCTION_ARM(MSR,)
393DEFINE_INSTRUCTION_ARM(MRS,)
394DEFINE_INSTRUCTION_ARM(MSRI,)
395DEFINE_INSTRUCTION_ARM(MRSI,)
396DEFINE_INSTRUCTION_ARM(SWI,)
397
398#define DECLARE_INSTRUCTION_ARM(COND, NAME) \
399 _ARMInstruction ## NAME ## COND
400
401#define DO_8(DIRECTIVE) \
402 DIRECTIVE, \
403 DIRECTIVE, \
404 DIRECTIVE, \
405 DIRECTIVE, \
406 DIRECTIVE, \
407 DIRECTIVE, \
408 DIRECTIVE, \
409 DIRECTIVE
410
411#define DO_256(DIRECTIVE) \
412 DO_8(DO_8(DIRECTIVE)), \
413 DO_8(DO_8(DIRECTIVE)), \
414 DO_8(DO_8(DIRECTIVE)), \
415 DO_8(DO_8(DIRECTIVE))
416
417#define DO_INTERLACE(LEFT, RIGHT) \
418 LEFT, \
419 RIGHT
420
421#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ALU) \
422 DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I)), \
423 DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I))
424
425#define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
426 DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
427 DECLARE_INSTRUCTION_ARM(COND, ALU), \
428 DECLARE_INSTRUCTION_ARM(COND, EX1), \
429 DECLARE_INSTRUCTION_ARM(COND, ALU), \
430 DECLARE_INSTRUCTION_ARM(COND, EX2), \
431 DECLARE_INSTRUCTION_ARM(COND, ALU), \
432 DECLARE_INSTRUCTION_ARM(COND, EX3), \
433 DECLARE_INSTRUCTION_ARM(COND, ALU), \
434 DECLARE_INSTRUCTION_ARM(COND, EX4)
435
436#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, NAME, P, U, W) \
437 DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)), \
438 DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W))
439
440#define DECLARE_ARM_LOAD_STORE_BLOCK(COND, NAME, P, U, W) \
441 DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSL_ ## P ## U ## W), \
442 DECLARE_INSTRUCTION_ARM(COND, ILL), \
443 DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSR_ ## P ## U ## W), \
444 DECLARE_INSTRUCTION_ARM(COND, ILL), \
445 DECLARE_INSTRUCTION_ARM(COND, NAME ## _ASR_ ## P ## U ## W), \
446 DECLARE_INSTRUCTION_ARM(COND, ILL), \
447 DECLARE_INSTRUCTION_ARM(COND, NAME ## _ROR_ ## P ## U ## W), \
448 DECLARE_INSTRUCTION_ARM(COND, ILL), \
449 DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSL_ ## P ## U ## W), \
450 DECLARE_INSTRUCTION_ARM(COND, ILL), \
451 DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSR_ ## P ## U ## W), \
452 DECLARE_INSTRUCTION_ARM(COND, ILL), \
453 DECLARE_INSTRUCTION_ARM(COND, NAME ## _ASR_ ## P ## U ## W), \
454 DECLARE_INSTRUCTION_ARM(COND, ILL), \
455 DECLARE_INSTRUCTION_ARM(COND, NAME ## _ROR_ ## P ## U ## W), \
456 DECLARE_INSTRUCTION_ARM(COND, ILL)
457
458#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, NAME, MODE, W) \
459 DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W)), \
460 DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W))
461
462#define DECLARE_ARM_BRANCH_BLOCK(COND, NAME) \
463 DO_256(DECLARE_INSTRUCTION_ARM(COND, NAME))
464
465// TODO: Support coprocessors
466#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, NAME, P, U, W, N) \
467 DO_8(0), \
468 DO_8(0)
469
470#define DECLARE_ARM_COPROCESSOR_BLOCK(COND, NAME1, NAME2) \
471 DO_8(DO_8(DO_INTERLACE(0, 0))), \
472 DO_8(DO_8(DO_INTERLACE(0, 0)))
473
474#define DECLARE_ARM_SWI_BLOCK(COND) \
475 DO_256(DECLARE_INSTRUCTION_ARM(COND, SWI))
476
477#define DECLARE_COND_BLOCK(COND) \
478 DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \
479 DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
480 DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, ILL, ILL, ILL), \
481 DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, ILL, ILL, ILL), \
482 DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRHI, ILL, ILL), \
483 DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
484 DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, ILL, ILL, ILL), \
485 DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, ILL, ILL, ILL), \
486 DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRHU, ILL, ILL), \
487 DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
488 DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, ILL, ILL, ILL), \
489 DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, ILL, ILL, ILL), \
490 DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRHIU, ILL, ILL), \
491 DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
492 DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, ILL, ILL, ILL), \
493 DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, ILL, ILL, ILL), \
494 DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \
495 DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
496 DECLARE_INSTRUCTION_ARM(COND, MSR), \
497 DECLARE_INSTRUCTION_ARM(COND, BX), \
498 DECLARE_INSTRUCTION_ARM(COND, ILL), \
499 DECLARE_INSTRUCTION_ARM(COND, ILL), \
500 DECLARE_INSTRUCTION_ARM(COND, ILL), \
501 DECLARE_INSTRUCTION_ARM(COND, ILL), \
502 DECLARE_INSTRUCTION_ARM(COND, ILL), \
503 DECLARE_INSTRUCTION_ARM(COND, ILL), \
504 DECLARE_INSTRUCTION_ARM(COND, ILL), \
505 DECLARE_INSTRUCTION_ARM(COND, ILL), \
506 DECLARE_INSTRUCTION_ARM(COND, ILL), \
507 DECLARE_INSTRUCTION_ARM(COND, STRHPW), \
508 DECLARE_INSTRUCTION_ARM(COND, ILL), \
509 DECLARE_INSTRUCTION_ARM(COND, ILL), \
510 DECLARE_INSTRUCTION_ARM(COND, ILL), \
511 DECLARE_INSTRUCTION_ARM(COND, ILL), \
512 DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
513 DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRHIP, ILL, ILL), \
514 DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
515 DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHIPW, ILL, ILL), \
516 DECLARE_ARM_ALU_BLOCK(COND, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
517 DECLARE_ARM_ALU_BLOCK(COND, ORR, SMLAL, STRHPU, ILL, ILL), \
518 DECLARE_ARM_ALU_BLOCK(COND, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
519 DECLARE_ARM_ALU_BLOCK(COND, MOV, SMLAL, STRHPUW, ILL, ILL), \
520 DECLARE_ARM_ALU_BLOCK(COND, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
521 DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRHIPU, ILL, ILL), \
522 DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
523 DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRHIPUW, ILL, ILL), \
524 DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
525 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, AND), \
526 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ANDS), \
527 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EOR), \
528 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EORS), \
529 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUB), \
530 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUBS), \
531 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSB), \
532 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSBS), \
533 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADD), \
534 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADDS), \
535 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADC), \
536 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADCS), \
537 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBC), \
538 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBCS), \
539 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSC), \
540 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSCS), \
541 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
542 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TST), \
543 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
544 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TEQ), \
545 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
546 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMP), \
547 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
548 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMN), \
549 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORR), \
550 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORRS), \
551 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOV), \
552 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOVS), \
553 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BIC), \
554 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \
555 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \
556 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS), \
557 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , ), \
558 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , ), \
559 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRT, , , ), \
560 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRT, , , ), \
561 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , ), \
562 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , ), \
563 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRBT, , , ), \
564 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRBT, , , ), \
565 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, ), \
566 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, ), \
567 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRT, , U, ), \
568 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRT, , U, ), \
569 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, ), \
570 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, ), \
571 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRBT, , U, ), \
572 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRBT, , U, ), \
573 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , ), \
574 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , ), \
575 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , W), \
576 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , W), \
577 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , ), \
578 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , ), \
579 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , W), \
580 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , W), \
581 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, ), \
582 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, ), \
583 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, W), \
584 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, W), \
585 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, ), \
586 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, ), \
587 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, W), \
588 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, W), \
589 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , ), \
590 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , ), \
591 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRT, , , ), \
592 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRT, , , ), \
593 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , ), \
594 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , ), \
595 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRBT, , , ), \
596 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRBT, , , ), \
597 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, ), \
598 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, ), \
599 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRT, , U, ), \
600 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRT, , U, ), \
601 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, ), \
602 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, ), \
603 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRBT, , U, ), \
604 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRBT, , U, ), \
605 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , ), \
606 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , ), \
607 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , W), \
608 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , W), \
609 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , ), \
610 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , ), \
611 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , W), \
612 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , W), \
613 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, ), \
614 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, ), \
615 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, W), \
616 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, W), \
617 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, ), \
618 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, ), \
619 DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, W), \
620 DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W), \
621 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DA, ), \
622 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DA, ), \
623 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DA, W), \
624 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DA, W), \
625 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DA, ), \
626 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DA, ), \
627 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DA, W), \
628 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DA, W), \
629 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IA, ), \
630 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IA, ), \
631 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IA, W), \
632 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IA, W), \
633 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IA, ), \
634 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IA, ), \
635 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IA, W), \
636 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IA, W), \
637 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DB, ), \
638 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DB, ), \
639 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, DB, W), \
640 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, DB, W), \
641 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DB, ), \
642 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DB, ), \
643 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, DB, W), \
644 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, DB, W), \
645 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IB, ), \
646 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IB, ), \
647 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, IB, W), \
648 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IB, W), \
649 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, ), \
650 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, ), \
651 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, W), \
652 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, W), \
653 DECLARE_ARM_BRANCH_BLOCK(COND, B), \
654 DECLARE_ARM_BRANCH_BLOCK(COND, BL), \
655 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \
656 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \
657 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \
658 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , W), \
659 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, ), \
660 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, ), \
661 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, W), \
662 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, W), \
663 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , ), \
664 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , ), \
665 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , W), \
666 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , W), \
667 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, ), \
668 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, ), \
669 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, W), \
670 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, W), \
671 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , ), \
672 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , ), \
673 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , W), \
674 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , W), \
675 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \
676 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \
677 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \
678 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \
679 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, ), \
680 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, ), \
681 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, W), \
682 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, W), \
683 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \
684 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \
685 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \
686 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \
687 DECLARE_ARM_COPROCESSOR_BLOCK(COND, CDP, MCR), \
688 DECLARE_ARM_SWI_BLOCK(COND)
689
690#define DECLARE_EMPTY_BLOCK \
691 DO_8(DO_256(0)), \
692 DO_8(DO_256(0))
693
694static const ARMInstruction _armTable[0x10000] = {
695 DECLARE_COND_BLOCK(EQ),
696 DECLARE_COND_BLOCK(NE),
697 DECLARE_COND_BLOCK(CS),
698 DECLARE_COND_BLOCK(CC),
699 DECLARE_COND_BLOCK(MI),
700 DECLARE_COND_BLOCK(PL),
701 DECLARE_COND_BLOCK(VS),
702 DECLARE_COND_BLOCK(VC),
703 DECLARE_COND_BLOCK(HI),
704 DECLARE_COND_BLOCK(LS),
705 DECLARE_COND_BLOCK(GE),
706 DECLARE_COND_BLOCK(LT),
707 DECLARE_COND_BLOCK(GT),
708 DECLARE_COND_BLOCK(LE),
709 DECLARE_COND_BLOCK(AL),
710 DECLARE_EMPTY_BLOCK
711};