src/arm/arm.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/arm.h>
7
8#include <mgba/internal/arm/isa-arm.h>
9#include <mgba/internal/arm/isa-inlines.h>
10#include <mgba/internal/arm/isa-thumb.h>
11
12static inline enum RegisterBank _ARMSelectBank(enum PrivilegeMode);
13
14void ARMSetPrivilegeMode(struct ARMCore* cpu, enum PrivilegeMode mode) {
15 if (mode == cpu->privilegeMode) {
16 // Not switching modes after all
17 return;
18 }
19
20 enum RegisterBank newBank = _ARMSelectBank(mode);
21 enum RegisterBank oldBank = _ARMSelectBank(cpu->privilegeMode);
22 if (newBank != oldBank) {
23 // Switch banked registers
24 if (mode == MODE_FIQ || cpu->privilegeMode == MODE_FIQ) {
25 int oldFIQBank = oldBank == BANK_FIQ;
26 int newFIQBank = newBank == BANK_FIQ;
27 cpu->bankedRegisters[oldFIQBank][2] = cpu->gprs[8];
28 cpu->bankedRegisters[oldFIQBank][3] = cpu->gprs[9];
29 cpu->bankedRegisters[oldFIQBank][4] = cpu->gprs[10];
30 cpu->bankedRegisters[oldFIQBank][5] = cpu->gprs[11];
31 cpu->bankedRegisters[oldFIQBank][6] = cpu->gprs[12];
32 cpu->gprs[8] = cpu->bankedRegisters[newFIQBank][2];
33 cpu->gprs[9] = cpu->bankedRegisters[newFIQBank][3];
34 cpu->gprs[10] = cpu->bankedRegisters[newFIQBank][4];
35 cpu->gprs[11] = cpu->bankedRegisters[newFIQBank][5];
36 cpu->gprs[12] = cpu->bankedRegisters[newFIQBank][6];
37 }
38 cpu->bankedRegisters[oldBank][0] = cpu->gprs[ARM_SP];
39 cpu->bankedRegisters[oldBank][1] = cpu->gprs[ARM_LR];
40 cpu->gprs[ARM_SP] = cpu->bankedRegisters[newBank][0];
41 cpu->gprs[ARM_LR] = cpu->bankedRegisters[newBank][1];
42
43 cpu->bankedSPSRs[oldBank] = cpu->spsr.packed;
44 cpu->spsr.packed = cpu->bankedSPSRs[newBank];
45 }
46 cpu->privilegeMode = mode;
47}
48
49static inline enum RegisterBank _ARMSelectBank(enum PrivilegeMode mode) {
50 switch (mode) {
51 case MODE_USER:
52 case MODE_SYSTEM:
53 // No banked registers
54 return BANK_NONE;
55 case MODE_FIQ:
56 return BANK_FIQ;
57 case MODE_IRQ:
58 return BANK_IRQ;
59 case MODE_SUPERVISOR:
60 return BANK_SUPERVISOR;
61 case MODE_ABORT:
62 return BANK_ABORT;
63 case MODE_UNDEFINED:
64 return BANK_UNDEFINED;
65 default:
66 // This should be unreached
67 return BANK_NONE;
68 }
69}
70
71void ARMInit(struct ARMCore* cpu) {
72 memset(&cpu->cp15, 0, sizeof(cpu->cp15));
73 cpu->master->init(cpu, cpu->master);
74 size_t i;
75 for (i = 0; i < cpu->numComponents; ++i) {
76 if (cpu->components[i] && cpu->components[i]->init) {
77 cpu->components[i]->init(cpu, cpu->components[i]);
78 }
79 }
80}
81
82void ARMDeinit(struct ARMCore* cpu) {
83 if (cpu->master->deinit) {
84 cpu->master->deinit(cpu->master);
85 }
86 size_t i;
87 for (i = 0; i < cpu->numComponents; ++i) {
88 if (cpu->components[i] && cpu->components[i]->deinit) {
89 cpu->components[i]->deinit(cpu->components[i]);
90 }
91 }
92}
93
94void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras) {
95 cpu->master = master;
96 cpu->numComponents = extra;
97 cpu->components = extras;
98}
99
100void ARMHotplugAttach(struct ARMCore* cpu, size_t slot) {
101 if (slot >= cpu->numComponents) {
102 return;
103 }
104 cpu->components[slot]->init(cpu, cpu->components[slot]);
105}
106
107void ARMHotplugDetach(struct ARMCore* cpu, size_t slot) {
108 if (slot >= cpu->numComponents) {
109 return;
110 }
111 cpu->components[slot]->deinit(cpu->components[slot]);
112}
113
114void ARMReset(struct ARMCore* cpu) {
115 int i;
116 for (i = 0; i < 16; ++i) {
117 cpu->gprs[i] = 0;
118 }
119 if (ARMControlRegIsVE(cpu->cp15.r1.c0)) {
120 cpu->gprs[ARM_PC] = 0xFFFF0000;
121 }
122
123 for (i = 0; i < 6; ++i) {
124 cpu->bankedRegisters[i][0] = 0;
125 cpu->bankedRegisters[i][1] = 0;
126 cpu->bankedRegisters[i][2] = 0;
127 cpu->bankedRegisters[i][3] = 0;
128 cpu->bankedRegisters[i][4] = 0;
129 cpu->bankedRegisters[i][5] = 0;
130 cpu->bankedRegisters[i][6] = 0;
131 cpu->bankedSPSRs[i] = 0;
132 }
133
134 cpu->privilegeMode = MODE_SYSTEM;
135 cpu->cpsr.packed = MODE_SYSTEM;
136 cpu->spsr.packed = 0;
137
138 cpu->shifterOperand = 0;
139 cpu->shifterCarryOut = 0;
140
141 cpu->executionMode = MODE_THUMB;
142 _ARMSetMode(cpu, MODE_ARM);
143 ARMWritePC(cpu);
144
145 cpu->cycles = 0;
146 cpu->nextEvent = 0;
147 cpu->halted = 0;
148
149 cpu->irqh.reset(cpu);
150}
151
152void ARMRaiseIRQ(struct ARMCore* cpu) {
153 if (cpu->cpsr.i) {
154 return;
155 }
156 union PSR cpsr = cpu->cpsr;
157 int instructionWidth;
158 if (cpu->executionMode == MODE_THUMB) {
159 instructionWidth = WORD_SIZE_THUMB;
160 } else {
161 instructionWidth = WORD_SIZE_ARM;
162 }
163 ARMSetPrivilegeMode(cpu, MODE_IRQ);
164 cpu->cpsr.priv = MODE_IRQ;
165 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - instructionWidth + WORD_SIZE_ARM;
166 cpu->gprs[ARM_PC] = BASE_IRQ;
167 if (ARMControlRegIsVE(cpu->cp15.r1.c0)) {
168 cpu->gprs[ARM_PC] |= 0xFFFF0000;
169 }
170 _ARMSetMode(cpu, MODE_ARM);
171 cpu->cycles += ARMWritePC(cpu);
172 cpu->spsr = cpsr;
173 cpu->cpsr.i = 1;
174 cpu->halted = 0;
175}
176
177void ARMRaiseSWI(struct ARMCore* cpu) {
178 union PSR cpsr = cpu->cpsr;
179 int instructionWidth;
180 if (cpu->executionMode == MODE_THUMB) {
181 instructionWidth = WORD_SIZE_THUMB;
182 } else {
183 instructionWidth = WORD_SIZE_ARM;
184 }
185 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
186 cpu->cpsr.priv = MODE_SUPERVISOR;
187 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - instructionWidth;
188 cpu->gprs[ARM_PC] = BASE_SWI;
189 if (ARMControlRegIsVE(cpu->cp15.r1.c0)) {
190 cpu->gprs[ARM_PC] |= 0xFFFF0000;
191 }
192 _ARMSetMode(cpu, MODE_ARM);
193 cpu->cycles += ARMWritePC(cpu);
194 cpu->spsr = cpsr;
195 cpu->cpsr.i = 1;
196}
197
198void ARMRaiseUndefined(struct ARMCore* cpu) {
199 union PSR cpsr = cpu->cpsr;
200 int instructionWidth;
201 if (cpu->executionMode == MODE_THUMB) {
202 instructionWidth = WORD_SIZE_THUMB;
203 } else {
204 instructionWidth = WORD_SIZE_ARM;
205 }
206 ARMSetPrivilegeMode(cpu, MODE_UNDEFINED);
207 cpu->cpsr.priv = MODE_UNDEFINED;
208 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - instructionWidth;
209 cpu->gprs[ARM_PC] = BASE_UNDEF;
210 if (ARMControlRegIsVE(cpu->cp15.r1.c0)) {
211 cpu->gprs[ARM_PC] |= 0xFFFF0000;
212 }
213 _ARMSetMode(cpu, MODE_ARM);
214 cpu->cycles += ARMWritePC(cpu);
215 cpu->spsr = cpsr;
216 cpu->cpsr.i = 1;
217}
218
219void ARMHalt(struct ARMCore* cpu) {
220 cpu->nextEvent = cpu->cycles;
221 cpu->halted = 1;
222}
223
224#define ARM_IMPLEMENT(VERSION) \
225 static inline void ARM ## VERSION ## Step(struct ARMCore* cpu) { \
226 uint32_t opcode = cpu->prefetch[0]; \
227 cpu->prefetch[0] = cpu->prefetch[1]; \
228 cpu->gprs[ARM_PC] += WORD_SIZE_ARM; \
229 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
230 \
231 ARMInstruction instruction; \
232 unsigned condition = opcode >> 28; \
233 if (condition != 0xE) { \
234 bool conditionMet = false; \
235 switch (condition) { \
236 case 0x0: \
237 conditionMet = ARM_COND_EQ; \
238 break; \
239 case 0x1: \
240 conditionMet = ARM_COND_NE; \
241 break; \
242 case 0x2: \
243 conditionMet = ARM_COND_CS; \
244 break; \
245 case 0x3: \
246 conditionMet = ARM_COND_CC; \
247 break; \
248 case 0x4: \
249 conditionMet = ARM_COND_MI; \
250 break; \
251 case 0x5: \
252 conditionMet = ARM_COND_PL; \
253 break; \
254 case 0x6: \
255 conditionMet = ARM_COND_VS; \
256 break; \
257 case 0x7: \
258 conditionMet = ARM_COND_VC; \
259 break; \
260 case 0x8: \
261 conditionMet = ARM_COND_HI; \
262 break; \
263 case 0x9: \
264 conditionMet = ARM_COND_LS; \
265 break; \
266 case 0xA: \
267 conditionMet = ARM_COND_GE; \
268 break; \
269 case 0xB: \
270 conditionMet = ARM_COND_LT; \
271 break; \
272 case 0xC: \
273 conditionMet = ARM_COND_GT; \
274 break; \
275 case 0xD: \
276 conditionMet = ARM_COND_LE; \
277 break; \
278 default: \
279 instruction = _arm ## VERSION ## FTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)]; \
280 instruction(cpu, opcode); \
281 return; \
282 } \
283 if (!conditionMet) { \
284 cpu->cycles += ARM_PREFETCH_CYCLES; \
285 return; \
286 } \
287 } \
288 instruction = _arm ## VERSION ## Table[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)]; \
289 instruction(cpu, opcode); \
290 } \
291 \
292 static inline void Thumb ## VERSION ## Step(struct ARMCore* cpu) { \
293 uint32_t opcode = cpu->prefetch[0]; \
294 cpu->prefetch[0] = cpu->prefetch[1]; \
295 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB; \
296 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
297 ThumbInstruction instruction = _thumb ## VERSION ## Table[opcode >> 6]; \
298 instruction(cpu, opcode); \
299 } \
300 \
301 void ARM ## VERSION ## Run(struct ARMCore* cpu) { \
302 if (cpu->cycles < cpu->nextEvent) { \
303 if (cpu->executionMode == MODE_THUMB) { \
304 Thumb ## VERSION ## Step(cpu); \
305 } else { \
306 ARM ## VERSION ## Step(cpu); \
307 } \
308 } \
309 if (cpu->cycles >= cpu->nextEvent) { \
310 cpu->irqh.processEvents(cpu); \
311 } \
312 } \
313 \
314 void ARM ## VERSION ## RunLoop(struct ARMCore* cpu) { \
315 if (cpu->executionMode == MODE_THUMB) { \
316 while (cpu->cycles < cpu->nextEvent) { \
317 Thumb ## VERSION ## Step(cpu); \
318 } \
319 } else { \
320 while (cpu->cycles < cpu->nextEvent) { \
321 ARM ## VERSION ## Step(cpu); \
322 } \
323 } \
324 cpu->irqh.processEvents(cpu); \
325 }
326
327ARM_IMPLEMENT(v4)
328ARM_IMPLEMENT(v5)
329
330void ARMRunFake(struct ARMCore* cpu, uint32_t opcode) {
331 if (cpu->executionMode == MODE_ARM) {
332 cpu->gprs[ARM_PC] -= WORD_SIZE_ARM;
333 } else {
334 cpu->gprs[ARM_PC] -= WORD_SIZE_THUMB;
335 }
336 cpu->prefetch[1] = cpu->prefetch[0];
337 cpu->prefetch[0] = opcode;
338}