1#ifndef ISA_INLINES_H
  2#define ISA_INLINES_H
  3
  4#include "common.h"
  5
  6#include "arm.h"
  7
  8#define DO_4(DIRECTIVE) \
  9	DIRECTIVE, \
 10	DIRECTIVE, \
 11	DIRECTIVE, \
 12	DIRECTIVE
 13
 14#define DO_8(DIRECTIVE) \
 15	DIRECTIVE, \
 16	DIRECTIVE, \
 17	DIRECTIVE, \
 18	DIRECTIVE, \
 19	DIRECTIVE, \
 20	DIRECTIVE, \
 21	DIRECTIVE, \
 22	DIRECTIVE
 23
 24#define DO_256(DIRECTIVE) \
 25	DO_4(DO_8(DO_8(DIRECTIVE)))
 26
 27#define DO_INTERLACE(LEFT, RIGHT) \
 28	LEFT, \
 29	RIGHT
 30
 31#define ARM_COND_EQ (cpu->cpsr.z)
 32#define ARM_COND_NE (!cpu->cpsr.z)
 33#define ARM_COND_CS (cpu->cpsr.c)
 34#define ARM_COND_CC (!cpu->cpsr.c)
 35#define ARM_COND_MI (cpu->cpsr.n)
 36#define ARM_COND_PL (!cpu->cpsr.n)
 37#define ARM_COND_VS (cpu->cpsr.v)
 38#define ARM_COND_VC (!cpu->cpsr.v)
 39#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
 40#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
 41#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
 42#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
 43#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
 44#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
 45#define ARM_COND_AL 1
 46
 47#define ARM_SIGN(I) ((I) >> 31)
 48#define ARM_ROR(I, ROTATE) ((((uint32_t) (I)) >> ROTATE) | ((I) << (32 - ROTATE)))
 49
 50#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
 51#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
 52#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
 53#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
 54
 55#define ARM_WAIT_MUL(R) \
 56	if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
 57		cpu->cycles += 1; \
 58	} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
 59		cpu->cycles += 2; \
 60	} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
 61		cpu->cycles += 3; \
 62	} else { \
 63		cpu->cycles += 4; \
 64	}
 65
 66#define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
 67#define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
 68
 69#define ARM_WRITE_PC \
 70	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM) + WORD_SIZE_ARM; \
 71	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC] - WORD_SIZE_ARM); \
 72	currentCycles += 2 + cpu->memory.activeNonseqCycles32 + cpu->memory.activePrefetchCycles32;
 73
 74#define THUMB_WRITE_PC \
 75	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB) + WORD_SIZE_THUMB; \
 76	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC] - WORD_SIZE_THUMB); \
 77	currentCycles += 2 + cpu->memory.activeNonseqCycles16 + cpu->memory.activePrefetchCycles16;
 78
 79static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
 80	return mode != MODE_SYSTEM && mode != MODE_USER;
 81}
 82
 83static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
 84	if (executionMode == cpu->executionMode) {
 85		return;
 86	}
 87
 88	cpu->executionMode = executionMode;
 89	switch (executionMode) {
 90	case MODE_ARM:
 91		cpu->cpsr.t = 0;
 92		break;
 93	case MODE_THUMB:
 94		cpu->cpsr.t = 1;
 95	}
 96}
 97
 98static inline void _ARMReadCPSR(struct ARMCore* cpu) {
 99	_ARMSetMode(cpu, cpu->cpsr.t);
100	ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
101	cpu->irqh.readCPSR(cpu);
102}
103
104#endif