src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-arm.h"
7
8#include "arm.h"
9#include "emitter-arm.h"
10#include "isa-inlines.h"
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int shift = cpu->gprs[rs];
23 if (rs == ARM_PC) {
24 shift += 4;
25 }
26 shift &= 0xFF;
27 int32_t shiftVal = cpu->gprs[rm];
28 if (rm == ARM_PC) {
29 shiftVal += 4;
30 }
31 if (!shift) {
32 cpu->shifterOperand = shiftVal;
33 cpu->shifterCarryOut = cpu->cpsr.c;
34 } else if (shift < 32) {
35 cpu->shifterOperand = shiftVal << shift;
36 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
37 } else if (shift == 32) {
38 cpu->shifterOperand = 0;
39 cpu->shifterCarryOut = shiftVal & 1;
40 } else {
41 cpu->shifterOperand = 0;
42 cpu->shifterCarryOut = 0;
43 }
44 } else {
45 int immediate = (opcode & 0x00000F80) >> 7;
46 if (!immediate) {
47 cpu->shifterOperand = cpu->gprs[rm];
48 cpu->shifterCarryOut = cpu->cpsr.c;
49 } else {
50 cpu->shifterOperand = cpu->gprs[rm] << immediate;
51 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
52 }
53 }
54}
55
56static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
57 int rm = opcode & 0x0000000F;
58 if (opcode & 0x00000010) {
59 int rs = (opcode >> 8) & 0x0000000F;
60 ++cpu->cycles;
61 int shift = cpu->gprs[rs];
62 if (rs == ARM_PC) {
63 shift += 4;
64 }
65 shift &= 0xFF;
66 uint32_t shiftVal = cpu->gprs[rm];
67 if (rm == ARM_PC) {
68 shiftVal += 4;
69 }
70 if (!shift) {
71 cpu->shifterOperand = shiftVal;
72 cpu->shifterCarryOut = cpu->cpsr.c;
73 } else if (shift < 32) {
74 cpu->shifterOperand = shiftVal >> shift;
75 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
76 } else if (shift == 32) {
77 cpu->shifterOperand = 0;
78 cpu->shifterCarryOut = shiftVal >> 31;
79 } else {
80 cpu->shifterOperand = 0;
81 cpu->shifterCarryOut = 0;
82 }
83 } else {
84 int immediate = (opcode & 0x00000F80) >> 7;
85 if (immediate) {
86 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
87 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
91 }
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 if (opcode & 0x00000010) {
98 int rs = (opcode >> 8) & 0x0000000F;
99 ++cpu->cycles;
100 int shift = cpu->gprs[rs];
101 if (rs == ARM_PC) {
102 shift += 4;
103 }
104 shift &= 0xFF;
105 int shiftVal = cpu->gprs[rm];
106 if (rm == ARM_PC) {
107 shiftVal += 4;
108 }
109 if (!shift) {
110 cpu->shifterOperand = shiftVal;
111 cpu->shifterCarryOut = cpu->cpsr.c;
112 } else if (shift < 32) {
113 cpu->shifterOperand = shiftVal >> shift;
114 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
115 } else if (cpu->gprs[rm] >> 31) {
116 cpu->shifterOperand = 0xFFFFFFFF;
117 cpu->shifterCarryOut = 1;
118 } else {
119 cpu->shifterOperand = 0;
120 cpu->shifterCarryOut = 0;
121 }
122 } else {
123 int immediate = (opcode & 0x00000F80) >> 7;
124 if (immediate) {
125 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
126 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
127 } else {
128 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
129 cpu->shifterOperand = cpu->shifterCarryOut;
130 }
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 if (opcode & 0x00000010) {
137 int rs = (opcode >> 8) & 0x0000000F;
138 ++cpu->cycles;
139 int shift = cpu->gprs[rs];
140 if (rs == ARM_PC) {
141 shift += 4;
142 }
143 shift &= 0xFF;
144 int shiftVal = cpu->gprs[rm];
145 if (rm == ARM_PC) {
146 shiftVal += 4;
147 }
148 int rotate = shift & 0x1F;
149 if (!shift) {
150 cpu->shifterOperand = shiftVal;
151 cpu->shifterCarryOut = cpu->cpsr.c;
152 } else if (rotate) {
153 cpu->shifterOperand = ROR(shiftVal, rotate);
154 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
155 } else {
156 cpu->shifterOperand = shiftVal;
157 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
158 }
159 } else {
160 int immediate = (opcode & 0x00000F80) >> 7;
161 if (immediate) {
162 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
163 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
164 } else {
165 // RRX
166 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
167 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
168 }
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187#define ARM_ADDITION_S(M, N, D) \
188 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
189 cpu->cpsr = cpu->spsr; \
190 _ARMReadCPSR(cpu); \
191 } else { \
192 cpu->cpsr.n = ARM_SIGN(D); \
193 cpu->cpsr.z = !(D); \
194 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
195 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
196 }
197
198#define ARM_SUBTRACTION_S(M, N, D) \
199 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
200 cpu->cpsr = cpu->spsr; \
201 _ARMReadCPSR(cpu); \
202 } else { \
203 cpu->cpsr.n = ARM_SIGN(D); \
204 cpu->cpsr.z = !(D); \
205 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
206 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
207 }
208
209#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
210 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
211 cpu->cpsr = cpu->spsr; \
212 _ARMReadCPSR(cpu); \
213 } else { \
214 cpu->cpsr.n = ARM_SIGN(D); \
215 cpu->cpsr.z = !(D); \
216 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
217 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
218 }
219
220#define ARM_NEUTRAL_S(M, N, D) \
221 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
222 cpu->cpsr = cpu->spsr; \
223 _ARMReadCPSR(cpu); \
224 } else { \
225 cpu->cpsr.n = ARM_SIGN(D); \
226 cpu->cpsr.z = !(D); \
227 cpu->cpsr.c = cpu->shifterCarryOut; \
228 }
229
230#define ARM_NEUTRAL_HI_S(DLO, DHI) \
231 cpu->cpsr.n = ARM_SIGN(DHI); \
232 cpu->cpsr.z = !((DHI) | (DLO));
233
234#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
235#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
236#define ADDR_MODE_2_ADDRESS (address)
237#define ADDR_MODE_2_RN (cpu->gprs[rn])
238#define ADDR_MODE_2_RM (cpu->gprs[rm])
239#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
240#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
241#define ADDR_MODE_2_WRITEBACK(ADDR) \
242 cpu->gprs[rn] = ADDR; \
243 if (UNLIKELY(rn == ARM_PC)) { \
244 ARM_WRITE_PC; \
245 }
246
247#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
248#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
249#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
250#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
251
252#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
253#define ADDR_MODE_3_RN ADDR_MODE_2_RN
254#define ADDR_MODE_3_RM ADDR_MODE_2_RM
255#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
256#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
257#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
258
259#define ADDR_MODE_4_WRITEBACK_LDM \
260 if (!((1 << rn) & rs)) { \
261 cpu->gprs[rn] = address; \
262 }
263
264#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
265
266#define ARM_LOAD_POST_BODY \
267 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
268 if (rd == ARM_PC) { \
269 ARM_WRITE_PC; \
270 }
271
272#define ARM_STORE_POST_BODY \
273 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
274
275#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
276 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
277 int currentCycles = ARM_PREFETCH_CYCLES; \
278 BODY; \
279 cpu->cycles += currentCycles; \
280 }
281
282#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
283 DEFINE_INSTRUCTION_ARM(NAME, \
284 int rd = (opcode >> 12) & 0xF; \
285 int rn = (opcode >> 16) & 0xF; \
286 UNUSED(rn); \
287 SHIFTER(cpu, opcode); \
288 BODY; \
289 S_BODY; \
290 if (rd == ARM_PC) { \
291 if (cpu->executionMode == MODE_ARM) { \
292 ARM_WRITE_PC; \
293 } else { \
294 THUMB_WRITE_PC; \
295 } \
296 })
297
298#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
309
310#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
316
317#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
318 DEFINE_INSTRUCTION_ARM(NAME, \
319 int rd = (opcode >> 12) & 0xF; \
320 int rdHi = (opcode >> 16) & 0xF; \
321 int rs = (opcode >> 8) & 0xF; \
322 int rm = opcode & 0xF; \
323 if (rdHi == ARM_PC || rd == ARM_PC) { \
324 return; \
325 } \
326 ARM_WAIT_MUL(cpu->gprs[rs]); \
327 BODY; \
328 S_BODY; \
329 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
330
331#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
332 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
333 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
334
335#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
336 DEFINE_INSTRUCTION_ARM(NAME, \
337 uint32_t address; \
338 int rn = (opcode >> 16) & 0xF; \
339 int rd = (opcode >> 12) & 0xF; \
340 int rm = opcode & 0xF; \
341 UNUSED(rm); \
342 address = ADDRESS; \
343 WRITEBACK; \
344 BODY;)
345
346#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
347 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
350 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
351 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
353
354#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
355 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
356 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
357 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
358 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
365
366#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
370 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
371 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
379
380#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
383
384#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
385 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
386 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
387 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
388 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
391
392#define ARM_MS_PRE \
393 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
394 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
395
396#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
397
398#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
399 DEFINE_INSTRUCTION_ARM(NAME, \
400 int rn = (opcode >> 16) & 0xF; \
401 int rs = opcode & 0x0000FFFF; \
402 uint32_t address = cpu->gprs[rn]; \
403 S_PRE; \
404 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
405 S_POST; \
406 POST_BODY; \
407 WRITEBACK;)
408
409
410#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
411 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
412 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
413 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
414 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
415 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
416 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
417 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
418 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
419 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
420 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
421 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
422 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
423 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
424 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
425 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
426 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
427
428// Begin ALU definitions
429
430DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
431 int32_t n = cpu->gprs[rn];
432 cpu->gprs[rd] = n + cpu->shifterOperand;)
433
434DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
435 int32_t n = cpu->gprs[rn];
436 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
437
438DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
439 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
440
441DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
442 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
443
444DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
445 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
446
447DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
448 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
449
450DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
451 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
452
453DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
454 cpu->gprs[rd] = cpu->shifterOperand;)
455
456DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
457 cpu->gprs[rd] = ~cpu->shifterOperand;)
458
459DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
460 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
461
462DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
463 int32_t n = cpu->gprs[rn];
464 cpu->gprs[rd] = cpu->shifterOperand - n;)
465
466DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
467 int32_t n = cpu->gprs[rn];
468 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
469
470DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
471 int32_t n = cpu->gprs[rn];
472 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
473
474DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
475 int32_t n = cpu->gprs[rn];
476 cpu->gprs[rd] = n - cpu->shifterOperand;)
477
478DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
479 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
480
481DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
482 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
483
484// End ALU definitions
485
486// Begin multiply definitions
487
488DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
489DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
490
491DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
492 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
493 int32_t dm = cpu->gprs[rd];
494 int32_t dn = d;
495 cpu->gprs[rd] = dm + dn;
496 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
497 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
498
499DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
500 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
501 cpu->gprs[rd] = d;
502 cpu->gprs[rdHi] = d >> 32;,
503 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
504
505DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
506 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
507 int32_t dm = cpu->gprs[rd];
508 int32_t dn = d;
509 cpu->gprs[rd] = dm + dn;
510 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
511 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
512
513DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
514 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
515 cpu->gprs[rd] = d;
516 cpu->gprs[rdHi] = d >> 32;,
517 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
518
519// End multiply definitions
520
521// Begin load/store definitions
522
523DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
524DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
525DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
526DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
527DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
528DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
529DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
530DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
531
532DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
533 enum PrivilegeMode priv = cpu->privilegeMode;
534 ARMSetPrivilegeMode(cpu, MODE_USER);
535 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
536 ARMSetPrivilegeMode(cpu, priv);
537 cpu->gprs[rd] = r;
538 ARM_LOAD_POST_BODY;)
539
540DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
541 enum PrivilegeMode priv = cpu->privilegeMode;
542 ARMSetPrivilegeMode(cpu, MODE_USER);
543 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
544 ARMSetPrivilegeMode(cpu, priv);
545 cpu->gprs[rd] = r;
546 ARM_LOAD_POST_BODY;)
547
548DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
549 enum PrivilegeMode priv = cpu->privilegeMode;
550 int32_t r = cpu->gprs[rd];
551 ARMSetPrivilegeMode(cpu, MODE_USER);
552 cpu->memory.store8(cpu, address, r, ¤tCycles);
553 ARMSetPrivilegeMode(cpu, priv);
554 ARM_STORE_POST_BODY;)
555
556DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
557 enum PrivilegeMode priv = cpu->privilegeMode;
558 int32_t r = cpu->gprs[rd];
559 ARMSetPrivilegeMode(cpu, MODE_USER);
560 cpu->memory.store32(cpu, address, r, ¤tCycles);
561 ARMSetPrivilegeMode(cpu, priv);
562 ARM_STORE_POST_BODY;)
563
564DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
565 load,
566 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
567 if (rs & 0x8000) {
568 ARM_WRITE_PC;
569 })
570
571DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
572 store,
573 ARM_STORE_POST_BODY;)
574
575DEFINE_INSTRUCTION_ARM(SWP,
576 int rm = opcode & 0xF;
577 int rd = (opcode >> 12) & 0xF;
578 int rn = (opcode >> 16) & 0xF;
579 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
580 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
581 cpu->gprs[rd] = d;)
582
583DEFINE_INSTRUCTION_ARM(SWPB,
584 int rm = opcode & 0xF;
585 int rd = (opcode >> 12) & 0xF;
586 int rn = (opcode >> 16) & 0xF;
587 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
588 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
589 cpu->gprs[rd] = d;)
590
591// End load/store definitions
592
593// Begin branch definitions
594
595DEFINE_INSTRUCTION_ARM(B,
596 int32_t offset = opcode << 8;
597 offset >>= 6;
598 cpu->gprs[ARM_PC] += offset;
599 ARM_WRITE_PC;)
600
601DEFINE_INSTRUCTION_ARM(BL,
602 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
603 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
604 cpu->gprs[ARM_PC] += immediate >> 6;
605 ARM_WRITE_PC;)
606
607DEFINE_INSTRUCTION_ARM(BX,
608 int rm = opcode & 0x0000000F;
609 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
610 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
611 if (cpu->executionMode == MODE_THUMB) {
612 THUMB_WRITE_PC;
613 } else {
614 ARM_WRITE_PC;
615 })
616
617// End branch definitions
618
619// Begin coprocessor definitions
620
621DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
622DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
623DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
624DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
625DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
626
627// Begin miscellaneous definitions
628
629DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
630DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
631
632DEFINE_INSTRUCTION_ARM(MSR,
633 int c = opcode & 0x00010000;
634 int f = opcode & 0x00080000;
635 int32_t operand = cpu->gprs[opcode & 0x0000000F];
636 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
637 if (mask & PSR_USER_MASK) {
638 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
639 }
640 if (mask & PSR_STATE_MASK) {
641 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
642 }
643 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
644 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
645 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
646 }
647 _ARMReadCPSR(cpu);
648 if (cpu->executionMode == MODE_THUMB) {
649 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
650 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
651 } else {
652 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
653 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
654 })
655
656DEFINE_INSTRUCTION_ARM(MSRR,
657 int c = opcode & 0x00010000;
658 int f = opcode & 0x00080000;
659 int32_t operand = cpu->gprs[opcode & 0x0000000F];
660 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
661 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
662 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
663
664DEFINE_INSTRUCTION_ARM(MRS, \
665 int rd = (opcode >> 12) & 0xF; \
666 cpu->gprs[rd] = cpu->cpsr.packed;)
667
668DEFINE_INSTRUCTION_ARM(MRSR, \
669 int rd = (opcode >> 12) & 0xF; \
670 cpu->gprs[rd] = cpu->spsr.packed;)
671
672DEFINE_INSTRUCTION_ARM(MSRI,
673 int c = opcode & 0x00010000;
674 int f = opcode & 0x00080000;
675 int rotate = (opcode & 0x00000F00) >> 7;
676 int32_t operand = ROR(opcode & 0x000000FF, rotate);
677 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
678 if (mask & PSR_USER_MASK) {
679 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
680 }
681 if (mask & PSR_STATE_MASK) {
682 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
683 }
684 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
685 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
686 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
687 }
688 _ARMReadCPSR(cpu);
689 if (cpu->executionMode == MODE_THUMB) {
690 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
691 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
692 } else {
693 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
694 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
695 })
696
697DEFINE_INSTRUCTION_ARM(MSRRI,
698 int c = opcode & 0x00010000;
699 int f = opcode & 0x00080000;
700 int rotate = (opcode & 0x00000F00) >> 7;
701 int32_t operand = ROR(opcode & 0x000000FF, rotate);
702 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
703 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
704 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
705
706DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
707
708const ARMInstruction _armTable[0x1000] = {
709 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
710};