src/gb/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GB_SERIALIZE_H
7#define GB_SERIALIZE_H
8
9#include "util/common.h"
10
11CXX_GUARD_START
12
13#include "core/core.h"
14#include "gb/gb.h"
15
16extern const uint32_t GB_SAVESTATE_MAGIC;
17extern const uint32_t GB_SAVESTATE_VERSION;
18
19mLOG_DECLARE_CATEGORY(GB_STATE);
20
21/* Savestate format:
22 * 0x00000 - 0x00003: Version Magic (0x01000001)
23 * 0x00004 - 0x00007: ROM CRC32
24 * 0x00008: Game Boy model
25 * 0x00009 - 0x0000B: Reserved (leave zero)
26 * 0x0000C - 0x0000F: Master cycles
27 * 0x00010 - 0x0001F: Game title/code (e.g. PM_CRYSTALBYTE)
28 * 0x00020 - 0x00047: CPU state:
29 * | 0x00020: A register
30 * | 0x00021: F register
31 * | 0x00022: B register
32 * | 0x00023: C register
33 * | 0x00024: D register
34 * | 0x00025: E register
35 * | 0x00026: H register
36 * | 0x00027: L register
37 * | 0x00028 - 0x00029: SP register
38 * | 0x0002A - 0x0002B: PC register
39 * | 0x0002C - 0x0002F: Cycles since last event
40 * | 0x00030 - 0x00033: Cycles until next event
41 * | 0x00034 - 0x00035: Reserved (current instruction)
42 * | 0x00036 - 0x00037: Index address
43 * | 0x00038: Bus value
44 * | 0x00039: Execution state
45 * | 0x0003A - 0x0003B: IRQ vector
46 * | 0x0003C - 0x0003F: EI pending cycles
47 * | 0x00040 - 0x00043: Reserved (DI pending cycles)
48 * | 0x00044 - 0x00047: Flags
49 * | bit 0: Is condition met?
50 * | bit 1: Is condition IRQ pending?
51 * | bit 2: Double speed
52 * | bit 3: Is EI pending?
53 * | bits 4 - 31: Reserved
54 * 0x00048 - 0x0005B: Audio channel 1/framer state
55 * | 0x00048 - 0x0004B: Envelepe timing
56 * | bits 0 - 6: Remaining length
57 * | bits 7 - 9: Next step
58 * | bits 10 - 20: Shadow frequency register
59 * | bits 21 - 31: Reserved
60 * | 0x0004C - 0x0004F: Next frame
61 * | 0x00050 - 0x00053: Next channel 3 fade
62 * | 0x00054 - 0x00057: Reserved
63 * | 0x00058 - 0x0005B: Next event
64 * 0x0005C - 0x0006B: Audio channel 2 state
65 * | 0x0005C - 0x0005F: Envelepe timing
66 * | bits 0 - 2: Remaining length
67 * | bits 3 - 5: Next step
68 * | bits 6 - 31: Reserved
69 * | 0x00060 - 0x00067: Reserved
70 * | 0x00068 - 0x0006B: Next event
71 * 0x0006C - 0x00093: Audio channel 3 state
72 * | 0x0006C - 0x0008B: Wave banks
73 * | 0x0008C - 0x0008D: Remaining length
74 * | 0x0008E - 0x0008F: Reserved
75 * | 0x00090 - 0x00093: Next event
76 * 0x00094 - 0x000A3: Audio channel 4 state
77 * | 0x00094 - 0x00097: Linear feedback shift register state
78 * | 0x00098 - 0x0009B: Envelepe timing
79 * | bits 0 - 2: Remaining length
80 * | bits 3 - 5: Next step
81 * | bits 6 - 31: Reserved
82 * | 0x00098 - 0x0009F: Reserved
83 * | 0x000A0 - 0x000A3: Next event
84 * 0x000A4 - 0x000B7: Audio miscellaneous state
85 * | TODO: Fix this, they're in big-endian order, but field is little-endian
86 * | 0x000A4: Channel 1 envelope state
87 * | bits 0 - 3: Current volume
88 * | bits 4 - 5: Is dead?
89 * | bit 6: Is high?
90 * | 0x000A5: Channel 2 envelope state
91 * | bits 0 - 3: Current volume
92 * | bits 4 - 5: Is dead?
93 * | bit 6: Is high?
94* | bits 7: Reserved
95 * | 0x000A6: Channel 4 envelope state
96 * | bits 0 - 3: Current volume
97 * | bits 4 - 5: Is dead?
98 * | bit 6: Is high?
99* | bits 7: Reserved
100 * | 0x000A7: Miscellaneous audio flags
101 * | bits 0 - 3: Current frame
102 * | bit 4: Is channel 1 sweep enabled?
103 * | bit 5: Has channel 1 sweep occurred?
104 * | bit 6: Is channel 3's memory readable?
105 * | bit 7: Reserved
106 * | 0x000A8 - 0x000AF: Rserved
107 * | 0x000B0 - 0x000B3: Next sample
108 * 0x000B4 - 0x000153: Video state
109 * | 0x000B4 - 0x000B5: Current x
110 * | 0x000B6 - 0x000B7: Current y (ly)
111 * | 0x000B8 - 0x000BB: Next frame
112 * | 0x000BC - 0x000BF: Reserved
113 * | 0x000C0 - 0x000C3: Next mode
114 * | 0x000C4 - 0x000C7: Dot cycle counter
115 * | 0x000C8 - 0x000CB: Frame counter
116 * | 0x000CC: Current VRAM bank
117 * | 0x000CD: Palette flags
118 * | bit 0: BCP increment
119 * | bit 1: OCP increment
120 * | bits 2 - 3: Mode
121 * | bits 4 - 7: Reserved
122 * | 0x000CE - 0x000CF: Reserved
123 * | 0x000D0 - 0x000D1: BCP index
124 * | 0x000D1 - 0x000D3: OCP index
125 * | 0x000D4 - 0x00153: Palette entries
126 * 0x00154 - 0x000167: Timer state
127 * | 0x00154 - 0x00157: Next event
128 * | 0x00158 - 0x0015B: Next IRQ
129 * | 0x0015C - 0x0015F: Next DIV
130 * | 0x00160 - 0x00163: Inernal DIV
131 * | 0x00164: TIMA period
132 * | 0x00165: Flags
133 * | bit 0: Is IRQ pending?
134 * | 0x00166 - 0x00167: Reserved
135 * 0x000168 - 0x000197: Memory state
136 * | 0x00168 - 0x00169: Current ROM bank
137 * | 0x0016A: Current WRAM bank
138 * | 0x0016B: Current SRAM bank
139 * | 0x0016C - 0x0016F: Next DMA
140 * | 0x00170 - 0x00171: Next DMA source
141 * | 0x00172 - 0x00173: Next DMA destination
142 * | 0x00174 - 0x00177: Next HDMA
143 * | 0x00178 - 0x00179: Next HDMA source
144 * | 0x0017A - 0x0017B: Next HDMA destination
145 * | 0x0017C - 0x0017D: HDMA remaining
146 * | 0x0017E: DMA remaining
147 * | 0x0017F - 0x00183: RTC registers
148 * | 0x00184 - 0x00193: MBC state (TODO)
149 * | 0x00194 - 0x00195: Flags
150 * | bit 0: SRAM accessable
151 * | bit 1: RTC accessible
152 * | bit 2: RTC latched
153 * | bit 3: IME
154 * | bit 4: Is HDMA active?
155 * | bits 5 - 7: Active RTC register
156 * | 0x00196 - 0x00197: Reserved (leave zero)
157 * 0x00198 - 0x0019F: Savestate creation time (usec since 1970)
158 * 0x001A0 - 0x0025F: Reserved (leave zero)
159 * 0x00260 - 0x002FF: OAM
160 * 0x00300 - 0x0037F: I/O memory
161 * 0x00380 - 0x003FE: HRAM
162 * 0x003FF: Interrupts enabled
163 * 0x00400 - 0x043FF: VRAM
164 * 0x04400 - 0x0C3FF: WRAM
165 * Total size: 0xC400 (50,176) bytes
166*/
167
168DECL_BITFIELD(GBSerializedAudioFlags, uint32_t);
169DECL_BITS(GBSerializedAudioFlags, Ch1Volume, 0, 4);
170DECL_BITS(GBSerializedAudioFlags, Ch1Dead, 4, 2);
171DECL_BIT(GBSerializedAudioFlags, Ch1Hi, 6);
172DECL_BITS(GBSerializedAudioFlags, Ch2Volume, 8, 4);
173DECL_BITS(GBSerializedAudioFlags, Ch2Dead, 12, 2);
174DECL_BIT(GBSerializedAudioFlags, Ch2Hi, 14);
175DECL_BITS(GBSerializedAudioFlags, Ch4Volume, 16, 4);
176DECL_BITS(GBSerializedAudioFlags, Ch4Dead, 20, 2);
177DECL_BITS(GBSerializedAudioFlags, Frame, 22, 3);
178DECL_BIT(GBSerializedAudioFlags, Ch1SweepEnabled, 25);
179DECL_BIT(GBSerializedAudioFlags, Ch1SweepOccurred, 26);
180DECL_BIT(GBSerializedAudioFlags, Ch3Readable, 27);
181
182DECL_BITFIELD(GBSerializedAudioEnvelope, uint32_t);
183DECL_BITS(GBSerializedAudioEnvelope, Length, 0, 7);
184DECL_BITS(GBSerializedAudioEnvelope, NextStep, 7, 3);
185DECL_BITS(GBSerializedAudioEnvelope, Frequency, 10, 11);
186
187struct GBSerializedPSGState {
188 struct {
189 GBSerializedAudioEnvelope envelope;
190 int32_t nextFrame;
191 int32_t nextCh3Fade;
192 int32_t reserved;
193 uint32_t nextEvent;
194 } ch1;
195 struct {
196 GBSerializedAudioEnvelope envelope;
197 int32_t reserved[2];
198 int32_t nextEvent;
199 } ch2;
200 struct {
201 uint32_t wavebanks[8];
202 int16_t length;
203 int16_t reserved;
204 uint32_t nextEvent;
205 } ch3;
206 struct {
207 int32_t lfsr;
208 GBSerializedAudioEnvelope envelope;
209 int32_t reserved;
210 uint32_t nextEvent;
211 } ch4;
212};
213
214DECL_BITFIELD(GBSerializedCpuFlags, uint32_t);
215DECL_BIT(GBSerializedCpuFlags, Condition, 0);
216DECL_BIT(GBSerializedCpuFlags, IrqPending, 1);
217DECL_BIT(GBSerializedCpuFlags, DoubleSpeed, 2);
218DECL_BIT(GBSerializedCpuFlags, EiPending, 1);
219
220DECL_BITFIELD(GBSerializedTimerFlags, uint8_t);
221DECL_BIT(GBSerializedTimerFlags, IrqPending, 0);
222
223DECL_BITFIELD(GBSerializedVideoFlags, uint8_t);
224DECL_BIT(GBSerializedVideoFlags, BcpIncrement, 0);
225DECL_BIT(GBSerializedVideoFlags, OcpIncrement, 1);
226DECL_BITS(GBSerializedVideoFlags, Mode, 2, 2);
227DECL_BIT(GBSerializedVideoFlags, NotModeEventScheduled, 4);
228DECL_BIT(GBSerializedVideoFlags, NotFrameEventScheduled, 5);
229
230DECL_BITFIELD(GBSerializedMBC7Flags, uint8_t);
231DECL_BITS(GBSerializedMBC7Flags, Command, 0, 2);
232DECL_BIT(GBSerializedMBC7Flags, Writable, 2);
233
234DECL_BITFIELD(GBSerializedMemoryFlags, uint16_t);
235DECL_BIT(GBSerializedMemoryFlags, SramAccess, 0);
236DECL_BIT(GBSerializedMemoryFlags, RtcAccess, 1);
237DECL_BIT(GBSerializedMemoryFlags, RtcLatched, 2);
238DECL_BIT(GBSerializedMemoryFlags, Ime, 3);
239DECL_BIT(GBSerializedMemoryFlags, IsHdma, 4);
240DECL_BITS(GBSerializedMemoryFlags, ActiveRtcReg, 5, 3);
241
242#pragma pack(push, 1)
243struct GBSerializedState {
244 uint32_t versionMagic;
245 uint32_t romCrc32;
246 uint8_t model;
247 uint8_t reservedHeader[3];
248 uint32_t masterCycles;
249
250 char title[16];
251
252 struct {
253 uint8_t a;
254 uint8_t f;
255 uint8_t b;
256 uint8_t c;
257 uint8_t d;
258 uint8_t e;
259 uint8_t h;
260 uint8_t l;
261 uint16_t sp;
262 uint16_t pc;
263
264 int32_t cycles;
265 int32_t nextEvent;
266
267 uint16_t reservedInstruction;
268 uint16_t index;
269 uint8_t bus;
270 uint8_t executionState;
271
272 uint16_t irqVector;
273
274 uint32_t eiPending;
275 int32_t reservedDiPending;
276 GBSerializedCpuFlags flags;
277 } cpu;
278
279 struct {
280 struct GBSerializedPSGState psg;
281 GBSerializedAudioFlags flags;
282 int32_t reserved[2];
283 uint32_t nextSample;
284 } audio;
285
286 struct {
287 int16_t x;
288 int16_t ly;
289 uint32_t nextFrame;
290 uint32_t reserved;
291 uint32_t nextMode;
292 int32_t dotCounter;
293 int32_t frameCounter;
294
295 uint8_t vramCurrentBank;
296 GBSerializedVideoFlags flags;
297 uint16_t reserved2;
298
299 uint16_t bcpIndex;
300 uint16_t ocpIndex;
301
302 uint16_t palette[64];
303 } video;
304
305 struct {
306 uint32_t nextEvent;
307 uint32_t nextIRQ;
308
309 uint32_t nextDiv;
310 uint32_t internalDiv;
311 uint8_t timaPeriod;
312 GBSerializedTimerFlags flags;
313 uint16_t reserved;
314 } timer;
315
316 struct {
317 uint16_t currentBank;
318 uint8_t wramCurrentBank;
319 uint8_t sramCurrentBank;
320
321 uint32_t dmaNext;
322 uint16_t dmaSource;
323 uint16_t dmaDest;
324
325 uint32_t hdmaNext;
326 uint16_t hdmaSource;
327 uint16_t hdmaDest;
328
329 uint16_t hdmaRemaining;
330 uint8_t dmaRemaining;
331 uint8_t rtcRegs[5];
332
333 union {
334 struct {
335 uint32_t mode;
336 } mbc1;
337 struct {
338 uint64_t lastLatch;
339 } rtc;
340 struct {
341 int8_t machineState;
342 GBMBC7Field field;
343 int8_t address;
344 uint8_t srBits;
345 uint32_t sr;
346 GBSerializedMBC7Flags flags;
347 } mbc7;
348 struct {
349 uint8_t reserved[16];
350 } padding;
351 };
352
353 GBSerializedMemoryFlags flags;
354 uint16_t reserved;
355 } memory;
356
357 uint64_t creationUsec;
358
359 uint32_t reserved[48];
360
361 uint8_t oam[GB_SIZE_OAM];
362
363 uint8_t io[GB_SIZE_IO];
364 uint8_t hram[GB_SIZE_HRAM];
365 uint8_t ie;
366
367 uint8_t vram[GB_SIZE_VRAM];
368 uint8_t wram[GB_SIZE_WORKING_RAM];
369};
370#pragma pack(pop)
371
372bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state);
373void GBSerialize(struct GB* gb, struct GBSerializedState* state);
374
375CXX_GUARD_END
376
377#endif