src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "emitter-arm.h"
5#include "isa-inlines.h"
6
7#define PSR_USER_MASK 0xF0000000
8#define PSR_PRIV_MASK 0x000000CF
9#define PSR_STATE_MASK 0x00000020
10
11// Addressing mode 1
12static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
13 int rm = opcode & 0x0000000F;
14 int immediate = (opcode & 0x00000F80) >> 7;
15 if (!immediate) {
16 cpu->shifterOperand = cpu->gprs[rm];
17 cpu->shifterCarryOut = cpu->cpsr.c;
18 } else {
19 cpu->shifterOperand = cpu->gprs[rm] << immediate;
20 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
21 }
22}
23
24static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
25 int rm = opcode & 0x0000000F;
26 int rs = (opcode >> 8) & 0x0000000F;
27 ++cpu->cycles;
28 int shift = cpu->gprs[rs];
29 if (rs == ARM_PC) {
30 shift += 4;
31 }
32 shift &= 0xFF;
33 int32_t shiftVal = cpu->gprs[rm];
34 if (rm == ARM_PC) {
35 shiftVal += 4;
36 }
37 if (!shift) {
38 cpu->shifterOperand = shiftVal;
39 cpu->shifterCarryOut = cpu->cpsr.c;
40 } else if (shift < 32) {
41 cpu->shifterOperand = shiftVal << shift;
42 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
43 } else if (shift == 32) {
44 cpu->shifterOperand = 0;
45 cpu->shifterCarryOut = shiftVal & 1;
46 } else {
47 cpu->shifterOperand = 0;
48 cpu->shifterCarryOut = 0;
49 }
50}
51
52static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
53 int rm = opcode & 0x0000000F;
54 int immediate = (opcode & 0x00000F80) >> 7;
55 if (immediate) {
56 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
57 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
58 } else {
59 cpu->shifterOperand = 0;
60 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
61 }
62}
63
64static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
65 int rm = opcode & 0x0000000F;
66 int rs = (opcode >> 8) & 0x0000000F;
67 ++cpu->cycles;
68 int shift = cpu->gprs[rs];
69 if (rs == ARM_PC) {
70 shift += 4;
71 }
72 shift &= 0xFF;
73 uint32_t shiftVal = cpu->gprs[rm];
74 if (rm == ARM_PC) {
75 shiftVal += 4;
76 }
77 if (!shift) {
78 cpu->shifterOperand = shiftVal;
79 cpu->shifterCarryOut = cpu->cpsr.c;
80 } else if (shift < 32) {
81 cpu->shifterOperand = shiftVal >> shift;
82 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
83 } else if (shift == 32) {
84 cpu->shifterOperand = 0;
85 cpu->shifterCarryOut = shiftVal >> 31;
86 } else {
87 cpu->shifterOperand = 0;
88 cpu->shifterCarryOut = 0;
89 }
90}
91
92static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
93 int rm = opcode & 0x0000000F;
94 int immediate = (opcode & 0x00000F80) >> 7;
95 if (immediate) {
96 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
97 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
98 } else {
99 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
100 cpu->shifterOperand = cpu->shifterCarryOut;
101 }
102}
103
104static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
105 int rm = opcode & 0x0000000F;
106 int rs = (opcode >> 8) & 0x0000000F;
107 ++cpu->cycles;
108 int shift = cpu->gprs[rs];
109 if (rs == ARM_PC) {
110 shift += 4;
111 }
112 shift &= 0xFF;
113 int shiftVal = cpu->gprs[rm];
114 if (rm == ARM_PC) {
115 shiftVal += 4;
116 }
117 if (!shift) {
118 cpu->shifterOperand = shiftVal;
119 cpu->shifterCarryOut = cpu->cpsr.c;
120 } else if (shift < 32) {
121 cpu->shifterOperand = shiftVal >> shift;
122 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
123 } else if (cpu->gprs[rm] >> 31) {
124 cpu->shifterOperand = 0xFFFFFFFF;
125 cpu->shifterCarryOut = 1;
126 } else {
127 cpu->shifterOperand = 0;
128 cpu->shifterCarryOut = 0;
129 }
130}
131
132static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
133 int rm = opcode & 0x0000000F;
134 int immediate = (opcode & 0x00000F80) >> 7;
135 if (immediate) {
136 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
137 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
138 } else {
139 // RRX
140 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
141 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
142 }
143}
144
145static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
146 int rm = opcode & 0x0000000F;
147 int rs = (opcode >> 8) & 0x0000000F;
148 ++cpu->cycles;
149 int shift = cpu->gprs[rs];
150 if (rs == ARM_PC) {
151 shift += 4;
152 }
153 shift &= 0xFF;
154 int shiftVal = cpu->gprs[rm];
155 if (rm == ARM_PC) {
156 shiftVal += 4;
157 }
158 int rotate = shift & 0x1F;
159 if (!shift) {
160 cpu->shifterOperand = shiftVal;
161 cpu->shifterCarryOut = cpu->cpsr.c;
162 } else if (rotate) {
163 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
164 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
165 } else {
166 cpu->shifterOperand = shiftVal;
167 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
168 }
169}
170
171static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
172 int rotate = (opcode & 0x00000F00) >> 7;
173 int immediate = opcode & 0x000000FF;
174 if (!rotate) {
175 cpu->shifterOperand = immediate;
176 cpu->shifterCarryOut = cpu->cpsr.c;
177 } else {
178 cpu->shifterOperand = ARM_ROR(immediate, rotate);
179 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
180 }
181}
182
183// Instruction definitions
184// Beware pre-processor antics
185
186#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 cpu->cpsr.n = ARM_SIGN(D); \
194 cpu->cpsr.z = !(D); \
195 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
196 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
197 }
198
199#define ARM_SUBTRACTION_S(M, N, D) \
200 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
201 cpu->cpsr = cpu->spsr; \
202 _ARMReadCPSR(cpu); \
203 } else { \
204 cpu->cpsr.n = ARM_SIGN(D); \
205 cpu->cpsr.z = !(D); \
206 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
207 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
208 }
209
210#define ARM_NEUTRAL_S(M, N, D) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 cpu->cpsr.n = ARM_SIGN(D); \
216 cpu->cpsr.z = !(D); \
217 cpu->cpsr.c = cpu->shifterCarryOut; \
218 }
219
220#define ARM_NEUTRAL_HI_S(DLO, DHI) \
221 cpu->cpsr.n = ARM_SIGN(DHI); \
222 cpu->cpsr.z = !((DHI) | (DLO));
223
224#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
225#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
226#define ADDR_MODE_2_ADDRESS (address)
227#define ADDR_MODE_2_RN (cpu->gprs[rn])
228#define ADDR_MODE_2_RM (cpu->gprs[rm])
229#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
230#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
231#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
232#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
233#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
234#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
235#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
236
237#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
238#define ADDR_MODE_3_RN ADDR_MODE_2_RN
239#define ADDR_MODE_3_RM ADDR_MODE_2_RM
240#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
241#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
242#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
243
244#define ADDR_MODE_4_WRITEBACK cpu->gprs[rn] = address
245
246#define ARM_LOAD_POST_BODY \
247 ++currentCycles; \
248 if (rd == ARM_PC) { \
249 ARM_WRITE_PC; \
250 }
251
252#define ARM_STORE_POST_BODY \
253 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
254
255#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
256 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
257 int currentCycles = ARM_PREFETCH_CYCLES; \
258 BODY; \
259 cpu->cycles += currentCycles; \
260 }
261
262#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
263 DEFINE_INSTRUCTION_ARM(NAME, \
264 int rd = (opcode >> 12) & 0xF; \
265 int rn = (opcode >> 16) & 0xF; \
266 UNUSED(rn); \
267 SHIFTER(cpu, opcode); \
268 BODY; \
269 S_BODY; \
270 if (rd == ARM_PC) { \
271 if (cpu->executionMode == MODE_ARM) { \
272 ARM_WRITE_PC; \
273 } else { \
274 THUMB_WRITE_PC; \
275 } \
276 })
277
278#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
279 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
280 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
281 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
282 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
283 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
284 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
285 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
286 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
287 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
288 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
289 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
290 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
291 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
292 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
295 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
296 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
297
298#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
308
309#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
310 DEFINE_INSTRUCTION_ARM(NAME, \
311 int rd = (opcode >> 12) & 0xF; \
312 int rdHi = (opcode >> 16) & 0xF; \
313 int rs = (opcode >> 8) & 0xF; \
314 int rm = opcode & 0xF; \
315 UNUSED(rdHi); \
316 ARM_WAIT_MUL(cpu->gprs[rs]); \
317 BODY; \
318 S_BODY; \
319 if (rd == ARM_PC) { \
320 ARM_WRITE_PC; \
321 })
322
323#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
324 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
325 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
326
327#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
328 DEFINE_INSTRUCTION_ARM(NAME, \
329 uint32_t address; \
330 int rn = (opcode >> 16) & 0xF; \
331 int rd = (opcode >> 12) & 0xF; \
332 int rm = opcode & 0xF; \
333 UNUSED(rm); \
334 address = ADDRESS; \
335 WRITEBACK; \
336 BODY;)
337
338#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
339 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
340 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
341 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
342 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
343 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
344 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
345
346#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
347 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
350 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
351 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
354 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
355 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
356 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
357
358#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
370 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
371
372#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
375
376#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
377 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
378 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
379 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
380 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
383
384#define ARM_MS_PRE \
385 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
386 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
387
388#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
389
390#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
391 DEFINE_INSTRUCTION_ARM(NAME, \
392 int rn = (opcode >> 16) & 0xF; \
393 int rs = opcode & 0x0000FFFF; \
394 uint32_t address = cpu->gprs[rn]; \
395 S_PRE; \
396 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
397 S_POST; \
398 POST_BODY; \
399 WRITEBACK;)
400
401
402#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
403 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
404 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK, , , DA, POST_BODY) \
405 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
406 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK, , , DB, POST_BODY) \
407 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
408 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK, , , IA, POST_BODY) \
409 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
410 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK, , , IB, POST_BODY) \
411 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
412 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
413 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
414 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
415 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
416 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
417 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
418 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
419
420// Begin ALU definitions
421
422DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
423 int32_t n = cpu->gprs[rn];
424 cpu->gprs[rd] = n + cpu->shifterOperand;)
425
426DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
427 int32_t n = cpu->gprs[rn];
428 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
429
430DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
431 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
432
433DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
434 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
435
436DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
437 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
438
439DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
440 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
441
442DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
443 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
444
445DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
446 cpu->gprs[rd] = cpu->shifterOperand;)
447
448DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
449 cpu->gprs[rd] = ~cpu->shifterOperand;)
450
451DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
452 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
453
454DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
455 int32_t n = cpu->gprs[rn];
456 cpu->gprs[rd] = cpu->shifterOperand - n;)
457
458DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
459 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
460 cpu->gprs[rd] = cpu->shifterOperand - n;)
461
462DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
463 int32_t n = cpu->gprs[rn];
464 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
465 cpu->gprs[rd] = n - shifterOperand;)
466
467DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
468 int32_t n = cpu->gprs[rn];
469 cpu->gprs[rd] = n - cpu->shifterOperand;)
470
471DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
472 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
473
474DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
475 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
476
477// End ALU definitions
478
479// Begin multiply definitions
480
481DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
482DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
483
484DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
485 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
486 int32_t dm = cpu->gprs[rd];
487 int32_t dn = d;
488 cpu->gprs[rd] = dm + dn;
489 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
490 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
491
492DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
493 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
494 cpu->gprs[rd] = d;
495 cpu->gprs[rdHi] = d >> 32;,
496 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
497
498DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
499 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
500 int32_t dm = cpu->gprs[rd];
501 int32_t dn = d;
502 cpu->gprs[rd] = dm + dn;
503 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
504 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
505
506DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
507 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
508 cpu->gprs[rd] = d;
509 cpu->gprs[rdHi] = d >> 32;,
510 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
511
512// End multiply definitions
513
514// Begin load/store definitions
515
516DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
517DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.loadU8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
518DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.loadU16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
519DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
520DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
521DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
522DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
523DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
524
525DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
526 enum PrivilegeMode priv = cpu->privilegeMode;
527 ARMSetPrivilegeMode(cpu, MODE_USER);
528 cpu->gprs[rd] = cpu->memory.loadU8(cpu, address, ¤tCycles);
529 ARMSetPrivilegeMode(cpu, priv);
530 ARM_LOAD_POST_BODY;)
531
532DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
533 enum PrivilegeMode priv = cpu->privilegeMode;
534 ARMSetPrivilegeMode(cpu, MODE_USER);
535 cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles);
536 ARMSetPrivilegeMode(cpu, priv);
537 ARM_LOAD_POST_BODY;)
538
539DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
540 enum PrivilegeMode priv = cpu->privilegeMode;
541 ARMSetPrivilegeMode(cpu, MODE_USER);
542 cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles);
543 ARMSetPrivilegeMode(cpu, priv);
544 ARM_STORE_POST_BODY;)
545
546DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
547 enum PrivilegeMode priv = cpu->privilegeMode;
548 ARMSetPrivilegeMode(cpu, MODE_USER);
549 cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles);
550 ARMSetPrivilegeMode(cpu, priv);
551 ARM_STORE_POST_BODY;)
552
553DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
554 load,
555 ++currentCycles;
556 if (rs & 0x8000) {
557 ARM_WRITE_PC;
558 })
559
560DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
561 store,
562 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
563
564DEFINE_INSTRUCTION_ARM(SWP,
565 int rm = opcode & 0xF;
566 int rd = (opcode >> 12) & 0xF;
567 int rn = (opcode >> 16) & 0xF;
568 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
569 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
570 cpu->gprs[rd] = d;)
571
572DEFINE_INSTRUCTION_ARM(SWPB,
573 int rm = opcode & 0xF;
574 int rd = (opcode >> 12) & 0xF;
575 int rn = (opcode >> 16) & 0xF;
576 int32_t d = cpu->memory.loadU8(cpu, cpu->gprs[rn], ¤tCycles);
577 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
578 cpu->gprs[rd] = d;)
579
580// End load/store definitions
581
582// Begin branch definitions
583
584DEFINE_INSTRUCTION_ARM(B,
585 int32_t offset = opcode << 8;
586 offset >>= 6;
587 cpu->gprs[ARM_PC] += offset;
588 ARM_WRITE_PC;)
589
590DEFINE_INSTRUCTION_ARM(BL,
591 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
592 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
593 cpu->gprs[ARM_PC] += immediate >> 6;
594 ARM_WRITE_PC;)
595
596DEFINE_INSTRUCTION_ARM(BX,
597 int rm = opcode & 0x0000000F;
598 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
599 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
600 if (cpu->executionMode == MODE_THUMB) {
601 THUMB_WRITE_PC;
602 } else {
603 ARM_WRITE_PC;
604 })
605
606// End branch definitions
607
608// Begin coprocessor definitions
609
610DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
611DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
612DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
613DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
614DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
615
616// Begin miscellaneous definitions
617
618DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
619DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
620
621DEFINE_INSTRUCTION_ARM(MSR,
622 int c = opcode & 0x00010000;
623 int f = opcode & 0x00080000;
624 int32_t operand = cpu->gprs[opcode & 0x0000000F];
625 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
626 if (mask & PSR_USER_MASK) {
627 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
628 }
629 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
630 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
631 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
632 }
633 _ARMReadCPSR(cpu);)
634
635DEFINE_INSTRUCTION_ARM(MSRR,
636 int c = opcode & 0x00010000;
637 int f = opcode & 0x00080000;
638 int32_t operand = cpu->gprs[opcode & 0x0000000F];
639 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
640 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
641 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
642
643DEFINE_INSTRUCTION_ARM(MRS, \
644 int rd = (opcode >> 12) & 0xF; \
645 cpu->gprs[rd] = cpu->cpsr.packed;)
646
647DEFINE_INSTRUCTION_ARM(MRSR, \
648 int rd = (opcode >> 12) & 0xF; \
649 cpu->gprs[rd] = cpu->spsr.packed;)
650
651DEFINE_INSTRUCTION_ARM(MSRI,
652 int c = opcode & 0x00010000;
653 int f = opcode & 0x00080000;
654 int rotate = (opcode & 0x00000F00) >> 7;
655 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
656 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
657 if (mask & PSR_USER_MASK) {
658 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
659 }
660 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
661 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
662 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
663 }
664 _ARMReadCPSR(cpu);)
665
666DEFINE_INSTRUCTION_ARM(MSRRI,
667 int c = opcode & 0x00010000;
668 int f = opcode & 0x00080000;
669 int rotate = (opcode & 0x00000F00) >> 7;
670 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
671 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
672 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
673 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
674
675DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
676
677const ARMInstruction _armTable[0x1000] = {
678 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
679};