1; this file was created with wlalink by ville helin <vhelin@iki.fi>.
  2; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/ret_timing.gb".
  3
  4[labels]
  501:4bff print_load_font
  601:4c0c print_string
  701:4c16 print_a
  801:4c20 print_newline
  901:4c2b print_digit
 1001:4c38 print_regs
 1101:4c41 _print_sl_data0
 1201:4c47 _print_sl_out0
 1301:4c54 _print_sl_data1
 1401:4c5a _print_sl_out1
 1501:4c6c _print_sl_data2
 1601:4c72 _print_sl_out2
 1701:4c7f _print_sl_data3
 1801:4c85 _print_sl_out3
 1901:4c97 _print_sl_data4
 2001:4c9d _print_sl_out4
 2101:4caa _print_sl_data5
 2201:4cb0 _print_sl_out5
 2301:4cc2 _print_sl_data6
 2401:4cc8 _print_sl_out6
 2501:4cd5 _print_sl_data7
 2601:4cdb _print_sl_out7
 2701:4000 font
 2800:c000 regs_save
 2900:c000 regs_save.f
 3000:c001 regs_save.a
 3100:c002 regs_save.c
 3200:c003 regs_save.b
 3300:c004 regs_save.e
 3400:c005 regs_save.d
 3500:c006 regs_save.l
 3600:c007 regs_save.h
 3700:c008 regs_flags
 3800:c009 regs_assert
 3900:c009 regs_assert.f
 4000:c00a regs_assert.a
 4100:c00b regs_assert.c
 4200:c00c regs_assert.b
 4300:c00d regs_assert.e
 4400:c00e regs_assert.d
 4500:c00f regs_assert.l
 4600:c010 regs_assert.h
 4700:c011 memdump_len
 4800:c012 memdump_addr
 4901:47f0 memcpy
 5001:47f9 memset
 5101:4802 memcmp
 5201:4810 clear_vram
 5301:481a clear_oam
 5401:4824 disable_lcd_safe
 5501:482a _wait_ly_0
 5601:4830 _wait_ly_1
 5701:4839 reset_screen
 5801:484d process_results
 5901:4861 _wait_ly_2
 6001:4867 _wait_ly_3
 6101:487d _print_results_halt_0
 6201:4880 _process_results_cb
 6301:488b _print_sl_data8
 6401:4895 _print_sl_out8
 6501:48af _print_sl_data9
 6601:48ba _print_sl_out9
 6701:48d2 _print_sl_data10
 6801:48de _print_sl_out10
 6901:48df dump_mem
 7001:48fe _dump_mem_line
 7101:4928 _check_asserts
 7201:4936 _print_sl_data11
 7301:4939 _print_sl_out11
 7401:4945 _print_sl_data12
 7501:4947 _print_sl_out12
 7601:494f _print_sl_data13
 7701:4952 _print_sl_out13
 7801:495c __check_assert_fail0
 7901:4967 _print_sl_data14
 8001:496a _print_sl_out14
 8101:496d __check_assert_ok0
 8201:4975 _print_sl_data15
 8301:497a _print_sl_out15
 8401:497c __check_assert_skip0
 8501:4984 _print_sl_data16
 8601:498c _print_sl_out16
 8701:498c __check_assert_out0
 8801:4998 _print_sl_data17
 8901:499a _print_sl_out17
 9001:49a2 _print_sl_data18
 9101:49a5 _print_sl_out18
 9201:49af __check_assert_fail1
 9301:49ba _print_sl_data19
 9401:49bd _print_sl_out19
 9501:49c0 __check_assert_ok1
 9601:49c8 _print_sl_data20
 9701:49cd _print_sl_out20
 9801:49cf __check_assert_skip1
 9901:49d7 _print_sl_data21
10001:49df _print_sl_out21
10101:49df __check_assert_out1
10201:49ea _print_sl_data22
10301:49ed _print_sl_out22
10401:49f9 _print_sl_data23
10501:49fb _print_sl_out23
10601:4a03 _print_sl_data24
10701:4a06 _print_sl_out24
10801:4a10 __check_assert_fail2
10901:4a1b _print_sl_data25
11001:4a1e _print_sl_out25
11101:4a21 __check_assert_ok2
11201:4a29 _print_sl_data26
11301:4a2e _print_sl_out26
11401:4a30 __check_assert_skip2
11501:4a38 _print_sl_data27
11601:4a40 _print_sl_out27
11701:4a40 __check_assert_out2
11801:4a4c _print_sl_data28
11901:4a4e _print_sl_out28
12001:4a56 _print_sl_data29
12101:4a59 _print_sl_out29
12201:4a63 __check_assert_fail3
12301:4a6e _print_sl_data30
12401:4a71 _print_sl_out30
12501:4a74 __check_assert_ok3
12601:4a7c _print_sl_data31
12701:4a81 _print_sl_out31
12801:4a83 __check_assert_skip3
12901:4a8b _print_sl_data32
13001:4a93 _print_sl_out32
13101:4a93 __check_assert_out3
13201:4a9e _print_sl_data33
13301:4aa1 _print_sl_out33
13401:4aad _print_sl_data34
13501:4aaf _print_sl_out34
13601:4ab7 _print_sl_data35
13701:4aba _print_sl_out35
13801:4ac4 __check_assert_fail4
13901:4acf _print_sl_data36
14001:4ad2 _print_sl_out36
14101:4ad5 __check_assert_ok4
14201:4add _print_sl_data37
14301:4ae2 _print_sl_out37
14401:4ae4 __check_assert_skip4
14501:4aec _print_sl_data38
14601:4af4 _print_sl_out38
14701:4af4 __check_assert_out4
14801:4b00 _print_sl_data39
14901:4b02 _print_sl_out39
15001:4b0a _print_sl_data40
15101:4b0d _print_sl_out40
15201:4b17 __check_assert_fail5
15301:4b22 _print_sl_data41
15401:4b25 _print_sl_out41
15501:4b28 __check_assert_ok5
15601:4b30 _print_sl_data42
15701:4b35 _print_sl_out42
15801:4b37 __check_assert_skip5
15901:4b3f _print_sl_data43
16001:4b47 _print_sl_out43
16101:4b47 __check_assert_out5
16201:4b52 _print_sl_data44
16301:4b55 _print_sl_out44
16401:4b61 _print_sl_data45
16501:4b63 _print_sl_out45
16601:4b6b _print_sl_data46
16701:4b6e _print_sl_out46
16801:4b78 __check_assert_fail6
16901:4b83 _print_sl_data47
17001:4b86 _print_sl_out47
17101:4b89 __check_assert_ok6
17201:4b91 _print_sl_data48
17301:4b96 _print_sl_out48
17401:4b98 __check_assert_skip6
17501:4ba0 _print_sl_data49
17601:4ba8 _print_sl_out49
17701:4ba8 __check_assert_out6
17801:4bb4 _print_sl_data50
17901:4bb6 _print_sl_out50
18001:4bbe _print_sl_data51
18101:4bc1 _print_sl_out51
18201:4bcb __check_assert_fail7
18301:4bd6 _print_sl_data52
18401:4bd9 _print_sl_out52
18501:4bdc __check_assert_ok7
18601:4be4 _print_sl_data53
18701:4be9 _print_sl_out53
18801:4beb __check_assert_skip7
18901:4bf3 _print_sl_data54
19001:4bfb _print_sl_out54
19101:4bfb __check_assert_out7
19200:015c test_round1
19300:015c _wait_ly_4
19400:0162 _wait_ly_5
19500:017c _wait_ly_6
19600:0182 _wait_ly_7
19700:0193 finish_round1
19800:01aa _wait_ly_8
19900:01b0 _wait_ly_9
20000:01c6 _print_results_halt_1
20100:01c9 _test_failure_cb_0
20200:01d1 _print_sl_data55
20300:01df _print_sl_out55
20400:01e2 test_round2
20500:01e2 _wait_ly_10
20600:01e8 _wait_ly_11
20700:01fc _wait_ly_12
20800:0202 _wait_ly_13
20900:0214 finish_round2
21000:022b _wait_ly_14
21100:0231 _wait_ly_15
21200:0247 _print_results_halt_2
21300:024a _test_failure_cb_1
21400:0252 _print_sl_data56
21500:0260 _print_sl_out56
21600:0263 test_success
21700:0277 _wait_ly_16
21800:027d _wait_ly_17
21900:0293 _print_results_halt_3
22000:0296 _test_ok_cb_0
22100:029e _print_sl_data57
22200:02a6 _print_sl_out57
22300:02a9 hiram_cb