src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
33
34static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
35static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
36static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
37static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
38
39static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
40
41static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
42static void _GBPocketCamCapture(struct GBMemory*);
43
44void GBMBCSwitchBank(struct GB* gb, int bank) {
45 size_t bankStart = bank * GB_SIZE_CART_BANK0;
46 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
47 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
48 bankStart &= (gb->memory.romSize - 1);
49 bank = bankStart / GB_SIZE_CART_BANK0;
50 }
51 gb->memory.romBank = &gb->memory.rom[bankStart];
52 gb->memory.currentBank = bank;
53 if (gb->cpu->pc < GB_BASE_VRAM) {
54 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
55 }
56}
57
58void GBMBCSwitchBank0(struct GB* gb, int bank) {
59 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
60 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
61 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
62 bankStart &= (gb->memory.romSize - 1);
63 }
64 gb->memory.romBase = &gb->memory.rom[bankStart];
65 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
66 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
67 }
68}
69
70void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
71 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
72 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
73 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
74 bankStart &= (gb->memory.romSize - 1);
75 bank = bankStart / GB_SIZE_CART_HALFBANK;
76 if (!bank) {
77 ++bank;
78 }
79 }
80 if (!half) {
81 gb->memory.romBank = &gb->memory.rom[bankStart];
82 gb->memory.currentBank = bank;
83 } else {
84 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
85 gb->memory.mbcState.mbc6.currentBank1 = bank;
86 }
87 if (gb->cpu->pc < GB_BASE_VRAM) {
88 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
89 }
90}
91
92static bool _isMulticart(const uint8_t* mem) {
93 bool success = true;
94 struct VFile* vf;
95
96 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
97 success = success && GBIsROM(vf);
98 vf->close(vf);
99
100 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
101 success = success && GBIsROM(vf);
102 vf->close(vf);
103
104 return success;
105}
106
107void GBMBCSwitchSramBank(struct GB* gb, int bank) {
108 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
109 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
110 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
111 bankStart &= (gb->sramSize - 1);
112 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
113 }
114 gb->memory.sramBank = &gb->memory.sram[bankStart];
115 gb->memory.sramCurrentBank = bank;
116}
117
118void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
119 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
120 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
121 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
122 bankStart &= (gb->sramSize - 1);
123 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
124 }
125 if (!half) {
126 gb->memory.sramBank = &gb->memory.sram[bankStart];
127 gb->memory.sramCurrentBank = bank;
128 } else {
129 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
130 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
131 }
132}
133
134void GBMBCInit(struct GB* gb) {
135 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
136 if (gb->memory.rom) {
137 switch (cart->ramSize) {
138 case 0:
139 gb->sramSize = 0;
140 break;
141 case 1:
142 gb->sramSize = 0x800;
143 break;
144 default:
145 case 2:
146 gb->sramSize = 0x2000;
147 break;
148 case 3:
149 gb->sramSize = 0x8000;
150 break;
151 case 4:
152 gb->sramSize = 0x20000;
153 break;
154 case 5:
155 gb->sramSize = 0x10000;
156 break;
157 }
158
159 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
160 switch (cart->type) {
161 case 0:
162 case 8:
163 case 9:
164 gb->memory.mbcType = GB_MBC_NONE;
165 break;
166 case 1:
167 case 2:
168 case 3:
169 gb->memory.mbcType = GB_MBC1;
170 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
171 gb->memory.mbcState.mbc1.multicartStride = 4;
172 } else {
173 gb->memory.mbcState.mbc1.multicartStride = 5;
174 }
175 break;
176 case 5:
177 case 6:
178 gb->memory.mbcType = GB_MBC2;
179 break;
180 case 0x0F:
181 case 0x10:
182 gb->memory.mbcType = GB_MBC3_RTC;
183 break;
184 case 0x11:
185 case 0x12:
186 case 0x13:
187 gb->memory.mbcType = GB_MBC3;
188 break;
189 default:
190 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
191 // Fall through
192 case 0x19:
193 case 0x1A:
194 case 0x1B:
195 gb->memory.mbcType = GB_MBC5;
196 break;
197 case 0x1C:
198 case 0x1D:
199 case 0x1E:
200 gb->memory.mbcType = GB_MBC5_RUMBLE;
201 break;
202 case 0x20:
203 gb->memory.mbcType = GB_MBC6;
204 break;
205 case 0x22:
206 gb->memory.mbcType = GB_MBC7;
207 break;
208 case 0xFC:
209 gb->memory.mbcType = GB_POCKETCAM;
210 break;
211 case 0xFD:
212 gb->memory.mbcType = GB_TAMA5;
213 break;
214 case 0xFE:
215 gb->memory.mbcType = GB_HuC3;
216 break;
217 case 0xFF:
218 gb->memory.mbcType = GB_HuC1;
219 break;
220 }
221 }
222 } else {
223 gb->memory.mbcType = GB_MBC_NONE;
224 }
225 gb->memory.mbcRead = NULL;
226 switch (gb->memory.mbcType) {
227 case GB_MBC_NONE:
228 gb->memory.mbcWrite = _GBMBCNone;
229 break;
230 case GB_MBC1:
231 gb->memory.mbcWrite = _GBMBC1;
232 break;
233 case GB_MBC2:
234 gb->memory.mbcWrite = _GBMBC2;
235 gb->memory.mbcRead = _GBMBC2Read;
236 gb->sramSize = 0x100;
237 break;
238 case GB_MBC3:
239 gb->memory.mbcWrite = _GBMBC3;
240 break;
241 default:
242 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
243 // Fall through
244 case GB_MBC5:
245 gb->memory.mbcWrite = _GBMBC5;
246 break;
247 case GB_MBC6:
248 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
249 gb->memory.mbcWrite = _GBMBC6;
250 gb->memory.mbcRead = _GBMBC6Read;
251 break;
252 case GB_MBC7:
253 gb->memory.mbcWrite = _GBMBC7;
254 gb->memory.mbcRead = _GBMBC7Read;
255 gb->sramSize = 0x100;
256 break;
257 case GB_MMM01:
258 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
259 gb->memory.mbcWrite = _GBMBC1;
260 break;
261 case GB_HuC1:
262 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
263 gb->memory.mbcWrite = _GBMBC1;
264 break;
265 case GB_HuC3:
266 gb->memory.mbcWrite = _GBHuC3;
267 break;
268 case GB_TAMA5:
269 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
270 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
271 gb->memory.mbcWrite = _GBTAMA5;
272 gb->memory.mbcRead = _GBTAMA5Read;
273 gb->sramSize = 0x20;
274 break;
275 case GB_MBC3_RTC:
276 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
277 gb->memory.mbcWrite = _GBMBC3;
278 break;
279 case GB_MBC5_RUMBLE:
280 gb->memory.mbcWrite = _GBMBC5;
281 break;
282 case GB_POCKETCAM:
283 gb->memory.mbcWrite = _GBPocketCam;
284 gb->memory.mbcRead = _GBPocketCamRead;
285 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
286 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
287 }
288 break;
289 }
290
291 gb->memory.currentBank = 1;
292 gb->memory.sramCurrentBank = 0;
293 gb->memory.sramAccess = false;
294 gb->memory.rtcAccess = false;
295 gb->memory.activeRtcReg = 0;
296 gb->memory.rtcLatched = false;
297 gb->memory.rtcLastLatch = 0;
298 if (gb->memory.rtc) {
299 if (gb->memory.rtc->sample) {
300 gb->memory.rtc->sample(gb->memory.rtc);
301 }
302 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
303 } else {
304 gb->memory.rtcLastLatch = time(0);
305 }
306 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
307
308 GBResizeSram(gb, gb->sramSize);
309
310 if (gb->memory.mbcType == GB_MBC3_RTC) {
311 GBMBCRTCRead(gb);
312 }
313}
314
315static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
316 time_t t;
317 if (rtc) {
318 if (rtc->sample) {
319 rtc->sample(rtc);
320 }
321 t = rtc->unixTime(rtc);
322 } else {
323 t = time(0);
324 }
325 time_t currentLatch = t;
326 t -= *rtcLastLatch;
327 *rtcLastLatch = currentLatch;
328
329 int64_t diff;
330 diff = rtcRegs[0] + t % 60;
331 if (diff < 0) {
332 diff += 60;
333 t -= 60;
334 }
335 rtcRegs[0] = diff % 60;
336 t /= 60;
337 t += diff / 60;
338
339 diff = rtcRegs[1] + t % 60;
340 if (diff < 0) {
341 diff += 60;
342 t -= 60;
343 }
344 rtcRegs[1] = diff % 60;
345 t /= 60;
346 t += diff / 60;
347
348 diff = rtcRegs[2] + t % 24;
349 if (diff < 0) {
350 diff += 24;
351 t -= 24;
352 }
353 rtcRegs[2] = diff % 24;
354 t /= 24;
355 t += diff / 24;
356
357 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
358 rtcRegs[3] = diff;
359 rtcRegs[4] &= 0xFE;
360 rtcRegs[4] |= (diff >> 8) & 1;
361 if (diff & 0x200) {
362 rtcRegs[4] |= 0x80;
363 }
364}
365
366void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
367 struct GBMemory* memory = &gb->memory;
368 int bank = value & 0x1F;
369 int stride = 1 << memory->mbcState.mbc1.multicartStride;
370 switch (address >> 13) {
371 case 0x0:
372 switch (value) {
373 case 0:
374 memory->sramAccess = false;
375 break;
376 case 0xA:
377 memory->sramAccess = true;
378 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
379 break;
380 default:
381 // TODO
382 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
383 break;
384 }
385 break;
386 case 0x1:
387 if (!bank) {
388 ++bank;
389 }
390 bank &= stride - 1;
391 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
392 break;
393 case 0x2:
394 bank &= 3;
395 if (memory->mbcState.mbc1.mode) {
396 GBMBCSwitchBank0(gb, bank);
397 GBMBCSwitchSramBank(gb, bank);
398 }
399 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
400 break;
401 case 0x3:
402 memory->mbcState.mbc1.mode = value & 1;
403 if (memory->mbcState.mbc1.mode) {
404 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
405 } else {
406 GBMBCSwitchBank0(gb, 0);
407 GBMBCSwitchSramBank(gb, 0);
408 }
409 break;
410 default:
411 // TODO
412 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
413 break;
414 }
415}
416
417void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
418 struct GBMemory* memory = &gb->memory;
419 int shift = (address & 1) * 4;
420 int bank = value & 0xF;
421 switch (address >> 13) {
422 case 0x0:
423 switch (value) {
424 case 0:
425 memory->sramAccess = false;
426 break;
427 case 0xA:
428 memory->sramAccess = true;
429 break;
430 default:
431 // TODO
432 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
433 break;
434 }
435 break;
436 case 0x1:
437 if (!bank) {
438 ++bank;
439 }
440 GBMBCSwitchBank(gb, bank);
441 break;
442 case 0x5:
443 if (!memory->sramAccess) {
444 return;
445 }
446 address &= 0x1FF;
447 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
448 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
449 default:
450 // TODO
451 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
452 break;
453 }
454}
455
456static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
457 address &= 0x1FF;
458 int shift = (address & 1) * 4;
459 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
460}
461
462void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
463 struct GBMemory* memory = &gb->memory;
464 int bank = value & 0x7F;
465 switch (address >> 13) {
466 case 0x0:
467 switch (value) {
468 case 0:
469 memory->sramAccess = false;
470 break;
471 case 0xA:
472 memory->sramAccess = true;
473 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
474 break;
475 default:
476 // TODO
477 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
478 break;
479 }
480 break;
481 case 0x1:
482 if (!bank) {
483 ++bank;
484 }
485 GBMBCSwitchBank(gb, bank);
486 break;
487 case 0x2:
488 if (value < 4) {
489 GBMBCSwitchSramBank(gb, value);
490 memory->rtcAccess = false;
491 } else if (value >= 8 && value <= 0xC) {
492 memory->activeRtcReg = value - 8;
493 memory->rtcAccess = true;
494 }
495 break;
496 case 0x3:
497 if (memory->rtcLatched && value == 0) {
498 memory->rtcLatched = false;
499 } else if (!memory->rtcLatched && value == 1) {
500 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
501 memory->rtcLatched = true;
502 }
503 break;
504 }
505}
506
507void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
508 struct GBMemory* memory = &gb->memory;
509 int bank;
510 switch (address >> 12) {
511 case 0x0:
512 case 0x1:
513 switch (value) {
514 case 0:
515 memory->sramAccess = false;
516 break;
517 case 0xA:
518 memory->sramAccess = true;
519 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
520 break;
521 default:
522 // TODO
523 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
524 break;
525 }
526 break;
527 case 0x2:
528 bank = (memory->currentBank & 0x100) | value;
529 GBMBCSwitchBank(gb, bank);
530 break;
531 case 0x3:
532 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
533 GBMBCSwitchBank(gb, bank);
534 break;
535 case 0x4:
536 case 0x5:
537 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
538 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
539 value &= ~8;
540 }
541 GBMBCSwitchSramBank(gb, value & 0xF);
542 break;
543 default:
544 // TODO
545 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
546 break;
547 }
548}
549
550void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
551 struct GBMemory* memory = &gb->memory;
552 int bank = value;
553 switch (address >> 10) {
554 case 0:
555 switch (value) {
556 case 0:
557 memory->mbcState.mbc6.sramAccess = false;
558 break;
559 case 0xA:
560 memory->mbcState.mbc6.sramAccess = true;
561 break;
562 default:
563 // TODO
564 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
565 break;
566 }
567 break;
568 case 0x1:
569 GBMBCSwitchSramHalfBank(gb, 0, bank);
570 break;
571 case 0x2:
572 GBMBCSwitchSramHalfBank(gb, 1, bank);
573 break;
574 case 0x8:
575 case 0x9:
576 GBMBCSwitchHalfBank(gb, 0, bank);
577 break;
578 case 0xC:
579 case 0xD:
580 GBMBCSwitchHalfBank(gb, 1, bank);
581 break;
582 case 0x28:
583 case 0x29:
584 case 0x2A:
585 case 0x2B:
586 if (memory->mbcState.mbc6.sramAccess) {
587 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
588 }
589 break;
590 case 0x2C:
591 case 0x2D:
592 case 0x2E:
593 case 0x2F:
594 if (memory->mbcState.mbc6.sramAccess) {
595 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
596 }
597 break;
598 default:
599 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
600 break;
601 }
602}
603
604uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
605 if (!memory->mbcState.mbc6.sramAccess) {
606 return 0xFF;
607 }
608 switch (address >> 12) {
609 case 0xA:
610 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
611 case 0xB:
612 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
613 }
614 return 0xFF;
615}
616
617void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
618 int bank = value & 0x7F;
619 switch (address >> 13) {
620 case 0x0:
621 switch (value) {
622 default:
623 case 0:
624 gb->memory.mbcState.mbc7.access = 0;
625 break;
626 case 0xA:
627 gb->memory.mbcState.mbc7.access |= 1;
628 break;
629 }
630 break;
631 case 0x1:
632 GBMBCSwitchBank(gb, bank);
633 break;
634 case 0x2:
635 if (value == 0x40) {
636 gb->memory.mbcState.mbc7.access |= 2;
637 } else {
638 gb->memory.mbcState.mbc7.access &= ~2;
639 }
640 break;
641 case 0x5:
642 _GBMBC7Write(&gb->memory, address, value);
643 default:
644 // TODO
645 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
646 break;
647 }
648}
649
650uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
651 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
652 if (mbc7->access != 3) {
653 return 0xFF;
654 }
655 switch (address & 0xF0) {
656 case 0x20:
657 if (memory->rotation && memory->rotation->readTiltX) {
658 int32_t x = -memory->rotation->readTiltX(memory->rotation);
659 x >>= 21;
660 x += 0x81D0;
661 return x;
662 }
663 return 0xFF;
664 case 0x30:
665 if (memory->rotation && memory->rotation->readTiltX) {
666 int32_t x = -memory->rotation->readTiltX(memory->rotation);
667 x >>= 21;
668 x += 0x81D0;
669 return x >> 8;
670 }
671 return 7;
672 case 0x40:
673 if (memory->rotation && memory->rotation->readTiltY) {
674 int32_t y = -memory->rotation->readTiltY(memory->rotation);
675 y >>= 21;
676 y += 0x81D0;
677 return y;
678 }
679 return 0xFF;
680 case 0x50:
681 if (memory->rotation && memory->rotation->readTiltY) {
682 int32_t y = -memory->rotation->readTiltY(memory->rotation);
683 y >>= 21;
684 y += 0x81D0;
685 return y >> 8;
686 }
687 return 7;
688 case 0x60:
689 return 0;
690 case 0x80:
691 return mbc7->eeprom;
692 default:
693 return 0xFF;
694 }
695}
696
697static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
698 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
699 if (mbc7->access != 3) {
700 return;
701 }
702 switch (address & 0xF0) {
703 case 0x00:
704 mbc7->latch = (value & 0x55) == 0x55;
705 return;
706 case 0x10:
707 mbc7->latch |= (value & 0xAA);
708 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
709 memory->rotation->sample(memory->rotation);
710 }
711 mbc7->latch = 0;
712 return;
713 default:
714 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
715 return;
716 case 0x80:
717 break;
718 }
719 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
720 value = GBMBC7FieldFillDO(value); // Hi-Z
721 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
722 mbc7->state = GBMBC7_STATE_IDLE;
723 }
724 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
725 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
726 mbc7->sr <<= 1;
727 mbc7->sr |= GBMBC7FieldGetDI(value);
728 ++mbc7->srBits;
729 }
730 switch (mbc7->state) {
731 case GBMBC7_STATE_IDLE:
732 if (GBMBC7FieldIsDI(value)) {
733 mbc7->state = GBMBC7_STATE_READ_COMMAND;
734 mbc7->srBits = 0;
735 mbc7->sr = 0;
736 }
737 break;
738 case GBMBC7_STATE_READ_COMMAND:
739 if (mbc7->srBits == 10) {
740 mbc7->state = 0x10 | (mbc7->sr >> 6);
741 if (mbc7->state & 0xC) {
742 mbc7->state &= ~0x3;
743 }
744 mbc7->srBits = 0;
745 mbc7->address = mbc7->sr & 0x7F;
746 }
747 break;
748 case GBMBC7_STATE_DO:
749 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
750 mbc7->sr <<= 1;
751 --mbc7->srBits;
752 if (!mbc7->srBits) {
753 mbc7->state = GBMBC7_STATE_IDLE;
754 }
755 break;
756 default:
757 break;
758 }
759 switch (mbc7->state) {
760 case GBMBC7_STATE_EEPROM_EWEN:
761 mbc7->writable = true;
762 mbc7->state = GBMBC7_STATE_IDLE;
763 break;
764 case GBMBC7_STATE_EEPROM_EWDS:
765 mbc7->writable = false;
766 mbc7->state = GBMBC7_STATE_IDLE;
767 break;
768 case GBMBC7_STATE_EEPROM_WRITE:
769 if (mbc7->srBits == 16) {
770 if (mbc7->writable) {
771 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
772 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
773 }
774 mbc7->state = GBMBC7_STATE_IDLE;
775 }
776 break;
777 case GBMBC7_STATE_EEPROM_ERASE:
778 if (mbc7->writable) {
779 memory->sram[mbc7->address * 2] = 0xFF;
780 memory->sram[mbc7->address * 2 + 1] = 0xFF;
781 }
782 mbc7->state = GBMBC7_STATE_IDLE;
783 break;
784 case GBMBC7_STATE_EEPROM_READ:
785 mbc7->srBits = 16;
786 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
787 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
788 mbc7->state = GBMBC7_STATE_DO;
789 value = GBMBC7FieldClearDO(value);
790 break;
791 case GBMBC7_STATE_EEPROM_WRAL:
792 if (mbc7->srBits == 16) {
793 if (mbc7->writable) {
794 int i;
795 for (i = 0; i < 128; ++i) {
796 memory->sram[i * 2] = mbc7->sr >> 8;
797 memory->sram[i * 2 + 1] = mbc7->sr;
798 }
799 }
800 mbc7->state = GBMBC7_STATE_IDLE;
801 }
802 break;
803 case GBMBC7_STATE_EEPROM_ERAL:
804 if (mbc7->writable) {
805 int i;
806 for (i = 0; i < 128; ++i) {
807 memory->sram[i * 2] = 0xFF;
808 memory->sram[i * 2 + 1] = 0xFF;
809 }
810 }
811 mbc7->state = GBMBC7_STATE_IDLE;
812 break;
813 default:
814 break;
815 }
816 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
817 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
818 }
819 mbc7->eeprom = value;
820}
821
822void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
823 struct GBMemory* memory = &gb->memory;
824 int bank = value & 0x3F;
825 if (address & 0x1FFF) {
826 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
827 }
828
829 switch (address >> 13) {
830 case 0x0:
831 switch (value) {
832 case 0xA:
833 memory->sramAccess = true;
834 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
835 break;
836 default:
837 memory->sramAccess = false;
838 break;
839 }
840 break;
841 case 0x1:
842 GBMBCSwitchBank(gb, bank);
843 break;
844 case 0x2:
845 GBMBCSwitchSramBank(gb, bank);
846 break;
847 default:
848 // TODO
849 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
850 break;
851 }
852}
853
854void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
855 struct GBMemory* memory = &gb->memory;
856 int bank = value & 0x3F;
857 switch (address >> 13) {
858 case 0x0:
859 switch (value) {
860 case 0:
861 memory->sramAccess = false;
862 break;
863 case 0xA:
864 memory->sramAccess = true;
865 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
866 break;
867 default:
868 // TODO
869 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
870 break;
871 }
872 break;
873 case 0x1:
874 GBMBCSwitchBank(gb, bank);
875 break;
876 case 0x2:
877 if (value < 0x10) {
878 GBMBCSwitchSramBank(gb, value);
879 memory->mbcState.pocketCam.registersActive = false;
880 } else {
881 memory->mbcState.pocketCam.registersActive = true;
882 }
883 break;
884 case 0x5:
885 address &= 0x7F;
886 if (address == 0 && value & 1) {
887 value &= 6; // TODO: Timing
888 _GBPocketCamCapture(memory);
889 }
890 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
891 memory->mbcState.pocketCam.registers[address] = value;
892 }
893 break;
894 default:
895 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
896 break;
897 }
898}
899
900uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
901 if (memory->mbcState.pocketCam.registersActive) {
902 if ((address & 0x7F) == 0) {
903 return memory->mbcState.pocketCam.registers[0];
904 }
905 return 0;
906 }
907 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
908}
909
910void _GBPocketCamCapture(struct GBMemory* memory) {
911 if (!memory->cam) {
912 return;
913 }
914 const void* image = NULL;
915 size_t stride;
916 enum mColorFormat format;
917 memory->cam->requestImage(memory->cam, &image, &stride, &format);
918 if (!image) {
919 return;
920 }
921 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
922 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
923 size_t x, y;
924 for (y = 0; y < GBCAM_HEIGHT; ++y) {
925 for (x = 0; x < GBCAM_WIDTH; ++x) {
926 uint32_t gray;
927 uint32_t color;
928 switch (format) {
929 case mCOLOR_XBGR8:
930 case mCOLOR_XRGB8:
931 case mCOLOR_ARGB8:
932 case mCOLOR_ABGR8:
933 color = ((const uint32_t*) image)[y * stride + x];
934 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
935 break;
936 case mCOLOR_BGRX8:
937 case mCOLOR_RGBX8:
938 case mCOLOR_RGBA8:
939 case mCOLOR_BGRA8:
940 color = ((const uint32_t*) image)[y * stride + x];
941 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
942 break;
943 case mCOLOR_BGR5:
944 case mCOLOR_RGB5:
945 case mCOLOR_ARGB5:
946 case mCOLOR_ABGR5:
947 color = ((const uint16_t*) image)[y * stride + x];
948 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
949 break;
950 case mCOLOR_BGR565:
951 case mCOLOR_RGB565:
952 color = ((const uint16_t*) image)[y * stride + x];
953 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
954 break;
955 case mCOLOR_BGRA5:
956 case mCOLOR_RGBA5:
957 color = ((const uint16_t*) image)[y * stride + x];
958 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
959 break;
960 default:
961 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
962 return;
963 }
964 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
965 gray = (gray + 1) * exposure / 0x300;
966 // TODO: Additional processing
967 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
968 if (gray < pocketCam->registers[matrixEntry + 6]) {
969 gray = 0x101;
970 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
971 gray = 0x100;
972 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
973 gray = 0x001;
974 } else {
975 gray = 0;
976 }
977 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
978 uint16_t existing;
979 LOAD_16LE(existing, coord + 0x100, memory->sram);
980 existing |= gray << (7 - (x & 7));
981 STORE_16LE(existing, coord + 0x100, memory->sram);
982 }
983 }
984}
985
986void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
987 struct GBMemory* memory = &gb->memory;
988 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
989 switch (address >> 13) {
990 case 0x5:
991 if (address & 1) {
992 tama5->reg = value;
993 } else {
994 value &= 0xF;
995 if (tama5->reg < GBTAMA5_MAX) {
996 tama5->registers[tama5->reg] = value;
997 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
998 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
999 switch (tama5->reg) {
1000 case GBTAMA5_BANK_LO:
1001 case GBTAMA5_BANK_HI:
1002 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1003 break;
1004 case GBTAMA5_WRITE_LO:
1005 case GBTAMA5_WRITE_HI:
1006 case GBTAMA5_CS:
1007 break;
1008 case GBTAMA5_ADDR_LO:
1009 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1010 case 0x0: // RAM write
1011 memory->sram[address] = out;
1012 break;
1013 case 0x1: // RAM read
1014 break;
1015 default:
1016 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1017 }
1018 break;
1019 default:
1020 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1021 break;
1022 }
1023 } else {
1024 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1025 }
1026 }
1027 break;
1028 default:
1029 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1030 }
1031}
1032
1033uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1034 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1035 if ((address & 0x1FFF) > 1) {
1036 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1037 }
1038 if (address & 1) {
1039 return 0xFF;
1040 } else {
1041 uint8_t value = 0xF0;
1042 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1043 switch (tama5->reg) {
1044 case GBTAMA5_ACTIVE:
1045 return 0xF1;
1046 case GBTAMA5_READ_LO:
1047 case GBTAMA5_READ_HI:
1048 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1049 case 1:
1050 value = memory->sram[address];
1051 break;
1052 default:
1053 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1054 break;
1055 }
1056 if (tama5->reg == GBTAMA5_READ_HI) {
1057 value >>= 4;
1058 }
1059 value |= 0xF0;
1060 return value;
1061 default:
1062 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1063 return 0xF1;
1064 }
1065 }
1066}
1067
1068void GBMBCRTCRead(struct GB* gb) {
1069 struct GBMBCRTCSaveBuffer rtcBuffer;
1070 struct VFile* vf = gb->sramVf;
1071 if (!vf) {
1072 return;
1073 }
1074 vf->seek(vf, gb->sramSize, SEEK_SET);
1075 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1076 return;
1077 }
1078
1079 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1080 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1081 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1082 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1083 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1084 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1085}
1086
1087void GBMBCRTCWrite(struct GB* gb) {
1088 struct VFile* vf = gb->sramVf;
1089 if (!vf) {
1090 return;
1091 }
1092
1093 uint8_t rtcRegs[5];
1094 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1095 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1096 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1097
1098 struct GBMBCRTCSaveBuffer rtcBuffer;
1099 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1100 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1101 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1102 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1103 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1104 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1105 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1106 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1107 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1108 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1109 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1110
1111 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1112 // Writing past the end of the file can invalidate the file mapping
1113 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1114 gb->memory.sram = NULL;
1115 }
1116 vf->seek(vf, gb->sramSize, SEEK_SET);
1117 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1118 if (!gb->memory.sram) {
1119 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1120 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1121 }
1122}