src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13
14static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
17static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
18static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
19
20void GBAMemoryInit(struct GBAMemory* memory) {
21 memory->d.load32 = GBALoad32;
22 memory->d.load16 = GBALoad16;
23 memory->d.loadU16 = GBALoadU16;
24 memory->d.load8 = GBALoad8;
25 memory->d.loadU8 = GBALoadU8;
26 memory->d.store32 = GBAStore32;
27 memory->d.store16 = GBAStore16;
28 memory->d.store8 = GBAStore8;
29
30 memory->bios = (uint32_t*) hleBios;
31 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
32 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
33 memory->rom = 0;
34 memset(memory->io, 0, sizeof(memory->io));
35 memset(memory->dma, 0, sizeof(memory->dma));
36
37 if (!memory->wram || !memory->iwram) {
38 GBAMemoryDeinit(memory);
39 memory->p->errno = GBA_OUT_OF_MEMORY;
40 memory->p->errstr = GBA_CANNOT_MMAP;
41 }
42
43 GBASavedataInit(&memory->savedata, "test.sav");
44
45 int i;
46 for (i = 0; i < 16; ++i) {
47 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
48 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
49 memory->waitstates32[i] = GBA_BASE_WAITSTATES[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
50 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
51 }
52 for (; i < 256; ++i) {
53 memory->waitstates16[i] = 0;
54 memory->waitstatesSeq16[i] = 0;
55 memory->waitstates32[i] = 0;
56 memory->waitstatesSeq32[i] = 0;
57 }
58
59 memory->activeRegion = 0;
60 memory->d.activeRegion = 0;
61 memory->d.activeMask = 0;
62 memory->d.setActiveRegion = GBASetActiveRegion;
63 memory->d.activePrefetchCycles32 = 0;
64 memory->d.activePrefetchCycles16 = 0;
65}
66
67void GBAMemoryDeinit(struct GBAMemory* memory) {
68 munmap(memory->wram, SIZE_WORKING_RAM);
69 munmap(memory->iwram, SIZE_WORKING_IRAM);
70 GBASavedataDeinit(&memory->savedata);
71}
72
73static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
74 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
75
76 memory->activePrefetchCycles32 = gbaMemory->waitstates32[address >> BASE_OFFSET];
77 memory->activePrefetchCycles16 = gbaMemory->waitstates16[address >> BASE_OFFSET];
78 gbaMemory->activeRegion = address >> BASE_OFFSET;
79 switch (address & ~OFFSET_MASK) {
80 case BASE_BIOS:
81 memory->activeRegion = gbaMemory->bios;
82 memory->activeMask = SIZE_BIOS - 1;
83 break;
84 case BASE_WORKING_RAM:
85 memory->activeRegion = gbaMemory->wram;
86 memory->activeMask = SIZE_WORKING_RAM - 1;
87 break;
88 case BASE_WORKING_IRAM:
89 memory->activeRegion = gbaMemory->iwram;
90 memory->activeMask = SIZE_WORKING_IRAM - 1;
91 break;
92 case BASE_CART0:
93 case BASE_CART0_EX:
94 case BASE_CART1:
95 case BASE_CART1_EX:
96 case BASE_CART2:
97 case BASE_CART2_EX:
98 memory->activeRegion = gbaMemory->rom;
99 memory->activeMask = SIZE_CART0 - 1;
100 break;
101 default:
102 memory->activeRegion = 0;
103 memory->activeMask = 0;
104 break;
105 }
106}
107
108int32_t GBALoad32(struct ARMMemory* memory, uint32_t address) {
109 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
110 uint32_t value = 0;
111
112 switch (address & ~OFFSET_MASK) {
113 case BASE_BIOS:
114 break;
115 case BASE_WORKING_RAM:
116 value = gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
117 break;
118 case BASE_WORKING_IRAM:
119 value = gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
120 break;
121 case BASE_IO:
122 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1)) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
123 break;
124 case BASE_PALETTE_RAM:
125 value = ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2];
126 break;
127 case BASE_VRAM:
128 value = ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2];
129 break;
130 case BASE_OAM:
131 value = ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2];
132 break;
133 case BASE_CART0:
134 case BASE_CART0_EX:
135 case BASE_CART1:
136 case BASE_CART1_EX:
137 case BASE_CART2:
138 case BASE_CART2_EX:
139 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
140 value = gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
141 }
142 break;
143 case BASE_CART_SRAM:
144 break;
145 default:
146 break;
147 }
148
149 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
150 int rotate = (address & 3) << 3;
151 return (value >> rotate) | (value << (32 - rotate));
152}
153
154int16_t GBALoad16(struct ARMMemory* memory, uint32_t address) {
155 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
156
157 switch (address & ~OFFSET_MASK) {
158 case BASE_BIOS:
159 break;
160 case BASE_WORKING_RAM:
161 return ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
162 case BASE_WORKING_IRAM:
163 return ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
164 case BASE_IO:
165 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
166 case BASE_PALETTE_RAM:
167 return gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
168 case BASE_VRAM:
169 return gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
170 case BASE_OAM:
171 return gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1];
172 case BASE_CART0:
173 case BASE_CART0_EX:
174 case BASE_CART1:
175 case BASE_CART1_EX:
176 case BASE_CART2:
177 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
178 return ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
179 }
180 case BASE_CART2_EX:
181 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
182 return GBASavedataReadEEPROM(&gbaMemory->savedata);
183 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
184 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
185 }
186 case BASE_CART_SRAM:
187 break;
188 default:
189 break;
190 }
191
192 return 0;
193}
194
195uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address) {
196 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
197
198 switch (address & ~OFFSET_MASK) {
199 case BASE_BIOS:
200 break;
201 case BASE_WORKING_RAM:
202 return ((uint16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
203 case BASE_WORKING_IRAM:
204 return ((uint16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
205 case BASE_IO:
206 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
207 case BASE_PALETTE_RAM:
208 return gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
209 case BASE_VRAM:
210 return gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
211 case BASE_OAM:
212 return gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1];
213 case BASE_CART0:
214 case BASE_CART0_EX:
215 case BASE_CART1:
216 case BASE_CART1_EX:
217 case BASE_CART2:
218 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
219 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
220 }
221 case BASE_CART2_EX:
222 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
223 return GBASavedataReadEEPROM(&gbaMemory->savedata);
224 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
225 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
226 }
227 case BASE_CART_SRAM:
228 break;
229 default:
230 break;
231 }
232
233 return 0;
234}
235
236int8_t GBALoad8(struct ARMMemory* memory, uint32_t address) {
237 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
238
239 switch (address & ~OFFSET_MASK) {
240 case BASE_BIOS:
241 break;
242 case BASE_WORKING_RAM:
243 return ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
244 case BASE_WORKING_IRAM:
245 return ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
246 case BASE_IO:
247 break;
248 case BASE_PALETTE_RAM:
249 break;
250 case BASE_VRAM:
251 break;
252 case BASE_OAM:
253 break;
254 case BASE_CART0:
255 case BASE_CART0_EX:
256 case BASE_CART1:
257 case BASE_CART1_EX:
258 case BASE_CART2:
259 case BASE_CART2_EX:
260 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
261 return ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
262 }
263 case BASE_CART_SRAM:
264 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
265 GBASavedataInitSRAM(&gbaMemory->savedata);
266 }
267 return gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
268 default:
269 break;
270 }
271
272 return 0;
273}
274
275uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address) {
276 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
277
278 switch (address & ~OFFSET_MASK) {
279 case BASE_BIOS:
280 break;
281 case BASE_WORKING_RAM:
282 return ((uint8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
283 break;
284 case BASE_WORKING_IRAM:
285 return ((uint8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
286 break;
287 case BASE_IO:
288 return (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
289 case BASE_PALETTE_RAM:
290 break;
291 case BASE_VRAM:
292 break;
293 case BASE_OAM:
294 break;
295 case BASE_CART0:
296 case BASE_CART0_EX:
297 case BASE_CART1:
298 case BASE_CART1_EX:
299 case BASE_CART2:
300 case BASE_CART2_EX:
301 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
302 return ((uint8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
303 }
304 case BASE_CART_SRAM:
305 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
306 GBASavedataInitSRAM(&gbaMemory->savedata);
307 }
308 return gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
309 default:
310 break;
311 }
312
313 return 0;
314}
315
316void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value) {
317 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
318
319 switch (address & ~OFFSET_MASK) {
320 case BASE_WORKING_RAM:
321 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
322 break;
323 case BASE_WORKING_IRAM:
324 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
325 break;
326 case BASE_IO:
327 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
328 break;
329 case BASE_PALETTE_RAM:
330 ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2] = value;
331 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
332 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
333 break;
334 case BASE_VRAM:
335 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
336 ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2] = value;
337 }
338 break;
339 case BASE_OAM:
340 ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2] = value;
341 break;
342 case BASE_CART0:
343 break;
344 case BASE_CART_SRAM:
345 break;
346 default:
347 break;
348 }
349}
350
351void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value) {
352 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
353
354 switch (address & ~OFFSET_MASK) {
355 case BASE_WORKING_RAM:
356 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
357 break;
358 case BASE_WORKING_IRAM:
359 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
360 break;
361 case BASE_IO:
362 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
363 break;
364 case BASE_PALETTE_RAM:
365 gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1] = value;
366 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
367 break;
368 case BASE_VRAM:
369 if ((address & OFFSET_MASK) < SIZE_VRAM) {
370 gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1] = value;
371 }
372 break;
373 case BASE_OAM:
374 gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1] = value;
375 break;
376 case BASE_CART0:
377 break;
378 case BASE_CART2_EX:
379 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
380 GBASavedataInitEEPROM(&gbaMemory->savedata);
381 }
382 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
383 break;
384 case BASE_CART_SRAM:
385 break;
386 default:
387 break;
388 }
389}
390
391void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value) {
392 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
393
394 switch (address & ~OFFSET_MASK) {
395 case BASE_WORKING_RAM:
396 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
397 break;
398 case BASE_WORKING_IRAM:
399 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
400 break;
401 case BASE_IO:
402 break;
403 case BASE_PALETTE_RAM:
404 break;
405 case BASE_VRAM:
406 break;
407 case BASE_OAM:
408 break;
409 case BASE_CART0:
410 break;
411 case BASE_CART_SRAM:
412 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
413 if (address == SAVEDATA_FLASH_BASE) {
414 GBASavedataInitFlash(&gbaMemory->savedata);
415 } else {
416 GBASavedataInitSRAM(&gbaMemory->savedata);
417 }
418 }
419 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
420 GBASavedataWriteFlash(&gbaMemory->savedata, value);
421 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
422 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
423 }
424 break;
425 default:
426 break;
427 }
428}
429
430void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
431 int sram = parameters & 0x0003;
432 int ws0 = (parameters & 0x000C) >> 2;
433 int ws0seq = (parameters & 0x0010) >> 4;
434 int ws1 = (parameters & 0x0060) >> 5;
435 int ws1seq = (parameters & 0x0080) >> 7;
436 int ws2 = (parameters & 0x0300) >> 8;
437 int ws2seq = (parameters & 0x0400) >> 10;
438 int prefetch = parameters & 0x4000;
439 (void)(prefetch);
440
441 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
442 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
443 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
444 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
445
446 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
447 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
448 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
449
450 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
451 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
452 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
453
454 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
455 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
456 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
457
458 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0 + 1] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
459 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1 + 1] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
460 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2 + 1] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
461
462 memory->d.activePrefetchCycles32 = memory->waitstates32[memory->activeRegion];
463 memory->d.activePrefetchCycles16 = memory->waitstates16[memory->activeRegion];
464}
465
466int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
467 struct GBADMA* dma;
468 int32_t test = INT_MAX;
469
470 dma = &memory->dma[0];
471 dma->nextIRQ -= cycles;
472 if (dma->enable && dma->doIrq && dma->nextIRQ) {
473 if (dma->nextIRQ <= 0) {
474 dma->nextIRQ = INT_MAX;
475 GBARaiseIRQ(memory->p, IRQ_DMA0);
476 } else if (dma->nextIRQ < test) {
477 test = dma->nextIRQ;
478 }
479 }
480
481 dma = &memory->dma[1];
482 dma->nextIRQ -= cycles;
483 if (dma->enable && dma->doIrq && dma->nextIRQ) {
484 if (dma->nextIRQ <= 0) {
485 dma->nextIRQ = INT_MAX;
486 GBARaiseIRQ(memory->p, IRQ_DMA1);
487 } else if (dma->nextIRQ < test) {
488 test = dma->nextIRQ;
489 }
490 }
491
492 dma = &memory->dma[2];
493 dma->nextIRQ -= cycles;
494 if (dma->enable && dma->doIrq && dma->nextIRQ) {
495 if (dma->nextIRQ <= 0) {
496 dma->nextIRQ = INT_MAX;
497 GBARaiseIRQ(memory->p, IRQ_DMA2);
498 } else if (dma->nextIRQ < test) {
499 test = dma->nextIRQ;
500 }
501 }
502
503 dma = &memory->dma[3];
504 dma->nextIRQ -= cycles;
505 if (dma->enable && dma->doIrq && dma->nextIRQ) {
506 if (dma->nextIRQ <= 0) {
507 dma->nextIRQ = INT_MAX;
508 GBARaiseIRQ(memory->p, IRQ_DMA3);
509 } else if (dma->nextIRQ < test) {
510 test = dma->nextIRQ;
511 }
512 }
513
514 return test;
515}
516
517void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
518 memory->dma[dma].source = address & 0xFFFFFFFE;
519}
520
521void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
522 memory->dma[dma].dest = address & 0xFFFFFFFE;
523}
524
525void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
526 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
527}
528
529uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
530 struct GBADMA* currentDma = &memory->dma[dma];
531 int wasEnabled = currentDma->enable;
532 currentDma->packed = control;
533 currentDma->nextIRQ = 0;
534
535 if (currentDma->drq) {
536 GBALog(GBA_LOG_STUB, "DRQ not implemented");
537 }
538
539 if (!wasEnabled && currentDma->enable) {
540 currentDma->nextSource = currentDma->source;
541 currentDma->nextDest = currentDma->dest;
542 currentDma->nextCount = currentDma->count;
543 GBAMemoryScheduleDMA(memory, dma, currentDma);
544 }
545 // If the DMA has already occurred, this value might have changed since the function started
546 return currentDma->packed;
547};
548
549void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
550 switch (info->timing) {
551 case DMA_TIMING_NOW:
552 GBAMemoryServiceDMA(memory, number, info);
553 break;
554 case DMA_TIMING_HBLANK:
555 // Handled implicitly
556 break;
557 case DMA_TIMING_VBLANK:
558 // Handled implicitly
559 break;
560 case DMA_TIMING_CUSTOM:
561 switch (number) {
562 case 0:
563 GBALog(GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
564 break;
565 case 1:
566 case 2:
567 //this.cpu.irq.audio.scheduleFIFODma(number, info);
568 break;
569 case 3:
570 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
571 break;
572 }
573 }
574}
575
576void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
577 struct GBADMA* dma;
578 int i;
579 for (i = 0; i < 4; ++i) {
580 dma = &memory->dma[i];
581 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
582 GBAMemoryServiceDMA(memory, i, dma);
583 }
584 }
585}
586
587void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
588 struct GBADMA* dma;
589 int i;
590 for (i = 0; i < 4; ++i) {
591 dma = &memory->dma[i];
592 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
593 GBAMemoryServiceDMA(memory, i, dma);
594 }
595 }
596}
597
598void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
599 if (!info->enable) {
600 // There was a DMA scheduled that got canceled
601 return;
602 }
603
604 uint32_t width = info->width ? 4 : 2;
605 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
606 int destOffset = DMA_OFFSET[info->dstControl] * width;
607 int32_t wordsRemaining = info->nextCount;
608 uint32_t source = info->nextSource;
609 uint32_t dest = info->nextDest;
610 uint32_t sourceRegion = source >> BASE_OFFSET;
611 uint32_t destRegion = dest >> BASE_OFFSET;
612
613 if (width == 4) {
614 int32_t word;
615 source &= 0xFFFFFFFC;
616 dest &= 0xFFFFFFFC;
617 while (wordsRemaining--) {
618 word = GBALoad32(&memory->d, source);
619 GBAStore32(&memory->d, dest, word);
620 source += sourceOffset;
621 dest += destOffset;
622 }
623 } else {
624 uint16_t word;
625 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
626 while (wordsRemaining--) {
627 word = GBASavedataReadEEPROM(&memory->savedata);
628 GBAStore16(&memory->d, dest, word);
629 source += sourceOffset;
630 dest += destOffset;
631 }
632 } else if (destRegion == REGION_CART2_EX) {
633 if (memory->savedata.type != SAVEDATA_EEPROM) {
634 GBASavedataInitEEPROM(&memory->savedata);
635 }
636 while (wordsRemaining) {
637 word = GBALoadU16(&memory->d, source);
638 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
639 source += sourceOffset;
640 dest += destOffset;
641 --wordsRemaining;
642 }
643 } else {
644 while (wordsRemaining--) {
645 word = GBALoadU16(&memory->d, source);
646 GBAStore16(&memory->d, dest, word);
647 source += sourceOffset;
648 dest += destOffset;
649 }
650 }
651 }
652
653 if (info->doIrq) {
654 info->nextIRQ = memory->p->cpu.cycles + 2;
655 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
656 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
657 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
658 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
659 }
660
661 info->nextSource = source;
662 info->nextDest = dest;
663 info->nextCount = wordsRemaining;
664
665 if (!info->repeat) {
666 info->enable = 0;
667
668 // Clear the enable bit in memory
669 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
670 } else {
671 info->nextCount = info->count;
672 if (info->dstControl == DMA_INCREMENT_RELOAD) {
673 info->nextDest = info->dest;
674 }
675 GBAMemoryScheduleDMA(memory, number, info);
676 }
677}