src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26
27static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
28static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
29static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
30
31enum {
32 DS7_SP_BASE = 0x380FD80,
33 DS7_SP_BASE_IRQ = 0x380FF80,
34 DS7_SP_BASE_SVC = 0x380FFC0,
35
36 DS9_SP_BASE = 0x3002F7C,
37 DS9_SP_BASE_IRQ = 0x3003F80,
38 DS9_SP_BASE_SVC = 0x3003FC0,
39};
40
41static void DSInit(void* cpu, struct mCPUComponent* component);
42
43static void DS7Reset(struct ARMCore* cpu);
44static void DS7TestIRQ(struct ARMCore* cpu);
45static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
46static void DS7ProcessEvents(struct ARMCore* cpu);
47
48static void DS9Reset(struct ARMCore* cpu);
49static void DS9TestIRQ(struct ARMCore* cpu);
50static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
51static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
52static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
53static void DS9ProcessEvents(struct ARMCore* cpu);
54
55static void DSProcessEvents(struct DSCommon* dscore);
56static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
57static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
58static void DSBreakpoint(struct ARMCore* cpu, int immediate);
59
60static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
61 UNUSED(cyclesLate);
62 struct DS* ds = context;
63 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
64 if (ds->activeCpu == ds->ds9.cpu) {
65 ds->activeCpu = ds->ds7.cpu;
66 ds->cycleDrift += cycles;
67 cycles = ds->cycleDrift >> 1;
68 timing = &ds->ds7.timing;
69 } else {
70 ds->activeCpu = ds->ds9.cpu;
71 ds->cycleDrift -= cycles << 1;
72 cycles = ds->cycleDrift + SLICE_CYCLES;
73 timing = &ds->ds9.timing;
74 }
75 mTimingSchedule(timing, &ds->slice, cycles);
76 ds->sliceStart = mTimingCurrentTime(timing);
77 ds->earlyExit = true;
78}
79
80static void _divide(struct mTiming* timing, void* context, uint32_t cyclesLate) {
81 UNUSED(timing);
82 UNUSED(cyclesLate);
83 struct DS* ds = context;
84 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x8000;
85 int64_t numerator;
86 int64_t denominator;
87 LOAD_64LE(numerator, DS9_REG_DIV_NUMER_0, ds->memory.io9);
88 LOAD_64LE(denominator, DS9_REG_DIV_DENOM_0, ds->memory.io9);
89 bool max = false;
90 switch (ds->memory.io9[DS9_REG_DIVCNT >> 1] & 0x3) {
91 case 0:
92 numerator = (int64_t)(int32_t) numerator;
93 case 1:
94 case 3:
95 denominator = (int64_t)(int32_t) denominator;
96 break;
97 }
98 if (numerator == INT64_MIN) {
99 max = true;
100 }
101 if (!denominator) {
102 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
103 STORE_64LE(numerator, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
104 numerator >>= 63LL;
105 numerator = -numerator;
106 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
107 return;
108 }
109 if (denominator == -1LL && max) {
110 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
111 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
112 return;
113 }
114 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x4000;
115 int64_t result = numerator / denominator;
116 int64_t remainder = numerator % denominator; // TODO: defined behavior for negative denominator?
117 STORE_64LE(result, DS9_REG_DIV_RESULT_0, ds->memory.io9);
118 STORE_64LE(remainder, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
119}
120
121 static void _sqrt(struct mTiming* timing, void* context, uint32_t cyclesLate) {
122 UNUSED(timing);
123 UNUSED(cyclesLate);
124 struct DS* ds = context;
125 ds->memory.io9[DS9_REG_SQRTCNT >> 1] &= ~0x8000;
126 uint64_t param;
127 LOAD_64LE(param, DS9_REG_SQRT_PARAM_0, ds->memory.io9);
128 if (!(ds->memory.io9[DS9_REG_SQRTCNT >> 1] & 1)) {
129 param &= 0xFFFFFFFFULL;
130 }
131
132 uint64_t result = 0;
133 uint64_t bit = 0x4000000000000000ULL; // The second-to-top bit is set: 1 << 30 for 32 bits
134
135 // "bit" starts at the highest power of four <= the argument.
136 while (bit > param) {
137 bit >>= 2;
138 }
139
140 while (bit != 0) {
141 if (param >= param + bit) {
142 param -= param + bit;
143 param = (result >> 1) + bit;
144 } else {
145 param >>= 1;
146 }
147 bit >>= 2;
148 }
149 STORE_32LE(result, DS9_REG_SQRT_RESULT_LO, ds->memory.io9);
150}
151
152void DSCreate(struct DS* ds) {
153 ds->d.id = DS_COMPONENT_MAGIC;
154 ds->d.init = DSInit;
155 ds->d.deinit = NULL;
156 ds->ds7.p = ds;
157 ds->ds9.p = ds;
158 ds->ds7.cpu = NULL;
159 ds->ds9.cpu = NULL;
160 ds->ds7.ipc = &ds->ds9;
161 ds->ds9.ipc = &ds->ds7;
162}
163
164static void DSInit(void* cpu, struct mCPUComponent* component) {
165 struct DS* ds = (struct DS*) component;
166 struct ARMCore* core = cpu;
167 if (!ds->ds7.cpu) {
168 // The ARM7 must get initialized first
169 ds->ds7.cpu = core;
170 ds->debugger = 0;
171 ds->sync = 0;
172 return;
173 }
174 ds->ds9.cpu = cpu;
175 ds->activeCpu = NULL;
176
177 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
178
179 ds->slice.name = "DS CPU Time Slicing";
180 ds->slice.callback = _slice;
181 ds->slice.context = ds;
182 ds->slice.priority = UINT_MAX;
183
184 CircleBufferInit(&ds->ds7.fifo, 64);
185 CircleBufferInit(&ds->ds9.fifo, 64);
186
187 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
188 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
189 DSMemoryInit(ds);
190 DSDMAInit(ds);
191
192 DSVideoInit(&ds->video);
193 ds->video.p = ds;
194
195 ds->ds7.springIRQ = 0;
196 ds->ds9.springIRQ = 0;
197 DSTimerInit(ds);
198 ds->keySource = NULL;
199 ds->rtcSource = NULL;
200 ds->rumble = NULL;
201
202 ds->romVf = NULL;
203
204 ds->keyCallback = NULL;
205
206 ds->divEvent.name = "DS Hardware Divide";
207 ds->divEvent.callback = _divide;
208 ds->divEvent.context = ds;
209 ds->divEvent.priority = 0x50;
210
211 ds->sqrtEvent.name = "DS Hardware Sqrt";
212 ds->sqrtEvent.callback = _sqrt;
213 ds->sqrtEvent.context = ds;
214 ds->sqrtEvent.priority = 0x51;
215
216 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
217 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
218}
219
220void DSUnloadROM(struct DS* ds) {
221 if (ds->romVf) {
222 ds->romVf->close(ds->romVf);
223 ds->romVf = NULL;
224 }
225}
226
227void DSDestroy(struct DS* ds) {
228 CircleBufferDeinit(&ds->ds7.fifo);
229 CircleBufferDeinit(&ds->ds9.fifo);
230 DSUnloadROM(ds);
231 DSMemoryDeinit(ds);
232 mTimingDeinit(&ds->ds7.timing);
233 mTimingDeinit(&ds->ds9.timing);
234}
235
236void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
237 irqh->reset = DS7Reset;
238 irqh->processEvents = DS7ProcessEvents;
239 irqh->swi16 = DS7Swi16;
240 irqh->swi32 = DS7Swi32;
241 irqh->hitIllegal = DSIllegal;
242 irqh->readCPSR = DS7TestIRQ;
243 irqh->writeCP15 = NULL;
244 irqh->readCP15 = NULL;
245 irqh->hitStub = DSHitStub;
246 irqh->bkpt16 = DSBreakpoint;
247 irqh->bkpt32 = DSBreakpoint;
248}
249
250void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
251 irqh->reset = DS9Reset;
252 irqh->processEvents = DS9ProcessEvents;
253 irqh->swi16 = DS9Swi16;
254 irqh->swi32 = DS9Swi32;
255 irqh->hitIllegal = DSIllegal;
256 irqh->readCPSR = DS9TestIRQ;
257 irqh->writeCP15 = DS9WriteCP15;
258 irqh->readCP15 = DS9ReadCP15;
259 irqh->hitStub = DSHitStub;
260 irqh->bkpt16 = DSBreakpoint;
261 irqh->bkpt32 = DSBreakpoint;
262}
263
264void DS7Reset(struct ARMCore* cpu) {
265 ARMSetPrivilegeMode(cpu, MODE_IRQ);
266 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
267 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
268 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
269 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
270 cpu->gprs[ARM_SP] = DS7_SP_BASE;
271
272 struct DS* ds = (struct DS*) cpu->master;
273 mTimingClear(&ds->ds7.timing);
274 CircleBufferInit(&ds->ds7.fifo, 64);
275 DSMemoryReset(ds);
276 DSDMAReset(&ds->ds7);
277 DS7IOInit(ds);
278
279 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
280 if (header) {
281 memcpy(&ds->memory.ram[0x3FFE00 >> 2], header, 0x170);
282 DS7IOWrite32(ds, DS_REG_ROMCNT_LO, header->busTiming | 0x2700000);
283 // TODO: Error check
284 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
285 uint32_t base = header->arm7Base - DS_BASE_RAM;
286 uint32_t* basePointer = &ds->memory.ram[base >> 2];
287 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
288 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
289 }
290 cpu->gprs[12] = header->arm7Entry;
291 cpu->gprs[ARM_LR] = header->arm7Entry;
292 cpu->gprs[ARM_PC] = header->arm7Entry;
293 int currentCycles = 0;
294 ARM_WRITE_PC;
295
296 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
297 }
298}
299
300void DS9Reset(struct ARMCore* cpu) {
301 ARMSetPrivilegeMode(cpu, MODE_IRQ);
302 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
303 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
304 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
305 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
306 cpu->gprs[ARM_SP] = DS9_SP_BASE;
307
308 struct DS* ds = (struct DS*) cpu->master;
309 mTimingClear(&ds->ds9.timing);
310 CircleBufferInit(&ds->ds9.fifo, 64);
311 DSVideoReset(&ds->video);
312 DSDMAReset(&ds->ds9);
313 DS9IOInit(ds);
314
315 ds->activeCpu = cpu;
316 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
317 ds->cycleDrift = 0;
318 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
319
320 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
321 if (header) {
322 // TODO: Error check
323 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
324 uint32_t base = header->arm9Base - DS_BASE_RAM;
325 uint32_t* basePointer = &ds->memory.ram[base >> 2];
326 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
327 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
328 }
329 cpu->gprs[12] = header->arm9Entry;
330 cpu->gprs[ARM_LR] = header->arm9Entry;
331 cpu->gprs[ARM_PC] = header->arm9Entry;
332 int currentCycles = 0;
333 ARM_WRITE_PC;
334
335 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
336 }
337}
338
339static void DS7ProcessEvents(struct ARMCore* cpu) {
340 struct DS* ds = (struct DS*) cpu->master;
341 DSProcessEvents(&ds->ds7);
342}
343
344static void DS9ProcessEvents(struct ARMCore* cpu) {
345 struct DS* ds = (struct DS*) cpu->master;
346 DSProcessEvents(&ds->ds9);
347}
348
349static void DSProcessEvents(struct DSCommon* dscore) {
350 struct ARMCore* cpu = dscore->cpu;
351 struct DS* ds = dscore->p;
352 if (dscore->springIRQ && !cpu->cpsr.i) {
353 ARMRaiseIRQ(cpu);
354 dscore->springIRQ = 0;
355 }
356
357 int32_t nextEvent = cpu->nextEvent;
358 while (cpu->cycles >= nextEvent) {
359 int32_t cycles = cpu->cycles;
360
361 cpu->cycles = 0;
362 cpu->nextEvent = INT_MAX;
363
364#ifndef NDEBUG
365 if (cycles < 0) {
366 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
367 }
368#endif
369 nextEvent = cycles;
370 do {
371 nextEvent = mTimingTick(&dscore->timing, nextEvent);
372 } while (ds->cpuBlocked);
373
374 cpu->nextEvent = nextEvent;
375
376 if (ds->earlyExit) {
377 ds->earlyExit = false;
378 break;
379 }
380 if (cpu->halted) {
381 cpu->cycles = nextEvent;
382 }
383#ifndef NDEBUG
384 else if (nextEvent < 0) {
385 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
386 }
387#endif
388 }
389}
390
391void DSRunLoop(struct DS* ds) {
392 if (ds->activeCpu == ds->ds9.cpu) {
393 ARMv5RunLoop(ds->ds9.cpu);
394 } else {
395 ARMv4RunLoop(ds->ds7.cpu);
396 }
397}
398
399void DS7Step(struct DS* ds) {
400 while (ds->activeCpu == ds->ds9.cpu) {
401 ARMv5RunLoop(ds->ds9.cpu);
402 }
403 ARMv4Run(ds->ds7.cpu);
404}
405
406void DS9Step(struct DS* ds) {
407 while (ds->activeCpu == ds->ds7.cpu) {
408 ARMv4RunLoop(ds->ds7.cpu);
409 }
410 ARMv5Run(ds->ds9.cpu);
411}
412
413void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
414 ds->debugger = (struct ARMDebugger*) debugger->platform;
415 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
416 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
417 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
418 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
419}
420
421void DSDetachDebugger(struct DS* ds) {
422 ds->debugger = NULL;
423 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
424 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
425 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
426 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
427}
428
429bool DSLoadROM(struct DS* ds, struct VFile* vf) {
430 DSUnloadROM(ds);
431 ds->romVf = vf;
432 // TODO: error check
433 return true;
434}
435
436bool DSIsROM(struct VFile* vf) {
437 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
438 return false;
439 }
440 uint8_t signature[sizeof(DS_ROM_MAGIC)];
441 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
442 return false;
443 }
444 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
445}
446
447bool DSIsBIOS7(struct VFile* vf) {
448 size_t size = vf->size(vf);
449 void* data = NULL;
450 uint32_t crc;
451 if (size == DS7_SIZE_BIOS) {
452 data = vf->map(vf, size, MAP_READ);
453 }
454 if (!data) {
455 return false;
456 }
457 crc = doCrc32(data, size);
458 vf->unmap(vf, data, size);
459 return crc == DS7_BIOS_CHECKSUM;
460}
461
462bool DSIsBIOS9(struct VFile* vf) {
463 size_t size = vf->size(vf);
464 void* data = NULL;
465 uint32_t crc;
466 if (size == DS9_SIZE_BIOS) {
467 data = vf->map(vf, 0x1000, MAP_READ);
468 } else if (size == 0x1000) {
469 data = vf->map(vf, 0x1000, MAP_READ);
470 }
471 if (!data) {
472 return false;
473 }
474 crc = doCrc32(data, 0x1000);
475 vf->unmap(vf, data, 0x1000);
476 return crc == DS9_BIOS_CHECKSUM;
477}
478
479bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
480 size_t size = vf->size(vf);
481 void* data = NULL;
482 uint32_t crc;
483 if (size == DS7_SIZE_BIOS) {
484 data = vf->map(vf, size, MAP_READ);
485 } else if (size == 0x1000) {
486 data = calloc(DS9_SIZE_BIOS, 1);
487 vf->read(vf, data, size);
488 } else if (size == DS9_SIZE_BIOS) {
489 data = vf->map(vf, size, MAP_READ);
490 }
491 if (!data) {
492 return false;
493 }
494 crc = doCrc32(data, size);
495 if (crc == DS7_BIOS_CHECKSUM) {
496 ds->bios7Vf = vf;
497 ds->memory.bios7 = data;
498 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
499 } else if (crc == DS9_BIOS_CHECKSUM) {
500 ds->bios9Vf = vf;
501 ds->memory.bios9 = data;
502 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
503 } else {
504 mLOG(DS, WARN, "BIOS checksum incorrect");
505 vf->unmap(vf, data, size);
506 return false;
507 }
508 return true;
509}
510
511void DSGetGameCode(struct DS* ds, char* out) {
512 memset(out, 0, 8);
513 if (!ds->romVf) {
514 return;
515 }
516
517 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
518 // TODO: TWL-?
519 memcpy(out, "NTR-", 4);
520 memcpy(&out[4], &cart->id, 4);
521 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
522}
523
524void DSGetGameTitle(struct DS* ds, char* out) {
525 memset(out, 0, 12);
526 if (!ds->romVf) {
527 return;
528 }
529
530 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
531 memcpy(out, &cart->title, 12);
532 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
533}
534
535void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
536 struct DS* ds = (struct DS*) cpu->master;
537 if (ds->debugger) {
538 struct mDebuggerEntryInfo info = {
539 .address = _ARMPCAddress(cpu),
540 .opcode = opcode
541 };
542 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
543 }
544 // TODO: More sensible category?
545 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
546}
547
548void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
549 struct DS* ds = (struct DS*) cpu->master;
550 if (ds->debugger) {
551 struct mDebuggerEntryInfo info = {
552 .address = _ARMPCAddress(cpu),
553 .opcode = opcode
554 };
555 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
556 } else {
557 ARMRaiseUndefined(cpu);
558 }
559}
560
561void DSBreakpoint(struct ARMCore* cpu, int immediate) {
562 struct DS* ds = (struct DS*) cpu->master;
563 if (immediate >= CPU_COMPONENT_MAX) {
564 return;
565 }
566 switch (immediate) {
567 case CPU_COMPONENT_DEBUGGER:
568 if (ds->debugger) {
569 struct mDebuggerEntryInfo info = {
570 .address = _ARMPCAddress(cpu)
571 };
572 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
573 }
574 break;
575 default:
576 break;
577 }
578}
579
580void DS7TestIRQ(struct ARMCore* cpu) {
581 struct DS* ds = (struct DS*) cpu->master;
582 if (!ds->memory.io7[DS_REG_IME >> 1]) {
583 return;
584 }
585 uint32_t test = (ds->memory.io7[DS_REG_IE_LO >> 1] & ds->memory.io7[DS_REG_IF_LO >> 1]);
586 test |= (ds->memory.io7[DS_REG_IE_HI >> 1] & ds->memory.io7[DS_REG_IF_HI >> 1]) << 16;
587 if (test) {
588 ds->ds7.springIRQ = test;
589 cpu->nextEvent = cpu->cycles;
590 }
591}
592
593void DS9TestIRQ(struct ARMCore* cpu) {
594 struct DS* ds = (struct DS*) cpu->master;
595 if (!ds->memory.io9[DS_REG_IME >> 1]) {
596 return;
597 }
598 uint32_t test = (ds->memory.io9[DS_REG_IE_LO >> 1] & ds->memory.io9[DS_REG_IF_LO >> 1]);
599 test |= (ds->memory.io9[DS_REG_IE_HI >> 1] & ds->memory.io9[DS_REG_IF_HI >> 1]) << 16;
600 if (test) {
601 ds->ds9.springIRQ = test;
602 cpu->nextEvent = cpu->cycles;
603 }
604}
605
606static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
607 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
608}
609
610static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
611 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
612 switch (opcode2) {
613 case 0:
614 cpu->cp15.r2.d = value;
615 break;
616 case 1:
617 cpu->cp15.r2.i = value;
618 break;
619 default:
620 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
621 break;
622 }
623}
624
625static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
626 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
627 switch (opcode2) {
628 case 0:
629 cpu->cp15.r3.d = value;
630 break;
631 default:
632 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
633 break;
634 }
635}
636
637static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
638 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
639}
640
641static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
642 cpu->cp15.r6.region[crm] = value;
643 uint32_t base = ARMProtectionGetBase(value) << 12;
644 uint32_t size = 2 << ARMProtectionGetSize(value);
645 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
646}
647
648static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
649 switch (crm) {
650 case 0:
651 if (opcode2 == 4) {
652 ARMHalt(cpu);
653 return;
654 }
655 break;
656 }
657 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
658}
659
660static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
661 uint32_t base = ARMTCMControlGetBase(value) << 12;
662 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
663 struct DS* ds = (struct DS*) cpu->master;
664 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
665 switch (opcode2) {
666 case 0:
667 cpu->cp15.r9.d = value;
668 ds->memory.dtcmBase = base;
669 ds->memory.dtcmSize = size;
670 break;
671 case 1:
672 cpu->cp15.r9.i = value;
673 ds->memory.itcmSize = size;
674 break;
675 default:
676 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
677 break;
678 }
679}
680
681void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
682 switch (crn) {
683 default:
684 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
685 break;
686 case 0:
687 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
688 ARMRaiseUndefined(cpu);
689 break;
690 case 1:
691 _writeSysControl(cpu, crm, opcode2, value);
692 break;
693 case 2:
694 _writeCacheControl(cpu, crm, opcode2, value);
695 break;
696 case 3:
697 _writeWriteBufferControl(cpu, crm, opcode2, value);
698 break;
699 case 5:
700 _writeAccessControl(cpu, crm, opcode2, value);
701 break;
702 case 6:
703 _writeRegionConfiguration(cpu, crm, opcode2, value);
704 break;
705 case 7:
706 _writeCache(cpu, crm, opcode2, value);
707 break;
708 case 9:
709 _writeTCMControl(cpu, crm, opcode2, value);
710 break;
711 }
712}
713
714static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
715 switch (opcode2) {
716 case 0:
717 return cpu->cp15.r9.d;
718 case 1:
719 return cpu->cp15.r9.i;
720 default:
721 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
722 return 0;
723 }
724}
725
726uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
727 switch (crn) {
728 default:
729 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
730 return 0;
731 case 9:
732 return _readTCMControl(cpu, crm, opcode2);
733 }
734}
735
736void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
737 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
738 ARMRaiseIRQ(cpu);
739 }
740}
741void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
742 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
743 ARMRaiseIRQ(cpu);
744 }
745}
746
747void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
748 if (irq < 16) {
749 io[DS_REG_IF_LO >> 1] |= 1 << irq;
750 } else {
751 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
752 }
753
754 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
755 cpu->halted = 0;
756 if (io[DS_REG_IME >> 1]) {
757 ARMRaiseIRQ(cpu);
758 }
759 }
760}
761
762void DSFrameStarted(struct DS* ds) {
763 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
764 if (callbacks && callbacks->videoFrameStarted) {
765 callbacks->videoFrameStarted(callbacks->context);
766 }
767}
768
769void DSFrameEnded(struct DS* ds) {
770 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
771 if (callbacks && callbacks->videoFrameEnded) {
772 callbacks->videoFrameEnded(callbacks->context);
773 }
774}