src/arm/isa-thumb.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-thumb.h>
7
8#include <mgba/internal/arm/isa-inlines.h>
9#include <mgba/internal/arm/emitter-thumb.h>
10
11// Instruction definitions
12// Beware pre-processor insanity
13
14#define THUMB_ADDITION_S(M, N, D) \
15 cpu->cpsr.flags = 0; \
16 cpu->cpsr.n = ARM_SIGN(D); \
17 cpu->cpsr.z = !(D); \
18 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
19 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
20
21#define THUMB_SUBTRACTION_S(M, N, D) \
22 cpu->cpsr.flags = 0; \
23 cpu->cpsr.n = ARM_SIGN(D); \
24 cpu->cpsr.z = !(D); \
25 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
26 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
27
28#define THUMB_SUBTRACTION_CARRY_S(M, N, D, C) \
29 cpu->cpsr.flags = 0; \
30 cpu->cpsr.n = ARM_SIGN(D); \
31 cpu->cpsr.z = !(D); \
32 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
33 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
34
35#define THUMB_NEUTRAL_S(M, N, D) \
36 cpu->cpsr.n = ARM_SIGN(D); \
37 cpu->cpsr.z = !(D);
38
39#define THUMB_ADDITION(D, M, N) \
40 int n = N; \
41 int m = M; \
42 D = M + N; \
43 THUMB_ADDITION_S(m, n, D)
44
45#define THUMB_SUBTRACTION(D, M, N) \
46 int n = N; \
47 int m = M; \
48 D = M - N; \
49 THUMB_SUBTRACTION_S(m, n, D)
50
51#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activeSeqCycles16)
52
53#define THUMB_LOAD_POST_BODY \
54 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
55
56#define THUMB_STORE_POST_BODY \
57 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
58
59#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
60 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
61 int currentCycles = THUMB_PREFETCH_CYCLES; \
62 BODY; \
63 cpu->cycles += currentCycles; \
64 }
65
66#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
67 DEFINE_INSTRUCTION_THUMB(NAME, \
68 int immediate = (opcode >> 6) & 0x001F; \
69 int rd = opcode & 0x0007; \
70 int rm = (opcode >> 3) & 0x0007; \
71 BODY;)
72
73DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
74 if (!immediate) {
75 cpu->gprs[rd] = cpu->gprs[rm];
76 } else {
77 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
78 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
79 }
80 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
81
82DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
83 if (!immediate) {
84 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
85 cpu->gprs[rd] = 0;
86 } else {
87 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
89 }
90 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
91
92DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
93 if (!immediate) {
94 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
95 if (cpu->cpsr.c) {
96 cpu->gprs[rd] = 0xFFFFFFFF;
97 } else {
98 cpu->gprs[rd] = 0;
99 }
100 } else {
101 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
102 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
103 }
104 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
105
106DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, ¤tCycles); THUMB_LOAD_POST_BODY;)
107DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rm] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
108DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rm] + immediate * 2, ¤tCycles); THUMB_LOAD_POST_BODY;)
109DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
110DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
111DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
112
113#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
114 DEFINE_INSTRUCTION_THUMB(NAME, \
115 int rm = (opcode >> 6) & 0x0007; \
116 int rd = opcode & 0x0007; \
117 int rn = (opcode >> 3) & 0x0007; \
118 BODY;)
119
120DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD3, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
121DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB3, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
122
123#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
124 DEFINE_INSTRUCTION_THUMB(NAME, \
125 int immediate = (opcode >> 6) & 0x0007; \
126 int rd = opcode & 0x0007; \
127 int rn = (opcode >> 3) & 0x0007; \
128 BODY;)
129
130DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD1, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
131DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB1, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
132
133#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
134 DEFINE_INSTRUCTION_THUMB(NAME, \
135 int rd = (opcode >> 8) & 0x0007; \
136 int immediate = opcode & 0x00FF; \
137 BODY;)
138
139DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
140DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
141DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
142DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
143
144#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
145 DEFINE_INSTRUCTION_THUMB(NAME, \
146 int rd = opcode & 0x0007; \
147 int rn = (opcode >> 3) & 0x0007; \
148 BODY;)
149
150DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
151DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
152DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
153 int rs = cpu->gprs[rn] & 0xFF;
154 if (rs) {
155 if (rs < 32) {
156 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
157 cpu->gprs[rd] <<= rs;
158 } else {
159 if (rs > 32) {
160 cpu->cpsr.c = 0;
161 } else {
162 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
163 }
164 cpu->gprs[rd] = 0;
165 }
166 }
167 ++currentCycles;
168 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
169
170DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
171 int rs = cpu->gprs[rn] & 0xFF;
172 if (rs) {
173 if (rs < 32) {
174 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
175 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
176 } else {
177 if (rs > 32) {
178 cpu->cpsr.c = 0;
179 } else {
180 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
181 }
182 cpu->gprs[rd] = 0;
183 }
184 }
185 ++currentCycles;
186 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
187
188DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
189 int rs = cpu->gprs[rn] & 0xFF;
190 if (rs) {
191 if (rs < 32) {
192 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
193 cpu->gprs[rd] >>= rs;
194 } else {
195 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
196 if (cpu->cpsr.c) {
197 cpu->gprs[rd] = 0xFFFFFFFF;
198 } else {
199 cpu->gprs[rd] = 0;
200 }
201 }
202 }
203 ++currentCycles;
204 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
205
206DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
207 int n = cpu->gprs[rn];
208 int d = cpu->gprs[rd];
209 cpu->gprs[rd] = d + n + cpu->cpsr.c;
210 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
211
212DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
213 int n = cpu->gprs[rn];
214 int d = cpu->gprs[rd];
215 cpu->gprs[rd] = d - n - !cpu->cpsr.c;
216 THUMB_SUBTRACTION_CARRY_S(d, n, cpu->gprs[rd], !cpu->cpsr.c);)
217
218DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
219 int rs = cpu->gprs[rn] & 0xFF;
220 if (rs) {
221 int r4 = rs & 0x1F;
222 if (r4 > 0) {
223 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
224 cpu->gprs[rd] = ROR(cpu->gprs[rd], r4);
225 } else {
226 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
227 }
228 }
229 ++currentCycles;
230 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
231DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
232DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
233DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
234DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
235DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
236DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rd]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]); currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16)
237DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
238DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
239
240#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
241 DEFINE_INSTRUCTION_THUMB(NAME, \
242 int rd = (opcode & 0x0007) | H1; \
243 int rm = ((opcode >> 3) & 0x0007) | H2; \
244 BODY;)
245
246#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
247 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
248 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
249 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
250 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
251
252DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
253 cpu->gprs[rd] += cpu->gprs[rm];
254 if (rd == ARM_PC) {
255 currentCycles += ThumbWritePC(cpu);
256 })
257
258DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
259DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
260 cpu->gprs[rd] = cpu->gprs[rm];
261 if (rd == ARM_PC) {
262 currentCycles += ThumbWritePC(cpu);
263 })
264
265#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
266 DEFINE_INSTRUCTION_THUMB(NAME, \
267 int rd = (opcode >> 8) & 0x0007; \
268 int immediate = (opcode & 0x00FF) << 2; \
269 BODY;)
270
271DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
272DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
273DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
274
275DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
276DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
277
278#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
279 DEFINE_INSTRUCTION_THUMB(NAME, \
280 int rm = (opcode >> 6) & 0x0007; \
281 int rd = opcode & 0x0007; \
282 int rn = (opcode >> 3) & 0x0007; \
283 BODY;)
284
285DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
286DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
287DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
288DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles)); THUMB_LOAD_POST_BODY;)
289DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, rm = cpu->gprs[rn] + cpu->gprs[rm]; cpu->gprs[rd] = rm & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, rm, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, rm, ¤tCycles)); THUMB_LOAD_POST_BODY;)
290DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
291DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
292DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
293
294#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
295 DEFINE_INSTRUCTION_THUMB(NAME, \
296 int rn = RN; \
297 UNUSED(rn); \
298 int rs = opcode & 0xFF; \
299 int32_t address = cpu->gprs[RN]; \
300 PRE_BODY; \
301 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
302 WRITEBACK;)
303
304DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
305 (opcode >> 8) & 0x0007,
306 load,
307 IA,
308 ,
309 THUMB_LOAD_POST_BODY;
310 if (!rs) {
311 currentCycles += ThumbWritePC(cpu);
312 }
313 if (!((1 << rn) & rs)) {
314 cpu->gprs[rn] = address;
315 })
316
317DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
318 (opcode >> 8) & 0x0007,
319 store,
320 IA,
321 ,
322 THUMB_STORE_POST_BODY;
323 cpu->gprs[rn] = address;)
324
325#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
326 DEFINE_INSTRUCTION_THUMB(B ## COND, \
327 if (ARM_COND_ ## COND) { \
328 int8_t immediate = opcode; \
329 cpu->gprs[ARM_PC] += (int32_t) immediate << 1; \
330 currentCycles += ThumbWritePC(cpu); \
331 })
332
333DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
334DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
335DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
336DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
337DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
338DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
339DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
340DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
341DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
342DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
343DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
344DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
345DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
346DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
347
348DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
349DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
350
351DEFINE_LOAD_STORE_MULTIPLE_THUMB(POP,
352 ARM_SP,
353 load,
354 IA,
355 ,
356 THUMB_LOAD_POST_BODY;
357 cpu->gprs[ARM_SP] = address)
358
359DEFINE_LOAD_STORE_MULTIPLE_THUMB(POPR,
360 ARM_SP,
361 load,
362 IA,
363 rs |= 1 << ARM_PC,
364 THUMB_LOAD_POST_BODY;
365 cpu->gprs[ARM_SP] = address;
366 currentCycles += ThumbWritePC(cpu);)
367
368DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSH,
369 ARM_SP,
370 store,
371 DB,
372 ,
373 THUMB_STORE_POST_BODY;
374 cpu->gprs[ARM_SP] = address)
375
376DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSHR,
377 ARM_SP,
378 store,
379 DB,
380 rs |= 1 << ARM_LR,
381 THUMB_STORE_POST_BODY;
382 cpu->gprs[ARM_SP] = address)
383
384DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
385DEFINE_INSTRUCTION_THUMB(BKPT, cpu->irqh.bkpt16(cpu, opcode & 0xFF);)
386DEFINE_INSTRUCTION_THUMB(B,
387 int16_t immediate = (opcode & 0x07FF) << 5;
388 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
389 currentCycles += ThumbWritePC(cpu);)
390
391DEFINE_INSTRUCTION_THUMB(BL1,
392 int16_t immediate = (opcode & 0x07FF) << 5;
393 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
394
395DEFINE_INSTRUCTION_THUMB(BL2,
396 uint16_t immediate = (opcode & 0x07FF) << 1;
397 uint32_t pc = cpu->gprs[ARM_PC];
398 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
399 cpu->gprs[ARM_LR] = pc - 1;
400 currentCycles += ThumbWritePC(cpu);)
401
402DEFINE_INSTRUCTION_THUMB(BX,
403 int rm = (opcode >> 3) & 0xF;
404 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
405 int misalign = 0;
406 if (rm == ARM_PC) {
407 misalign = cpu->gprs[rm] & 0x00000002;
408 }
409 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
410 if (cpu->executionMode == MODE_THUMB) {
411 currentCycles += ThumbWritePC(cpu);
412 } else {
413 currentCycles += ARMWritePC(cpu);
414 })
415
416DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
417
418const ThumbInstruction _thumbTable[0x400] = {
419 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
420};