include/mgba/internal/gb/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GB_SERIALIZE_H
7#define GB_SERIALIZE_H
8
9#include <mgba-util/common.h>
10
11CXX_GUARD_START
12
13#include <mgba/core/core.h>
14#include <mgba/internal/gb/gb.h>
15
16extern const uint32_t GB_SAVESTATE_MAGIC;
17extern const uint32_t GB_SAVESTATE_VERSION;
18
19mLOG_DECLARE_CATEGORY(GB_STATE);
20
21/* Savestate format:
22 * 0x00000 - 0x00003: Version Magic (0x01000002)
23 * 0x00004 - 0x00007: ROM CRC32
24 * 0x00008: Game Boy model
25 * 0x00009 - 0x0000B: Reserved (leave zero)
26 * 0x0000C - 0x0000F: Master cycles
27 * 0x00010 - 0x0001F: Game title/code (e.g. PM_CRYSTALBYTE)
28 * 0x00020 - 0x00047: CPU state:
29 * | 0x00020: A register
30 * | 0x00021: F register
31 * | 0x00022: B register
32 * | 0x00023: C register
33 * | 0x00024: D register
34 * | 0x00025: E register
35 * | 0x00026: H register
36 * | 0x00027: L register
37 * | 0x00028 - 0x00029: SP register
38 * | 0x0002A - 0x0002B: PC register
39 * | 0x0002C - 0x0002F: Cycles since last event
40 * | 0x00030 - 0x00033: Cycles until next event
41 * | 0x00034 - 0x00035: Reserved (current instruction)
42 * | 0x00036 - 0x00037: Index address
43 * | 0x00038: Bus value
44 * | 0x00039: Execution state
45 * | 0x0003A - 0x0003B: Reserved
46 * | 0x0003C - 0x0003F: EI pending cycles
47 * | 0x00040 - 0x00043: Reserved (DI pending cycles)
48 * | 0x00044 - 0x00047: Flags
49 * | bit 0: Is condition met?
50 * | bit 1: Is IRQ pending?
51 * | bit 2: Double speed
52 * | bit 3: Is EI pending?
53 * | bits 4 - 31: Reserved
54 * 0x00048 - 0x0005B: Audio channel 1/framer state
55 * | 0x00048 - 0x0004B: Envelepe timing
56 * | bits 0 - 6: Remaining length
57 * | bits 7 - 9: Next step
58 * | bits 10 - 20: Shadow frequency register
59 * | bits 21 - 31: Reserved
60 * | 0x0004C - 0x0004F: Next frame
61 * | 0x00050 - 0x00053: Next channel 3 fade
62 * | 0x00054 - 0x00057: Reserved
63 * | 0x00058 - 0x0005B: Next event
64 * 0x0005C - 0x0006B: Audio channel 2 state
65 * | 0x0005C - 0x0005F: Envelepe timing
66 * | bits 0 - 2: Remaining length
67 * | bits 3 - 5: Next step
68 * | bits 6 - 31: Reserved
69 * | 0x00060 - 0x00067: Reserved
70 * | 0x00068 - 0x0006B: Next event
71 * 0x0006C - 0x00093: Audio channel 3 state
72 * | 0x0006C - 0x0008B: Wave banks
73 * | 0x0008C - 0x0008D: Remaining length
74 * | 0x0008E - 0x0008F: Reserved
75 * | 0x00090 - 0x00093: Next event
76 * 0x00094 - 0x000A3: Audio channel 4 state
77 * | 0x00094 - 0x00097: Linear feedback shift register state
78 * | 0x00098 - 0x0009B: Envelepe timing
79 * | bits 0 - 2: Remaining length
80 * | bits 3 - 5: Next step
81 * | bits 6 - 31: Reserved
82 * | 0x00098 - 0x0009F: Reserved
83 * | 0x000A0 - 0x000A3: Next event
84 * 0x000A4 - 0x000B7: Audio miscellaneous state
85 * | TODO: Fix this, they're in big-endian order, but field is little-endian
86 * | 0x000A4: Channel 1 envelope state
87 * | bits 0 - 3: Current volume
88 * | bits 4 - 5: Is dead?
89 * | bit 6: Is high?
90 * | 0x000A5: Channel 2 envelope state
91 * | bits 0 - 3: Current volume
92 * | bits 4 - 5: Is dead?
93 * | bit 6: Is high?
94* | bits 7: Reserved
95 * | 0x000A6: Channel 4 envelope state
96 * | bits 0 - 3: Current volume
97 * | bits 4 - 5: Is dead?
98 * | bit 6: Is high?
99* | bits 7: Reserved
100 * | 0x000A7: Miscellaneous audio flags
101 * | bits 0 - 3: Current frame
102 * | bit 4: Is channel 1 sweep enabled?
103 * | bit 5: Has channel 1 sweep occurred?
104 * | bit 6: Is channel 3's memory readable?
105 * | bit 7: Reserved
106 * | 0x000A8 - 0x000AB: Left capacitor charge
107 * | 0x000AC - 0x000AF: Right capacitor charge
108 * | 0x000B0 - 0x000B3: Next sample
109 * 0x000B4 - 0x000153: Video state
110 * | 0x000B4 - 0x000B5: Current x
111 * | 0x000B6 - 0x000B7: Current y (ly)
112 * | 0x000B8 - 0x000BB: Next frame
113 * | 0x000BC - 0x000BF: Reserved
114 * | 0x000C0 - 0x000C3: Next mode
115 * | 0x000C4 - 0x000C7: Dot cycle counter
116 * | 0x000C8 - 0x000CB: Frame counter
117 * | 0x000CC: Current VRAM bank
118 * | 0x000CD: Palette flags
119 * | bit 0: BCP increment
120 * | bit 1: OCP increment
121 * | bits 2 - 3: Mode
122 * | bits 4 - 7: Reserved
123 * | 0x000CE - 0x000CF: Reserved
124 * | 0x000D0 - 0x000D1: BCP index
125 * | 0x000D1 - 0x000D3: OCP index
126 * | 0x000D4 - 0x00153: Palette entries
127 * 0x00154 - 0x000167: Timer state
128 * | 0x00154 - 0x00157: Next event
129 * | 0x00158 - 0x0015B: Next IRQ
130 * | 0x0015C - 0x0015F: Next DIV
131 * | 0x00160 - 0x00163: Inernal DIV
132 * | 0x00164: TIMA period
133 * | 0x00165: Flags
134 * | bit 0: Is IRQ pending?
135 * | 0x00166 - 0x00167: Reserved
136 * 0x000168 - 0x000197: Memory state
137 * | 0x00168 - 0x00169: Current ROM bank
138 * | 0x0016A: Current WRAM bank
139 * | 0x0016B: Current SRAM bank
140 * | 0x0016C - 0x0016F: Next DMA
141 * | 0x00170 - 0x00171: Next DMA source
142 * | 0x00172 - 0x00173: Next DMA destination
143 * | 0x00174 - 0x00177: Next HDMA
144 * | 0x00178 - 0x00179: Next HDMA source
145 * | 0x0017A - 0x0017B: Next HDMA destination
146 * | 0x0017C - 0x0017D: HDMA remaining
147 * | 0x0017E: DMA remaining
148 * | 0x0017F - 0x00183: RTC registers
149 * | 0x00184 - 0x00193: MBC state
150 * | 0x00194 - 0x00195: Flags
151 * | bit 0: SRAM accessable
152 * | bit 1: RTC accessible
153 * | bit 2: RTC latched
154 * | bit 3: IME
155 * | bit 4: Is HDMA active?
156 * | bits 5 - 7: Active RTC register
157 * | 0x00196 - 0x00197: Reserved (leave zero)
158 * 0x00198 - 0x0025F: Reserved (leave zero)
159 * 0x00260 - 0x002FF: OAM
160 * 0x00300 - 0x0037F: I/O memory
161 * 0x00380 - 0x003FE: HRAM
162 * 0x003FF: Interrupts enabled
163 * 0x00400 - 0x043FF: VRAM
164 * 0x04400 - 0x0C3FF: WRAM
165 * 0x0C400 - 0x0C77F: Reserved
166 * 0x0C780 - 0x117FF: Super Game Boy
167 * | 0x0C780 - 0x0C7D9: Current attributes
168 * | 0x0C7DA: Current command
169 * | 0x0C7DB: Current bit count
170 * | 0x0C7DC - 0x0C7DF: Flags
171 * | bits 0 - 1: Current P1 bits
172 * | bits 2 - 3: Current render mode
173 * | bit 4: Is a mode event not scheduled?
174 * | bit 5: Is a frame event not scheduled?
175 * | bits 6 - 31: Reserved (leave 0)
176 * | 0x0C7E0 - 0x0C7EF: Current packet
177 * | 0x0C7F0 - 0x0C7FF: Reserved
178 * | 0x0C800 - 0x0E7FF: Character VRAM
179 * | 0x0E800 - 0x0F7FF: Tile map VRAM
180 * | 0x0F800 - 0x107FF: Palette VRAM
181 * | 0x10800 - 0x117FF: Attribute file
182 * Total size: 0x11800 (71,680) bytes
183*/
184
185DECL_BITFIELD(GBSerializedAudioFlags, uint32_t);
186DECL_BITS(GBSerializedAudioFlags, Ch1Volume, 0, 4);
187DECL_BITS(GBSerializedAudioFlags, Ch1Dead, 4, 2);
188DECL_BIT(GBSerializedAudioFlags, Ch1Hi, 6);
189DECL_BITS(GBSerializedAudioFlags, Ch2Volume, 8, 4);
190DECL_BITS(GBSerializedAudioFlags, Ch2Dead, 12, 2);
191DECL_BIT(GBSerializedAudioFlags, Ch2Hi, 14);
192DECL_BITS(GBSerializedAudioFlags, Ch4Volume, 16, 4);
193DECL_BITS(GBSerializedAudioFlags, Ch4Dead, 20, 2);
194DECL_BITS(GBSerializedAudioFlags, Frame, 22, 3);
195DECL_BIT(GBSerializedAudioFlags, Ch1SweepEnabled, 25);
196DECL_BIT(GBSerializedAudioFlags, Ch1SweepOccurred, 26);
197DECL_BIT(GBSerializedAudioFlags, Ch3Readable, 27);
198
199DECL_BITFIELD(GBSerializedAudioEnvelope, uint32_t);
200DECL_BITS(GBSerializedAudioEnvelope, Length, 0, 7);
201DECL_BITS(GBSerializedAudioEnvelope, NextStep, 7, 3);
202DECL_BITS(GBSerializedAudioEnvelope, Frequency, 10, 11);
203
204struct GBSerializedPSGState {
205 struct {
206 GBSerializedAudioEnvelope envelope;
207 int32_t nextFrame;
208 int32_t nextCh3Fade;
209 int32_t reserved;
210 uint32_t nextEvent;
211 } ch1;
212 struct {
213 GBSerializedAudioEnvelope envelope;
214 int32_t reserved[2];
215 int32_t nextEvent;
216 } ch2;
217 struct {
218 uint32_t wavebanks[8];
219 int16_t length;
220 int16_t reserved;
221 uint32_t nextEvent;
222 } ch3;
223 struct {
224 int32_t lfsr;
225 GBSerializedAudioEnvelope envelope;
226 int32_t reserved;
227 uint32_t nextEvent;
228 } ch4;
229};
230
231DECL_BITFIELD(GBSerializedCpuFlags, uint32_t);
232DECL_BIT(GBSerializedCpuFlags, Condition, 0);
233DECL_BIT(GBSerializedCpuFlags, IrqPending, 1);
234DECL_BIT(GBSerializedCpuFlags, DoubleSpeed, 2);
235DECL_BIT(GBSerializedCpuFlags, EiPending, 3);
236
237DECL_BITFIELD(GBSerializedTimerFlags, uint8_t);
238DECL_BIT(GBSerializedTimerFlags, IrqPending, 0);
239
240DECL_BITFIELD(GBSerializedVideoFlags, uint8_t);
241DECL_BIT(GBSerializedVideoFlags, BcpIncrement, 0);
242DECL_BIT(GBSerializedVideoFlags, OcpIncrement, 1);
243DECL_BITS(GBSerializedVideoFlags, Mode, 2, 2);
244DECL_BIT(GBSerializedVideoFlags, NotModeEventScheduled, 4);
245DECL_BIT(GBSerializedVideoFlags, NotFrameEventScheduled, 5);
246
247DECL_BITFIELD(GBSerializedMBC7Flags, uint8_t);
248DECL_BITS(GBSerializedMBC7Flags, Command, 0, 2);
249DECL_BIT(GBSerializedMBC7Flags, Writable, 2);
250
251DECL_BITFIELD(GBSerializedMemoryFlags, uint16_t);
252DECL_BIT(GBSerializedMemoryFlags, SramAccess, 0);
253DECL_BIT(GBSerializedMemoryFlags, RtcAccess, 1);
254DECL_BIT(GBSerializedMemoryFlags, RtcLatched, 2);
255DECL_BIT(GBSerializedMemoryFlags, Ime, 3);
256DECL_BIT(GBSerializedMemoryFlags, IsHdma, 4);
257DECL_BITS(GBSerializedMemoryFlags, ActiveRtcReg, 5, 3);
258
259DECL_BITFIELD(GBSerializedSGBFlags, uint32_t);
260DECL_BITS(GBSerializedSGBFlags, P1Bits, 0, 2);
261DECL_BITS(GBSerializedSGBFlags, RenderMode, 2, 2);
262DECL_BITS(GBSerializedSGBFlags, BufferIndex, 4, 3);
263DECL_BITS(GBSerializedSGBFlags, CurrentController, 7, 2);
264DECL_BITS(GBSerializedSGBFlags, ReqControllers, 9, 2);
265
266#pragma pack(push, 1)
267struct GBSerializedState {
268 uint32_t versionMagic;
269 uint32_t romCrc32;
270 uint8_t model;
271 uint8_t reservedHeader[3];
272 uint32_t masterCycles;
273
274 char title[16];
275
276 struct {
277 uint8_t a;
278 uint8_t f;
279 uint8_t b;
280 uint8_t c;
281 uint8_t d;
282 uint8_t e;
283 uint8_t h;
284 uint8_t l;
285 uint16_t sp;
286 uint16_t pc;
287
288 int32_t cycles;
289 int32_t nextEvent;
290
291 uint16_t reservedInstruction;
292 uint16_t index;
293 uint8_t bus;
294 uint8_t executionState;
295
296 uint16_t reserved;
297
298 uint32_t eiPending;
299 int32_t reservedDiPending;
300 GBSerializedCpuFlags flags;
301 } cpu;
302
303 struct {
304 struct GBSerializedPSGState psg;
305 GBSerializedAudioFlags flags;
306 int32_t capLeft;
307 int32_t capRight;
308 uint32_t nextSample;
309 } audio;
310
311 struct {
312 int16_t x;
313 int16_t ly;
314 uint32_t nextFrame;
315 uint32_t reserved;
316 uint32_t nextMode;
317 int32_t dotCounter;
318 int32_t frameCounter;
319
320 uint8_t vramCurrentBank;
321 GBSerializedVideoFlags flags;
322 uint16_t reserved2;
323
324 uint16_t bcpIndex;
325 uint16_t ocpIndex;
326
327 uint16_t palette[64];
328 } video;
329
330 struct {
331 uint32_t nextEvent;
332 uint32_t nextIRQ;
333
334 uint32_t nextDiv;
335 uint32_t internalDiv;
336 uint8_t timaPeriod;
337 GBSerializedTimerFlags flags;
338 uint16_t reserved;
339 } timer;
340
341 struct {
342 uint16_t currentBank;
343 uint8_t wramCurrentBank;
344 uint8_t sramCurrentBank;
345
346 uint32_t dmaNext;
347 uint16_t dmaSource;
348 uint16_t dmaDest;
349
350 uint32_t hdmaNext;
351 uint16_t hdmaSource;
352 uint16_t hdmaDest;
353
354 uint16_t hdmaRemaining;
355 uint8_t dmaRemaining;
356 uint8_t rtcRegs[5];
357
358 union {
359 struct {
360 uint8_t mode;
361 uint8_t multicartStride;
362 } mbc1;
363 struct {
364 uint64_t lastLatch;
365 } rtc;
366 struct {
367 uint8_t state;
368 GBMBC7Field eeprom;
369 uint8_t address;
370 uint8_t access;
371 uint8_t latch;
372 uint8_t srBits;
373 uint16_t sr;
374 uint32_t writable;
375 } mbc7;
376 struct {
377 uint8_t locked;
378 uint8_t bank0;
379 } mmm01;
380 struct {
381 uint8_t reserved[16];
382 } padding;
383 };
384
385 GBSerializedMemoryFlags flags;
386 uint16_t reserved;
387 } memory;
388
389 uint32_t reserved[50];
390
391 uint8_t oam[GB_SIZE_OAM];
392
393 uint8_t io[GB_SIZE_IO];
394 uint8_t hram[GB_SIZE_HRAM];
395 uint8_t ie;
396
397 uint8_t vram[GB_SIZE_VRAM];
398 uint8_t wram[GB_SIZE_WORKING_RAM];
399
400 uint32_t reserved2[0xC4];
401
402 struct {
403 uint8_t attributes[90];
404 uint8_t command;
405 uint8_t bits;
406 GBSerializedSGBFlags flags;
407 uint8_t inProgressPacket[16];
408 uint8_t packet[128];
409 uint8_t charRam[SGB_SIZE_CHAR_RAM];
410 uint8_t mapRam[SGB_SIZE_MAP_RAM];
411 uint8_t palRam[SGB_SIZE_PAL_RAM];
412 uint8_t atfRam[SGB_SIZE_ATF_RAM];
413 } sgb;
414};
415#pragma pack(pop)
416
417bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state);
418void GBSerialize(struct GB* gb, struct GBSerializedState* state);
419
420CXX_GUARD_END
421
422#endif