1#ifndef ISA_INLINES_H
 2#define ISA_INLINES_H
 3
 4#define UNUSED(V) (void)(V)
 5
 6#define DO_8(DIRECTIVE) \
 7	DIRECTIVE, \
 8	DIRECTIVE, \
 9	DIRECTIVE, \
10	DIRECTIVE, \
11	DIRECTIVE, \
12	DIRECTIVE, \
13	DIRECTIVE, \
14	DIRECTIVE
15
16#define DO_256(DIRECTIVE) \
17	DO_8(DO_8(DIRECTIVE)), \
18	DO_8(DO_8(DIRECTIVE)), \
19	DO_8(DO_8(DIRECTIVE)), \
20	DO_8(DO_8(DIRECTIVE))
21
22#define DO_INTERLACE(LEFT, RIGHT) \
23	LEFT, \
24	RIGHT
25
26#define ARM_COND_EQ (cpu->cpsr.z)
27#define ARM_COND_NE (!cpu->cpsr.z)
28#define ARM_COND_CS (cpu->cpsr.c)
29#define ARM_COND_CC (!cpu->cpsr.c)
30#define ARM_COND_MI (cpu->cpsr.n)
31#define ARM_COND_PL (!cpu->cpsr.n)
32#define ARM_COND_VS (cpu->cpsr.v)
33#define ARM_COND_VC (!cpu->cpsr.v)
34#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
35#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
36#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
37#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
38#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
39#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
40#define ARM_COND_AL 1
41
42#define ARM_SIGN(I) ((I) >> 31)
43#define ARM_ROR(I, ROTATE) (((I) >> ROTATE) | (I << (32 - ROTATE)))
44
45#define ARM_CARRY_FROM(M, N, D) ((ARM_SIGN((M) | (N))) && !(ARM_SIGN(D)))
46#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
47#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
48#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
49
50static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
51	return mode != MODE_SYSTEM && mode != MODE_USER;
52}
53
54static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
55	if (executionMode == cpu->executionMode) {
56		return;
57	}
58
59	cpu->executionMode = executionMode;
60	switch (executionMode) {
61	case MODE_ARM:
62		cpu->cpsr.t = 0;
63		break;
64	case MODE_THUMB:
65		cpu->cpsr.t = 1;
66	}
67}
68
69static inline void _ARMReadCPSR(struct ARMCore* cpu) {
70	_ARMSetMode(cpu, cpu->cpsr.t);
71	ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
72}
73
74#endif