src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value);
39
40static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
41static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
42static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
43static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
44
45static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
46
47static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
48static void _GBPocketCamCapture(struct GBMemory*);
49
50void GBMBCSwitchBank(struct GB* gb, int bank) {
51 size_t bankStart = bank * GB_SIZE_CART_BANK0;
52 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
53 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
54 bankStart &= (gb->memory.romSize - 1);
55 bank = bankStart / GB_SIZE_CART_BANK0;
56 }
57 gb->memory.romBank = &gb->memory.rom[bankStart];
58 gb->memory.currentBank = bank;
59 if (gb->cpu->pc < GB_BASE_VRAM) {
60 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
61 }
62}
63
64void GBMBCSwitchBank0(struct GB* gb, int bank) {
65 size_t bankStart = bank * GB_SIZE_CART_BANK0;
66 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
67 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
68 bankStart &= (gb->memory.romSize - 1);
69 }
70 gb->memory.romBase = &gb->memory.rom[bankStart];
71 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
72 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
73 }
74}
75
76void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
77 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
78 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
79 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
80 bankStart &= (gb->memory.romSize - 1);
81 bank = bankStart / GB_SIZE_CART_HALFBANK;
82 if (!bank) {
83 ++bank;
84 }
85 }
86 if (!half) {
87 gb->memory.romBank = &gb->memory.rom[bankStart];
88 gb->memory.currentBank = bank;
89 } else {
90 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
91 gb->memory.mbcState.mbc6.currentBank1 = bank;
92 }
93 if (gb->cpu->pc < GB_BASE_VRAM) {
94 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
95 }
96}
97
98static bool _isMulticart(const uint8_t* mem) {
99 bool success;
100 struct VFile* vf;
101
102 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
103 success = GBIsROM(vf);
104 vf->close(vf);
105
106 if (!success) {
107 return false;
108 }
109
110 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
111 success = GBIsROM(vf);
112 vf->close(vf);
113
114 if (!success) {
115 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
116 success = GBIsROM(vf);
117 vf->close(vf);
118 }
119
120 return success;
121}
122
123static bool _isWisdomTree(const uint8_t* mem) {
124 int i;
125 for (i = 0x134; i < 0x14C; i += 4) {
126 if (*(uint32_t*) &mem[i] != 0) {
127 return false;
128 }
129 }
130 for (i = 0xF0; i < 0x100; i += 4) {
131 if (*(uint32_t*) &mem[i] != 0) {
132 return false;
133 }
134 }
135 if (mem[0x14D] != 0xE7) {
136 return false;
137 }
138 return true;
139}
140
141void GBMBCSwitchSramBank(struct GB* gb, int bank) {
142 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
143 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
144 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
145 bankStart &= (gb->sramSize - 1);
146 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
147 }
148 gb->memory.sramBank = &gb->memory.sram[bankStart];
149 gb->memory.sramCurrentBank = bank;
150}
151
152void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
153 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
154 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
155 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
156 bankStart &= (gb->sramSize - 1);
157 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
158 }
159 if (!half) {
160 gb->memory.sramBank = &gb->memory.sram[bankStart];
161 gb->memory.sramCurrentBank = bank;
162 } else {
163 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
164 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
165 }
166}
167
168void GBMBCInit(struct GB* gb) {
169 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
170 if (gb->memory.rom) {
171 if (gb->memory.romSize >= 0x8000) {
172 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
173 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
174 cart = cartFooter;
175 }
176 }
177 switch (cart->ramSize) {
178 case 0:
179 gb->sramSize = 0;
180 break;
181 case 1:
182 gb->sramSize = 0x800;
183 break;
184 default:
185 case 2:
186 gb->sramSize = 0x2000;
187 break;
188 case 3:
189 gb->sramSize = 0x8000;
190 break;
191 case 4:
192 gb->sramSize = 0x20000;
193 break;
194 case 5:
195 gb->sramSize = 0x10000;
196 break;
197 }
198
199 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
200 switch (cart->type) {
201 case 0:
202 if (_isWisdomTree(gb->memory.rom)) {
203 gb->memory.mbcType = GB_UNL_WISDOM_TREE;
204 break;
205 }
206 // Fall through
207 case 8:
208 case 9:
209 gb->memory.mbcType = GB_MBC_NONE;
210 break;
211 case 1:
212 case 2:
213 case 3:
214 gb->memory.mbcType = GB_MBC1;
215 break;
216 case 5:
217 case 6:
218 gb->memory.mbcType = GB_MBC2;
219 break;
220 case 0x0B:
221 case 0x0C:
222 case 0x0D:
223 gb->memory.mbcType = GB_MMM01;
224 break;
225 case 0x0F:
226 case 0x10:
227 gb->memory.mbcType = GB_MBC3_RTC;
228 break;
229 case 0x11:
230 case 0x12:
231 case 0x13:
232 gb->memory.mbcType = GB_MBC3;
233 break;
234 default:
235 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
236 // Fall through
237 case 0x19:
238 case 0x1A:
239 case 0x1B:
240 gb->memory.mbcType = GB_MBC5;
241 break;
242 case 0x1C:
243 case 0x1D:
244 case 0x1E:
245 gb->memory.mbcType = GB_MBC5_RUMBLE;
246 break;
247 case 0x20:
248 gb->memory.mbcType = GB_MBC6;
249 break;
250 case 0x22:
251 gb->memory.mbcType = GB_MBC7;
252 break;
253 case 0xFC:
254 gb->memory.mbcType = GB_POCKETCAM;
255 break;
256 case 0xFD:
257 gb->memory.mbcType = GB_TAMA5;
258 break;
259 case 0xFE:
260 gb->memory.mbcType = GB_HuC3;
261 break;
262 case 0xFF:
263 gb->memory.mbcType = GB_HuC1;
264 break;
265 }
266 }
267 } else {
268 gb->memory.mbcType = GB_MBC_NONE;
269 }
270 gb->memory.mbcRead = NULL;
271 switch (gb->memory.mbcType) {
272 case GB_MBC_NONE:
273 gb->memory.mbcWrite = _GBMBCNone;
274 break;
275 case GB_MBC1:
276 gb->memory.mbcWrite = _GBMBC1;
277 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
278 gb->memory.mbcState.mbc1.multicartStride = 4;
279 } else {
280 gb->memory.mbcState.mbc1.multicartStride = 5;
281 }
282 break;
283 case GB_MBC2:
284 gb->memory.mbcWrite = _GBMBC2;
285 gb->memory.mbcRead = _GBMBC2Read;
286 gb->sramSize = 0x100;
287 break;
288 case GB_MBC3:
289 gb->memory.mbcWrite = _GBMBC3;
290 break;
291 default:
292 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
293 // Fall through
294 case GB_MBC5:
295 gb->memory.mbcWrite = _GBMBC5;
296 break;
297 case GB_MBC6:
298 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
299 gb->memory.mbcWrite = _GBMBC6;
300 gb->memory.mbcRead = _GBMBC6Read;
301 break;
302 case GB_MBC7:
303 gb->memory.mbcWrite = _GBMBC7;
304 gb->memory.mbcRead = _GBMBC7Read;
305 gb->sramSize = 0x100;
306 break;
307 case GB_MMM01:
308 gb->memory.mbcWrite = _GBMMM01;
309 break;
310 case GB_HuC1:
311 gb->memory.mbcWrite = _GBHuC1;
312 break;
313 case GB_HuC3:
314 gb->memory.mbcWrite = _GBHuC3;
315 break;
316 case GB_TAMA5:
317 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
318 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
319 gb->memory.mbcWrite = _GBTAMA5;
320 gb->memory.mbcRead = _GBTAMA5Read;
321 gb->sramSize = 0x20;
322 break;
323 case GB_MBC3_RTC:
324 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
325 gb->memory.mbcWrite = _GBMBC3;
326 break;
327 case GB_MBC5_RUMBLE:
328 gb->memory.mbcWrite = _GBMBC5;
329 break;
330 case GB_POCKETCAM:
331 gb->memory.mbcWrite = _GBPocketCam;
332 gb->memory.mbcRead = _GBPocketCamRead;
333 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
334 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
335 }
336 break;
337 case GB_UNL_WISDOM_TREE:
338 gb->memory.mbcWrite = _GBWisdomTree;
339 break;
340 }
341
342 gb->memory.currentBank = 1;
343 gb->memory.sramCurrentBank = 0;
344 gb->memory.sramAccess = false;
345 gb->memory.rtcAccess = false;
346 gb->memory.activeRtcReg = 0;
347 gb->memory.rtcLatched = false;
348 gb->memory.rtcLastLatch = 0;
349 if (gb->memory.rtc) {
350 if (gb->memory.rtc->sample) {
351 gb->memory.rtc->sample(gb->memory.rtc);
352 }
353 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
354 } else {
355 gb->memory.rtcLastLatch = time(0);
356 }
357 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
358
359 GBResizeSram(gb, gb->sramSize);
360
361 if (gb->memory.mbcType == GB_MBC3_RTC) {
362 GBMBCRTCRead(gb);
363 }
364}
365
366static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
367 time_t t;
368 if (rtc) {
369 if (rtc->sample) {
370 rtc->sample(rtc);
371 }
372 t = rtc->unixTime(rtc);
373 } else {
374 t = time(0);
375 }
376 time_t currentLatch = t;
377 t -= *rtcLastLatch;
378 *rtcLastLatch = currentLatch;
379
380 int64_t diff;
381 diff = rtcRegs[0] + t % 60;
382 if (diff < 0) {
383 diff += 60;
384 t -= 60;
385 }
386 rtcRegs[0] = diff % 60;
387 t /= 60;
388 t += diff / 60;
389
390 diff = rtcRegs[1] + t % 60;
391 if (diff < 0) {
392 diff += 60;
393 t -= 60;
394 }
395 rtcRegs[1] = diff % 60;
396 t /= 60;
397 t += diff / 60;
398
399 diff = rtcRegs[2] + t % 24;
400 if (diff < 0) {
401 diff += 24;
402 t -= 24;
403 }
404 rtcRegs[2] = diff % 24;
405 t /= 24;
406 t += diff / 24;
407
408 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
409 rtcRegs[3] = diff;
410 rtcRegs[4] &= 0xFE;
411 rtcRegs[4] |= (diff >> 8) & 1;
412 if (diff & 0x200) {
413 rtcRegs[4] |= 0x80;
414 }
415}
416
417void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
418 struct GBMemory* memory = &gb->memory;
419 int bank = value & 0x1F;
420 int stride = 1 << memory->mbcState.mbc1.multicartStride;
421 switch (address >> 13) {
422 case 0x0:
423 switch (value) {
424 case 0:
425 memory->sramAccess = false;
426 break;
427 case 0xA:
428 memory->sramAccess = true;
429 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
430 break;
431 default:
432 // TODO
433 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
434 break;
435 }
436 break;
437 case 0x1:
438 if (!bank) {
439 ++bank;
440 }
441 bank &= stride - 1;
442 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
443 break;
444 case 0x2:
445 bank &= 3;
446 if (memory->mbcState.mbc1.mode) {
447 GBMBCSwitchBank0(gb, bank << gb->memory.mbcState.mbc1.multicartStride);
448 GBMBCSwitchSramBank(gb, bank);
449 }
450 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
451 break;
452 case 0x3:
453 memory->mbcState.mbc1.mode = value & 1;
454 if (memory->mbcState.mbc1.mode) {
455 GBMBCSwitchBank0(gb, memory->currentBank & ~((1 << memory->mbcState.mbc1.multicartStride) - 1));
456 } else {
457 GBMBCSwitchBank0(gb, 0);
458 GBMBCSwitchSramBank(gb, 0);
459 }
460 break;
461 default:
462 // TODO
463 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
464 break;
465 }
466}
467
468void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
469 struct GBMemory* memory = &gb->memory;
470 int shift = (address & 1) * 4;
471 int bank = value & 0xF;
472 switch (address >> 13) {
473 case 0x0:
474 switch (value) {
475 case 0:
476 memory->sramAccess = false;
477 break;
478 case 0xA:
479 memory->sramAccess = true;
480 break;
481 default:
482 // TODO
483 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
484 break;
485 }
486 break;
487 case 0x1:
488 if (!bank) {
489 ++bank;
490 }
491 GBMBCSwitchBank(gb, bank);
492 break;
493 case 0x5:
494 if (!memory->sramAccess) {
495 return;
496 }
497 address &= 0x1FF;
498 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
499 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
500 break;
501 default:
502 // TODO
503 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
504 break;
505 }
506}
507
508static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
509 address &= 0x1FF;
510 int shift = (address & 1) * 4;
511 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
512}
513
514void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
515 struct GBMemory* memory = &gb->memory;
516 int bank = value & 0x7F;
517 switch (address >> 13) {
518 case 0x0:
519 switch (value) {
520 case 0:
521 memory->sramAccess = false;
522 break;
523 case 0xA:
524 memory->sramAccess = true;
525 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
526 break;
527 default:
528 // TODO
529 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
530 break;
531 }
532 break;
533 case 0x1:
534 if (!bank) {
535 ++bank;
536 }
537 GBMBCSwitchBank(gb, bank);
538 break;
539 case 0x2:
540 if (value < 8) {
541 GBMBCSwitchSramBank(gb, value);
542 memory->rtcAccess = false;
543 } else if (value <= 0xC) {
544 memory->activeRtcReg = value - 8;
545 memory->rtcAccess = true;
546 }
547 break;
548 case 0x3:
549 if (memory->rtcLatched && value == 0) {
550 memory->rtcLatched = false;
551 } else if (!memory->rtcLatched && value == 1) {
552 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
553 memory->rtcLatched = true;
554 }
555 break;
556 }
557}
558
559void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
560 struct GBMemory* memory = &gb->memory;
561 int bank;
562 switch (address >> 12) {
563 case 0x0:
564 case 0x1:
565 switch (value) {
566 case 0:
567 memory->sramAccess = false;
568 break;
569 case 0xA:
570 memory->sramAccess = true;
571 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
572 break;
573 default:
574 // TODO
575 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
576 break;
577 }
578 break;
579 case 0x2:
580 bank = (memory->currentBank & 0x100) | value;
581 GBMBCSwitchBank(gb, bank);
582 break;
583 case 0x3:
584 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
585 GBMBCSwitchBank(gb, bank);
586 break;
587 case 0x4:
588 case 0x5:
589 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
590 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
591 value &= ~8;
592 }
593 GBMBCSwitchSramBank(gb, value & 0xF);
594 break;
595 default:
596 // TODO
597 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
598 break;
599 }
600}
601
602void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
603 struct GBMemory* memory = &gb->memory;
604 int bank = value;
605 switch (address >> 10) {
606 case 0:
607 switch (value) {
608 case 0:
609 memory->mbcState.mbc6.sramAccess = false;
610 break;
611 case 0xA:
612 memory->mbcState.mbc6.sramAccess = true;
613 break;
614 default:
615 // TODO
616 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
617 break;
618 }
619 break;
620 case 0x1:
621 GBMBCSwitchSramHalfBank(gb, 0, bank);
622 break;
623 case 0x2:
624 GBMBCSwitchSramHalfBank(gb, 1, bank);
625 break;
626 case 0x8:
627 case 0x9:
628 GBMBCSwitchHalfBank(gb, 0, bank);
629 break;
630 case 0xC:
631 case 0xD:
632 GBMBCSwitchHalfBank(gb, 1, bank);
633 break;
634 case 0x28:
635 case 0x29:
636 case 0x2A:
637 case 0x2B:
638 if (memory->mbcState.mbc6.sramAccess) {
639 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
640 }
641 break;
642 case 0x2C:
643 case 0x2D:
644 case 0x2E:
645 case 0x2F:
646 if (memory->mbcState.mbc6.sramAccess) {
647 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
648 }
649 break;
650 default:
651 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
652 break;
653 }
654}
655
656uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
657 if (!memory->mbcState.mbc6.sramAccess) {
658 return 0xFF;
659 }
660 switch (address >> 12) {
661 case 0xA:
662 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
663 case 0xB:
664 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
665 }
666 return 0xFF;
667}
668
669void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
670 int bank = value & 0x7F;
671 switch (address >> 13) {
672 case 0x0:
673 switch (value) {
674 default:
675 case 0:
676 gb->memory.mbcState.mbc7.access = 0;
677 break;
678 case 0xA:
679 gb->memory.mbcState.mbc7.access |= 1;
680 break;
681 }
682 break;
683 case 0x1:
684 GBMBCSwitchBank(gb, bank);
685 break;
686 case 0x2:
687 if (value == 0x40) {
688 gb->memory.mbcState.mbc7.access |= 2;
689 } else {
690 gb->memory.mbcState.mbc7.access &= ~2;
691 }
692 break;
693 case 0x5:
694 _GBMBC7Write(&gb->memory, address, value);
695 break;
696 default:
697 // TODO
698 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
699 break;
700 }
701}
702
703uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
704 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
705 if (mbc7->access != 3) {
706 return 0xFF;
707 }
708 switch (address & 0xF0) {
709 case 0x20:
710 if (memory->rotation && memory->rotation->readTiltX) {
711 int32_t x = -memory->rotation->readTiltX(memory->rotation);
712 x >>= 21;
713 x += 0x81D0;
714 return x;
715 }
716 return 0xFF;
717 case 0x30:
718 if (memory->rotation && memory->rotation->readTiltX) {
719 int32_t x = -memory->rotation->readTiltX(memory->rotation);
720 x >>= 21;
721 x += 0x81D0;
722 return x >> 8;
723 }
724 return 7;
725 case 0x40:
726 if (memory->rotation && memory->rotation->readTiltY) {
727 int32_t y = -memory->rotation->readTiltY(memory->rotation);
728 y >>= 21;
729 y += 0x81D0;
730 return y;
731 }
732 return 0xFF;
733 case 0x50:
734 if (memory->rotation && memory->rotation->readTiltY) {
735 int32_t y = -memory->rotation->readTiltY(memory->rotation);
736 y >>= 21;
737 y += 0x81D0;
738 return y >> 8;
739 }
740 return 7;
741 case 0x60:
742 return 0;
743 case 0x80:
744 return mbc7->eeprom;
745 default:
746 return 0xFF;
747 }
748}
749
750static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
751 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
752 if (mbc7->access != 3) {
753 return;
754 }
755 switch (address & 0xF0) {
756 case 0x00:
757 mbc7->latch = (value & 0x55) == 0x55;
758 return;
759 case 0x10:
760 mbc7->latch |= (value & 0xAA);
761 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
762 memory->rotation->sample(memory->rotation);
763 }
764 mbc7->latch = 0;
765 return;
766 default:
767 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
768 return;
769 case 0x80:
770 break;
771 }
772 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
773 value = GBMBC7FieldFillDO(value); // Hi-Z
774 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
775 mbc7->state = GBMBC7_STATE_IDLE;
776 }
777 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
778 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
779 mbc7->sr <<= 1;
780 mbc7->sr |= GBMBC7FieldGetDI(value);
781 ++mbc7->srBits;
782 }
783 switch (mbc7->state) {
784 case GBMBC7_STATE_IDLE:
785 if (GBMBC7FieldIsDI(value)) {
786 mbc7->state = GBMBC7_STATE_READ_COMMAND;
787 mbc7->srBits = 0;
788 mbc7->sr = 0;
789 }
790 break;
791 case GBMBC7_STATE_READ_COMMAND:
792 if (mbc7->srBits == 10) {
793 mbc7->state = 0x10 | (mbc7->sr >> 6);
794 if (mbc7->state & 0xC) {
795 mbc7->state &= ~0x3;
796 }
797 mbc7->srBits = 0;
798 mbc7->address = mbc7->sr & 0x7F;
799 }
800 break;
801 case GBMBC7_STATE_DO:
802 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
803 mbc7->sr <<= 1;
804 --mbc7->srBits;
805 if (!mbc7->srBits) {
806 mbc7->state = GBMBC7_STATE_IDLE;
807 }
808 break;
809 default:
810 break;
811 }
812 switch (mbc7->state) {
813 case GBMBC7_STATE_EEPROM_EWEN:
814 mbc7->writable = true;
815 mbc7->state = GBMBC7_STATE_IDLE;
816 break;
817 case GBMBC7_STATE_EEPROM_EWDS:
818 mbc7->writable = false;
819 mbc7->state = GBMBC7_STATE_IDLE;
820 break;
821 case GBMBC7_STATE_EEPROM_WRITE:
822 if (mbc7->srBits == 16) {
823 if (mbc7->writable) {
824 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
825 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
826 }
827 mbc7->state = GBMBC7_STATE_IDLE;
828 }
829 break;
830 case GBMBC7_STATE_EEPROM_ERASE:
831 if (mbc7->writable) {
832 memory->sram[mbc7->address * 2] = 0xFF;
833 memory->sram[mbc7->address * 2 + 1] = 0xFF;
834 }
835 mbc7->state = GBMBC7_STATE_IDLE;
836 break;
837 case GBMBC7_STATE_EEPROM_READ:
838 mbc7->srBits = 16;
839 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
840 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
841 mbc7->state = GBMBC7_STATE_DO;
842 value = GBMBC7FieldClearDO(value);
843 break;
844 case GBMBC7_STATE_EEPROM_WRAL:
845 if (mbc7->srBits == 16) {
846 if (mbc7->writable) {
847 int i;
848 for (i = 0; i < 128; ++i) {
849 memory->sram[i * 2] = mbc7->sr >> 8;
850 memory->sram[i * 2 + 1] = mbc7->sr;
851 }
852 }
853 mbc7->state = GBMBC7_STATE_IDLE;
854 }
855 break;
856 case GBMBC7_STATE_EEPROM_ERAL:
857 if (mbc7->writable) {
858 int i;
859 for (i = 0; i < 128; ++i) {
860 memory->sram[i * 2] = 0xFF;
861 memory->sram[i * 2 + 1] = 0xFF;
862 }
863 }
864 mbc7->state = GBMBC7_STATE_IDLE;
865 break;
866 default:
867 break;
868 }
869 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
870 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
871 }
872 mbc7->eeprom = value;
873}
874
875void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
876 struct GBMemory* memory = &gb->memory;
877 if (!memory->mbcState.mmm01.locked) {
878 switch (address >> 13) {
879 case 0x0:
880 memory->mbcState.mmm01.locked = true;
881 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
882 break;
883 case 0x1:
884 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
885 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
886 break;
887 case 0x2:
888 memory->mbcState.mmm01.currentBank0 &= ~0x180;
889 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
890 break;
891 default:
892 // TODO
893 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
894 break;
895 }
896 return;
897 }
898 switch (address >> 13) {
899 case 0x0:
900 switch (value) {
901 case 0xA:
902 memory->sramAccess = true;
903 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
904 break;
905 default:
906 memory->sramAccess = false;
907 break;
908 }
909 break;
910 case 0x1:
911 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
912 break;
913 case 0x2:
914 GBMBCSwitchSramBank(gb, value);
915 break;
916 default:
917 // TODO
918 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
919 break;
920 }
921}
922
923void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
924 struct GBMemory* memory = &gb->memory;
925 int bank = value & 0x3F;
926 switch (address >> 13) {
927 case 0x0:
928 switch (value) {
929 case 0xE:
930 memory->sramAccess = false;
931 break;
932 default:
933 memory->sramAccess = true;
934 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
935 break;
936 }
937 break;
938 case 0x1:
939 GBMBCSwitchBank(gb, bank);
940 break;
941 case 0x2:
942 GBMBCSwitchSramBank(gb, value);
943 break;
944 default:
945 // TODO
946 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
947 break;
948 }
949}
950
951void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
952 struct GBMemory* memory = &gb->memory;
953 int bank = value & 0x3F;
954 if (address & 0x1FFF) {
955 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
956 }
957
958 switch (address >> 13) {
959 case 0x0:
960 switch (value) {
961 case 0xA:
962 memory->sramAccess = true;
963 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
964 break;
965 default:
966 memory->sramAccess = false;
967 break;
968 }
969 break;
970 case 0x1:
971 GBMBCSwitchBank(gb, bank);
972 break;
973 case 0x2:
974 GBMBCSwitchSramBank(gb, bank);
975 break;
976 default:
977 // TODO
978 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
979 break;
980 }
981}
982
983void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
984 struct GBMemory* memory = &gb->memory;
985 int bank = value & 0x3F;
986 switch (address >> 13) {
987 case 0x0:
988 switch (value) {
989 case 0:
990 memory->sramAccess = false;
991 break;
992 case 0xA:
993 memory->sramAccess = true;
994 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
995 break;
996 default:
997 // TODO
998 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
999 break;
1000 }
1001 break;
1002 case 0x1:
1003 GBMBCSwitchBank(gb, bank);
1004 break;
1005 case 0x2:
1006 if (value < 0x10) {
1007 GBMBCSwitchSramBank(gb, value);
1008 memory->mbcState.pocketCam.registersActive = false;
1009 } else {
1010 memory->mbcState.pocketCam.registersActive = true;
1011 }
1012 break;
1013 case 0x5:
1014 address &= 0x7F;
1015 if (address == 0 && value & 1) {
1016 value &= 6; // TODO: Timing
1017 _GBPocketCamCapture(memory);
1018 }
1019 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
1020 memory->mbcState.pocketCam.registers[address] = value;
1021 }
1022 break;
1023 default:
1024 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
1025 break;
1026 }
1027}
1028
1029uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1030 if (memory->mbcState.pocketCam.registersActive) {
1031 if ((address & 0x7F) == 0) {
1032 return memory->mbcState.pocketCam.registers[0];
1033 }
1034 return 0;
1035 }
1036 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1037}
1038
1039void _GBPocketCamCapture(struct GBMemory* memory) {
1040 if (!memory->cam) {
1041 return;
1042 }
1043 const void* image = NULL;
1044 size_t stride;
1045 enum mColorFormat format;
1046 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1047 if (!image) {
1048 return;
1049 }
1050 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1051 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1052 size_t x, y;
1053 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1054 for (x = 0; x < GBCAM_WIDTH; ++x) {
1055 uint32_t gray;
1056 uint32_t color;
1057 switch (format) {
1058 case mCOLOR_XBGR8:
1059 case mCOLOR_XRGB8:
1060 case mCOLOR_ARGB8:
1061 case mCOLOR_ABGR8:
1062 color = ((const uint32_t*) image)[y * stride + x];
1063 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1064 break;
1065 case mCOLOR_BGRX8:
1066 case mCOLOR_RGBX8:
1067 case mCOLOR_RGBA8:
1068 case mCOLOR_BGRA8:
1069 color = ((const uint32_t*) image)[y * stride + x];
1070 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1071 break;
1072 case mCOLOR_BGR5:
1073 case mCOLOR_RGB5:
1074 case mCOLOR_ARGB5:
1075 case mCOLOR_ABGR5:
1076 color = ((const uint16_t*) image)[y * stride + x];
1077 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1078 break;
1079 case mCOLOR_BGR565:
1080 case mCOLOR_RGB565:
1081 color = ((const uint16_t*) image)[y * stride + x];
1082 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1083 break;
1084 case mCOLOR_BGRA5:
1085 case mCOLOR_RGBA5:
1086 color = ((const uint16_t*) image)[y * stride + x];
1087 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1088 break;
1089 default:
1090 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1091 return;
1092 }
1093 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1094 gray = (gray + 1) * exposure / 0x300;
1095 // TODO: Additional processing
1096 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1097 if (gray < pocketCam->registers[matrixEntry + 6]) {
1098 gray = 0x101;
1099 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1100 gray = 0x100;
1101 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1102 gray = 0x001;
1103 } else {
1104 gray = 0;
1105 }
1106 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1107 uint16_t existing;
1108 LOAD_16LE(existing, coord + 0x100, memory->sram);
1109 existing |= gray << (7 - (x & 7));
1110 STORE_16LE(existing, coord + 0x100, memory->sram);
1111 }
1112 }
1113}
1114
1115void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1116 struct GBMemory* memory = &gb->memory;
1117 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1118 switch (address >> 13) {
1119 case 0x5:
1120 if (address & 1) {
1121 tama5->reg = value;
1122 } else {
1123 value &= 0xF;
1124 if (tama5->reg < GBTAMA5_MAX) {
1125 tama5->registers[tama5->reg] = value;
1126 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1127 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1128 switch (tama5->reg) {
1129 case GBTAMA5_BANK_LO:
1130 case GBTAMA5_BANK_HI:
1131 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1132 break;
1133 case GBTAMA5_WRITE_LO:
1134 case GBTAMA5_WRITE_HI:
1135 case GBTAMA5_CS:
1136 break;
1137 case GBTAMA5_ADDR_LO:
1138 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1139 case 0x0: // RAM write
1140 memory->sram[address] = out;
1141 break;
1142 case 0x1: // RAM read
1143 break;
1144 default:
1145 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1146 }
1147 break;
1148 default:
1149 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1150 break;
1151 }
1152 } else {
1153 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1154 }
1155 }
1156 break;
1157 default:
1158 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1159 }
1160}
1161
1162uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1163 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1164 if ((address & 0x1FFF) > 1) {
1165 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1166 }
1167 if (address & 1) {
1168 return 0xFF;
1169 } else {
1170 uint8_t value = 0xF0;
1171 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1172 switch (tama5->reg) {
1173 case GBTAMA5_ACTIVE:
1174 return 0xF1;
1175 case GBTAMA5_READ_LO:
1176 case GBTAMA5_READ_HI:
1177 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1178 case 1:
1179 value = memory->sram[address];
1180 break;
1181 default:
1182 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1183 break;
1184 }
1185 if (tama5->reg == GBTAMA5_READ_HI) {
1186 value >>= 4;
1187 }
1188 value |= 0xF0;
1189 return value;
1190 default:
1191 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1192 return 0xF1;
1193 }
1194 }
1195}
1196
1197void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) {
1198 UNUSED(value);
1199 int bank = address & 0x3F;
1200 switch (address >> 14) {
1201 case 0x0:
1202 GBMBCSwitchBank0(gb, bank * 2);
1203 GBMBCSwitchBank(gb, bank * 2 + 1);
1204 break;
1205 default:
1206 // TODO
1207 mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value);
1208 break;
1209 }
1210}
1211
1212void GBMBCRTCRead(struct GB* gb) {
1213 struct GBMBCRTCSaveBuffer rtcBuffer;
1214 struct VFile* vf = gb->sramVf;
1215 if (!vf) {
1216 return;
1217 }
1218 vf->seek(vf, gb->sramSize, SEEK_SET);
1219 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1220 return;
1221 }
1222
1223 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1224 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1225 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1226 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1227 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1228 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1229}
1230
1231void GBMBCRTCWrite(struct GB* gb) {
1232 struct VFile* vf = gb->sramVf;
1233 if (!vf) {
1234 return;
1235 }
1236
1237 uint8_t rtcRegs[5];
1238 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1239 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1240 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1241
1242 struct GBMBCRTCSaveBuffer rtcBuffer;
1243 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1244 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1245 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1246 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1247 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1248 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1249 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1250 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1251 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1252 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1253 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1254
1255 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1256 // Writing past the end of the file can invalidate the file mapping
1257 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1258 gb->memory.sram = NULL;
1259 }
1260 vf->seek(vf, gb->sramSize, SEEK_SET);
1261 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1262 if (!gb->memory.sram) {
1263 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1264 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1265 }
1266}