src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-gpio.h"
4#include "gba-io.h"
5#include "gba-serialize.h"
6#include "hle-bios.h"
7#include "util/memory.h"
8
9static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
10static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count);
11static void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info);
12
13static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
14static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
17static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
18static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
19static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
20
21void GBAMemoryInit(struct GBAMemory* memory) {
22 memory->d.load32 = GBALoad32;
23 memory->d.load16 = GBALoad16;
24 memory->d.loadU16 = GBALoadU16;
25 memory->d.load8 = GBALoad8;
26 memory->d.loadU8 = GBALoadU8;
27 memory->d.store32 = GBAStore32;
28 memory->d.store16 = GBAStore16;
29 memory->d.store8 = GBAStore8;
30
31 memory->bios = (uint32_t*) hleBios;
32 memory->fullBios = 0;
33 memory->wram = anonymousMemoryMap(SIZE_WORKING_RAM);
34 memory->iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
35 memory->rom = 0;
36 memory->gpio.p = memory->p;
37 memset(memory->io, 0, sizeof(memory->io));
38 memset(memory->dma, 0, sizeof(memory->dma));
39 int i;
40 for (i = 0; i < 4; ++i) {
41 memory->dma[i].count = 0x10000;
42 memory->dma[i].nextEvent = INT_MAX;
43 }
44 memory->activeDMA = -1;
45 memory->nextDMA = INT_MAX;
46 memory->eventDiff = 0;
47
48 if (!memory->wram || !memory->iwram) {
49 GBAMemoryDeinit(memory);
50 GBALog(memory->p, GBA_LOG_FATAL, "Could not map memory");
51 return;
52 }
53
54 for (i = 0; i < 16; ++i) {
55 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
56 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
57 memory->waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
58 memory->waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
59 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
60 memory->waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
61 }
62 for (; i < 256; ++i) {
63 memory->waitstates16[i] = 0;
64 memory->waitstatesSeq16[i] = 0;
65 memory->waitstatesPrefetch16[i] = 0;
66 memory->waitstates32[i] = 0;
67 memory->waitstatesSeq32[i] = 0;
68 memory->waitstatesPrefetch32[i] = 0;
69 }
70
71 memory->activeRegion = -1;
72 memory->d.activeRegion = 0;
73 memory->d.activeMask = 0;
74 memory->d.setActiveRegion = GBASetActiveRegion;
75 memory->d.activePrefetchCycles32 = 0;
76 memory->d.activePrefetchCycles16 = 0;
77 memory->biosPrefetch = 0;
78 memory->d.waitMultiple = GBAWaitMultiple;
79}
80
81void GBAMemoryDeinit(struct GBAMemory* memory) {
82 mappedMemoryFree(memory->wram, SIZE_WORKING_RAM);
83 mappedMemoryFree(memory->iwram, SIZE_WORKING_IRAM);
84 GBASavedataDeinit(&memory->savedata);
85}
86
87static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
88 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
89
90 int newRegion = address >> BASE_OFFSET;
91 if (newRegion == gbaMemory->activeRegion) {
92 return;
93 }
94 if (gbaMemory->activeRegion == REGION_BIOS) {
95 gbaMemory->biosPrefetch = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
96 }
97 gbaMemory->activeRegion = newRegion;
98 memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[gbaMemory->activeRegion];
99 memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[gbaMemory->activeRegion];
100 memory->activeNonseqCycles32 = gbaMemory->waitstates32[gbaMemory->activeRegion];
101 memory->activeNonseqCycles16 = gbaMemory->waitstates16[gbaMemory->activeRegion];
102 switch (address & ~OFFSET_MASK) {
103 case BASE_BIOS:
104 memory->activeRegion = gbaMemory->bios;
105 memory->activeMask = SIZE_BIOS - 1;
106 break;
107 case BASE_WORKING_RAM:
108 memory->activeRegion = gbaMemory->wram;
109 memory->activeMask = SIZE_WORKING_RAM - 1;
110 break;
111 case BASE_WORKING_IRAM:
112 memory->activeRegion = gbaMemory->iwram;
113 memory->activeMask = SIZE_WORKING_IRAM - 1;
114 break;
115 case BASE_CART0:
116 case BASE_CART0_EX:
117 case BASE_CART1:
118 case BASE_CART1_EX:
119 case BASE_CART2:
120 case BASE_CART2_EX:
121 memory->activeRegion = gbaMemory->rom;
122 memory->activeMask = SIZE_CART0 - 1;
123 break;
124 default:
125 memory->activeRegion = 0;
126 memory->activeMask = 0;
127 GBALog(gbaMemory->p, GBA_LOG_FATAL, "Jumped to invalid address");
128 break;
129 }
130}
131
132int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
133 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
134 uint32_t value = 0;
135 int wait = 0;
136
137 switch (address & ~OFFSET_MASK) {
138 case BASE_BIOS:
139 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
140 if (address < SIZE_BIOS) {
141 LOAD_32(value, address, gbaMemory->bios);
142 } else {
143 value = 0;
144 }
145 } else {
146 value = gbaMemory->biosPrefetch;
147 }
148 break;
149 case BASE_WORKING_RAM:
150 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
151 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
152 break;
153 case BASE_WORKING_IRAM:
154 LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
155 break;
156 case BASE_IO:
157 value = GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
158 break;
159 case BASE_PALETTE_RAM:
160 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
161 break;
162 case BASE_VRAM:
163 LOAD_32(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
164 break;
165 case BASE_OAM:
166 LOAD_32(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
167 break;
168 case BASE_CART0:
169 case BASE_CART0_EX:
170 case BASE_CART1:
171 case BASE_CART1_EX:
172 case BASE_CART2:
173 case BASE_CART2_EX:
174 wait = gbaMemory->waitstates32[address >> BASE_OFFSET];
175 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
176 LOAD_32(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
177 }
178 break;
179 case BASE_CART_SRAM:
180 case BASE_CART_SRAM_MIRROR:
181 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
182 break;
183 default:
184 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
185 if (gbaMemory->p->cpu.executionMode == MODE_ARM) {
186 value = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
187 } else {
188 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_THUMB * 2, 0);
189 value |= value << 16;
190 }
191 break;
192 }
193
194
195 if (cycleCounter) {
196 *cycleCounter += 2 + wait;
197 }
198 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
199 int rotate = (address & 3) << 3;
200 return (value >> rotate) | (value << (32 - rotate));
201}
202
203uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
204 return GBALoad16(memory, address, cycleCounter);
205}
206
207int16_t GBALoad16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
208 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
209 uint16_t value = 0;
210 int wait = 0;
211
212 switch (address & ~OFFSET_MASK) {
213 case BASE_BIOS:
214 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
215 if (address < SIZE_BIOS) {
216 LOAD_16(value, address, gbaMemory->bios);
217 } else {
218 value = 0;
219 }
220 } else {
221 value = gbaMemory->biosPrefetch;
222 }
223 break;
224 case BASE_WORKING_RAM:
225 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
226 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
227 break;
228 case BASE_WORKING_IRAM:
229 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
230 break;
231 case BASE_IO:
232 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
233 break;
234 case BASE_PALETTE_RAM:
235 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
236 break;
237 case BASE_VRAM:
238 LOAD_16(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
239 break;
240 case BASE_OAM:
241 LOAD_16(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
242 break;
243 case BASE_CART0:
244 case BASE_CART0_EX:
245 case BASE_CART1:
246 case BASE_CART1_EX:
247 case BASE_CART2:
248 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
249 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
250 LOAD_16(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
251 }
252 break;
253 case BASE_CART2_EX:
254 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
255 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
256 value = GBASavedataReadEEPROM(&gbaMemory->savedata);
257 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
258 LOAD_16(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
259 }
260 break;
261 case BASE_CART_SRAM:
262 case BASE_CART_SRAM_MIRROR:
263 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
264 break;
265 default:
266 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
267 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0);
268 break;
269 }
270
271 if (cycleCounter) {
272 *cycleCounter += 2 + wait;
273 }
274 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
275 int rotate = (address & 1) << 3;
276 return (value >> rotate) | (value << (16 - rotate));
277}
278
279uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
280 return GBALoad8(memory, address, cycleCounter);
281}
282
283int8_t GBALoad8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
284 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
285 int8_t value = 0;
286 int wait = 0;
287
288 switch (address & ~OFFSET_MASK) {
289 case BASE_BIOS:
290 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
291 if (address < SIZE_BIOS) {
292 value = ((int8_t*) gbaMemory->bios)[address];
293 } else {
294 value = 0;
295 }
296 } else {
297 value = gbaMemory->biosPrefetch;
298 }
299 break;
300 case BASE_WORKING_RAM:
301 value = ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
302 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
303 break;
304 case BASE_WORKING_IRAM:
305 value = ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
306 break;
307 case BASE_IO:
308 value = (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
309 break;
310 case BASE_PALETTE_RAM:
311 value = ((int8_t*) gbaMemory->p->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
312 break;
313 case BASE_VRAM:
314 value = ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x0001FFFF];
315 break;
316 case BASE_OAM:
317 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
318 break;
319 case BASE_CART0:
320 case BASE_CART0_EX:
321 case BASE_CART1:
322 case BASE_CART1_EX:
323 case BASE_CART2:
324 case BASE_CART2_EX:
325 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
326 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
327 value = ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
328 }
329 break;
330 case BASE_CART_SRAM:
331 case BASE_CART_SRAM_MIRROR:
332 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
333 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
334 GBASavedataInitSRAM(&gbaMemory->savedata);
335 }
336 if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
337 value = gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
338 } else if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
339 value = GBASavedataReadFlash(&gbaMemory->savedata, address);
340 }
341 break;
342 default:
343 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
344 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0) >> ((address & 1) << 3);
345 break;
346 }
347
348 if (cycleCounter) {
349 *cycleCounter += 2 + wait;
350 }
351 return value;
352}
353
354void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value, int* cycleCounter) {
355 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
356 int wait = 0;
357
358 switch (address & ~OFFSET_MASK) {
359 case BASE_WORKING_RAM:
360 STORE_32(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
361 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
362 break;
363 case BASE_WORKING_IRAM:
364 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
365 break;
366 case BASE_IO:
367 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
368 break;
369 case BASE_PALETTE_RAM:
370 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
371 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
372 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
373 break;
374 case BASE_VRAM:
375 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
376 STORE_32(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
377 }
378 break;
379 case BASE_OAM:
380 STORE_32(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
381 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
382 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
383 break;
384 case BASE_CART0:
385 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
386 break;
387 case BASE_CART_SRAM:
388 case BASE_CART_SRAM_MIRROR:
389 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
390 break;
391 default:
392 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
393 break;
394 }
395
396 if (cycleCounter) {
397 *cycleCounter += 1 + wait;
398 }
399}
400
401void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value, int* cycleCounter) {
402 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
403 int wait = 0;
404
405 switch (address & ~OFFSET_MASK) {
406 case BASE_WORKING_RAM:
407 STORE_16(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
408 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
409 break;
410 case BASE_WORKING_IRAM:
411 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
412 break;
413 case BASE_IO:
414 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
415 break;
416 case BASE_PALETTE_RAM:
417 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
418 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
419 break;
420 case BASE_VRAM:
421 if ((address & OFFSET_MASK) < SIZE_VRAM) {
422 STORE_16(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
423 }
424 break;
425 case BASE_OAM:
426 STORE_16(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
427 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
428 break;
429 case BASE_CART0:
430 if (IS_GPIO_REGISTER(address & 0xFFFFFF)) {
431 uint32_t reg = address & 0xFFFFFF;
432 GBAGPIOWrite(&gbaMemory->gpio, reg, value);
433 } else {
434 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
435 }
436 break;
437 case BASE_CART2_EX:
438 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
439 GBASavedataInitEEPROM(&gbaMemory->savedata);
440 }
441 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
442 break;
443 case BASE_CART_SRAM:
444 case BASE_CART_SRAM_MIRROR:
445 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
446 break;
447 default:
448 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
449 break;
450 }
451
452 if (cycleCounter) {
453 *cycleCounter += 1 + wait;
454 }
455}
456
457void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value, int* cycleCounter) {
458 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
459 int wait = 0;
460
461 switch (address & ~OFFSET_MASK) {
462 case BASE_WORKING_RAM:
463 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
464 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
465 break;
466 case BASE_WORKING_IRAM:
467 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
468 break;
469 case BASE_IO:
470 GBAIOWrite8(gbaMemory->p, address & (SIZE_IO - 1), value);
471 break;
472 case BASE_PALETTE_RAM:
473 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
474 break;
475 case BASE_VRAM:
476 if (address >= 0x06018000) {
477 // TODO: check BG mode
478 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
479 break;
480 }
481 ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x1FFFE] = value;
482 ((int8_t*) gbaMemory->p->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
483 break;
484 case BASE_OAM:
485 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
486 break;
487 case BASE_CART0:
488 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
489 break;
490 case BASE_CART_SRAM:
491 case BASE_CART_SRAM_MIRROR:
492 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
493 if (address == SAVEDATA_FLASH_BASE) {
494 GBASavedataInitFlash(&gbaMemory->savedata);
495 } else {
496 GBASavedataInitSRAM(&gbaMemory->savedata);
497 }
498 }
499 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
500 GBASavedataWriteFlash(&gbaMemory->savedata, address, value);
501 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
502 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
503 }
504 wait = gbaMemory->waitstates16[REGION_CART_SRAM];
505 break;
506 default:
507 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
508 break;
509 }
510
511 if (cycleCounter) {
512 *cycleCounter += 1 + wait;
513 }
514}
515
516static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count) {
517 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
518 int wait = 1 + gbaMemory->waitstates32[startAddress >> BASE_OFFSET];
519 wait += (1 + gbaMemory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
520 return wait;
521}
522
523void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
524 int sram = parameters & 0x0003;
525 int ws0 = (parameters & 0x000C) >> 2;
526 int ws0seq = (parameters & 0x0010) >> 4;
527 int ws1 = (parameters & 0x0060) >> 5;
528 int ws1seq = (parameters & 0x0080) >> 7;
529 int ws2 = (parameters & 0x0300) >> 8;
530 int ws2seq = (parameters & 0x0400) >> 10;
531 int prefetch = parameters & 0x4000;
532
533 memory->waitstates16[REGION_CART_SRAM] = memory->waitstates16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
534 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
535 memory->waitstates32[REGION_CART_SRAM] = memory->waitstates32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
536 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
537
538 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
539 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
540 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
541
542 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
543 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
544 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
545
546 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
547 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
548 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
549
550 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
551 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
552 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
553
554 if (!prefetch) {
555 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
556 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
557 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
558
559 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
560 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
561 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
562 } else {
563 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
564 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
565 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
566
567 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
568 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
569 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
570 }
571
572 memory->d.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
573 memory->d.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
574 memory->d.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
575 memory->d.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
576}
577
578void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
579 memory->dma[dma].source = address & 0xFFFFFFFE;
580}
581
582void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
583 memory->dma[dma].dest = address & 0xFFFFFFFE;
584}
585
586void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
587 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
588}
589
590uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
591 struct GBADMA* currentDma = &memory->dma[dma];
592 int wasEnabled = currentDma->enable;
593 currentDma->packed = control;
594
595 if (currentDma->drq) {
596 GBALog(memory->p, GBA_LOG_STUB, "DRQ not implemented");
597 }
598
599 if (!wasEnabled && currentDma->enable) {
600 currentDma->nextSource = currentDma->source;
601 currentDma->nextDest = currentDma->dest;
602 currentDma->nextCount = currentDma->count;
603 GBAMemoryScheduleDMA(memory, dma, currentDma);
604 }
605 // If the DMA has already occurred, this value might have changed since the function started
606 return currentDma->packed;
607};
608
609void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
610 switch (info->timing) {
611 case DMA_TIMING_NOW:
612 info->nextEvent = memory->p->cpu.cycles;
613 GBAMemoryUpdateDMAs(memory, 0);
614 break;
615 case DMA_TIMING_HBLANK:
616 // Handled implicitly
617 info->nextEvent = INT_MAX;
618 break;
619 case DMA_TIMING_VBLANK:
620 // Handled implicitly
621 info->nextEvent = INT_MAX;
622 break;
623 case DMA_TIMING_CUSTOM:
624 info->nextEvent = INT_MAX;
625 switch (number) {
626 case 0:
627 GBALog(memory->p, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
628 break;
629 case 1:
630 case 2:
631 GBAAudioScheduleFifoDma(&memory->p->audio, number, info);
632 break;
633 case 3:
634 // GBAVideoScheduleVCaptureDma(dma, info);
635 break;
636 }
637 }
638}
639
640void GBAMemoryRunHblankDMAs(struct GBAMemory* memory, int32_t cycles) {
641 struct GBADMA* dma;
642 int i;
643 for (i = 0; i < 4; ++i) {
644 dma = &memory->dma[i];
645 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
646 dma->nextEvent = cycles;
647 }
648 }
649 GBAMemoryUpdateDMAs(memory, 0);
650}
651
652void GBAMemoryRunVblankDMAs(struct GBAMemory* memory, int32_t cycles) {
653 struct GBADMA* dma;
654 int i;
655 for (i = 0; i < 4; ++i) {
656 dma = &memory->dma[i];
657 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
658 dma->nextEvent = cycles;
659 }
660 }
661 GBAMemoryUpdateDMAs(memory, 0);
662}
663
664int32_t GBAMemoryRunDMAs(struct GBAMemory* memory, int32_t cycles) {
665 if (memory->nextDMA == INT_MAX) {
666 return INT_MAX;
667 }
668 memory->nextDMA -= cycles;
669 memory->eventDiff += cycles;
670 if (memory->nextDMA <= 0) {
671 struct GBADMA* dma = &memory->dma[memory->activeDMA];
672 GBAMemoryServiceDMA(memory, memory->activeDMA, dma);
673 GBAMemoryUpdateDMAs(memory, memory->eventDiff);
674 memory->eventDiff = 0;
675 }
676 return memory->nextDMA;
677}
678
679void GBAMemoryUpdateDMAs(struct GBAMemory* memory, int32_t cycles) {
680 int i;
681 memory->activeDMA = -1;
682 memory->nextDMA = INT_MAX;
683 for (i = 3; i >= 0; --i) {
684 struct GBADMA* dma = &memory->dma[i];
685 if (dma->nextEvent != INT_MAX) {
686 dma->nextEvent -= cycles;
687 if (dma->enable) {
688 memory->activeDMA = i;
689 memory->nextDMA = dma->nextEvent;
690 }
691 }
692 }
693 if (memory->nextDMA < memory->p->cpu.nextEvent) {
694 memory->p->cpu.nextEvent = memory->nextDMA;
695 }
696}
697
698void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
699 uint32_t width = info->width ? 4 : 2;
700 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
701 int destOffset = DMA_OFFSET[info->dstControl] * width;
702 int32_t wordsRemaining = info->nextCount;
703 uint32_t source = info->nextSource;
704 uint32_t dest = info->nextDest;
705 uint32_t sourceRegion = source >> BASE_OFFSET;
706 uint32_t destRegion = dest >> BASE_OFFSET;
707 int32_t cycles = 0;
708
709 if (source == info->source) {
710 // TODO: support 4 cycles for ROM access
711 cycles += 2;
712 if (width == 4) {
713 cycles += memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion];
714 source &= 0xFFFFFFFC;
715 dest &= 0xFFFFFFFC;
716 } else {
717 cycles += memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion];
718 }
719 } else {
720 if (width == 4) {
721 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
722 } else {
723 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
724 }
725 }
726
727 if (width == 4) {
728 int32_t word;
729 word = memory->d.load32(&memory->d, source, 0);
730 memory->d.store32(&memory->d, dest, word, 0);
731 source += sourceOffset;
732 dest += destOffset;
733 --wordsRemaining;
734 } else {
735 uint16_t word;
736 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
737 word = GBASavedataReadEEPROM(&memory->savedata);
738 memory->d.store16(&memory->d, dest, word, 0);
739 source += sourceOffset;
740 dest += destOffset;
741 --wordsRemaining;
742 } else if (destRegion == REGION_CART2_EX) {
743 if (memory->savedata.type == SAVEDATA_NONE) {
744 GBASavedataInitEEPROM(&memory->savedata);
745 }
746 word = memory->d.load16(&memory->d, source, 0);
747 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
748 source += sourceOffset;
749 dest += destOffset;
750 --wordsRemaining;
751 } else {
752 word = memory->d.load16(&memory->d, source, 0);
753 memory->d.store16(&memory->d, dest, word, 0);
754 source += sourceOffset;
755 dest += destOffset;
756 --wordsRemaining;
757 }
758 }
759
760 if (!wordsRemaining) {
761 if (!info->repeat) {
762 info->enable = 0;
763 info->nextEvent = INT_MAX;
764
765 // Clear the enable bit in memory
766 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
767 } else {
768 info->nextCount = info->count;
769 if (info->dstControl == DMA_INCREMENT_RELOAD) {
770 info->nextDest = info->dest;
771 }
772 GBAMemoryScheduleDMA(memory, number, info);
773 }
774 if (info->doIrq) {
775 GBARaiseIRQ(memory->p, IRQ_DMA0 + number);
776 }
777 } else {
778 info->nextDest = dest;
779 info->nextCount = wordsRemaining;
780 }
781 info->nextSource = source;
782
783 int i;
784 for (i = 0; i < 4; ++i) {
785 if (memory->dma[i].nextEvent != INT_MAX) {
786 memory->dma[i].nextEvent += cycles;
787 }
788 }
789 memory->p->cpu.cycles += cycles;
790}
791
792void GBAMemorySerialize(struct GBAMemory* memory, struct GBASerializedState* state) {
793 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
794 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
795}
796
797void GBAMemoryDeserialize(struct GBAMemory* memory, struct GBASerializedState* state) {
798 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
799 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
800}