src/ds/io.c (view raw)
1/* Copyright (c) 2013-2017 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/io.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/ds/audio.h>
10#include <mgba/internal/ds/ds.h>
11#include <mgba/internal/ds/gx.h>
12#include <mgba/internal/ds/ipc.h>
13#include <mgba/internal/ds/slot1.h>
14#include <mgba/internal/ds/spi.h>
15
16mLOG_DEFINE_CATEGORY(DS_IO, "DS I/O", "ds.io");
17
18static void _DSHaltCNT(struct DSCommon* dscore, uint8_t value) {
19 switch (value >> 6) {
20 case 0:
21 default:
22 break;
23 case 1:
24 mLOG(DS_IO, STUB, "Enter GBA mode not supported");
25 break;
26 case 2:
27 ARMHalt(dscore->cpu);
28 break;
29 case 3:
30 mLOG(DS_IO, STUB, "Enter sleep mode not supported");
31 break;
32 }
33}
34
35static uint16_t _scheduleDiv(struct DS* ds, uint16_t control) {
36 mTimingDeschedule(&ds->ds9.timing, &ds->divEvent);
37 mTimingSchedule(&ds->ds9.timing, &ds->divEvent, (control & 3) ? 36 : 68);
38 return control | 0x8000;
39}
40
41static uint16_t _scheduleSqrt(struct DS* ds, uint16_t control) {
42 mTimingDeschedule(&ds->ds9.timing, &ds->sqrtEvent);
43 mTimingSchedule(&ds->ds9.timing, &ds->sqrtEvent, 26);
44 return control | 0x8000;
45}
46
47static uint32_t DSIOWrite(struct DSCommon* dscore, uint32_t address, uint16_t value) {
48 switch (address) {
49 // Video
50 case DS_REG_DISPSTAT:
51 DSVideoWriteDISPSTAT(dscore, value);
52 break;
53
54 // DMA Fill
55 case DS_REG_DMA0FILL_LO:
56 case DS_REG_DMA0FILL_HI:
57 case DS_REG_DMA1FILL_LO:
58 case DS_REG_DMA1FILL_HI:
59 case DS_REG_DMA2FILL_LO:
60 case DS_REG_DMA2FILL_HI:
61 case DS_REG_DMA3FILL_LO:
62 case DS_REG_DMA3FILL_HI:
63 break;
64
65 // Timers
66 case DS_REG_TM0CNT_LO:
67 GBATimerWriteTMCNT_LO(&dscore->timers[0], value);
68 return 0x20000;
69 case DS_REG_TM1CNT_LO:
70 GBATimerWriteTMCNT_LO(&dscore->timers[1], value);
71 return 0x20000;
72 case DS_REG_TM2CNT_LO:
73 GBATimerWriteTMCNT_LO(&dscore->timers[2], value);
74 return 0x20000;
75 case DS_REG_TM3CNT_LO:
76 GBATimerWriteTMCNT_LO(&dscore->timers[3], value);
77 return 0x20000;
78
79 case DS_REG_TM0CNT_HI:
80 value &= 0x00C7;
81 DSTimerWriteTMCNT_HI(&dscore->timers[0], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM0CNT_LO >> 1], value);
82 break;
83 case DS_REG_TM1CNT_HI:
84 value &= 0x00C7;
85 DSTimerWriteTMCNT_HI(&dscore->timers[1], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM1CNT_LO >> 1], value);
86 break;
87 case DS_REG_TM2CNT_HI:
88 value &= 0x00C7;
89 DSTimerWriteTMCNT_HI(&dscore->timers[2], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM2CNT_LO >> 1], value);
90 break;
91 case DS_REG_TM3CNT_HI:
92 value &= 0x00C7;
93 DSTimerWriteTMCNT_HI(&dscore->timers[3], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM3CNT_LO >> 1], value);
94 break;
95
96 // IPC
97 case DS_REG_IPCSYNC:
98 value &= 0x6F00;
99 value |= dscore->memory.io[address >> 1] & 0x000F;
100 DSIPCWriteSYNC(dscore->ipc->cpu, dscore->ipc->memory.io, value);
101 break;
102 case DS_REG_IPCFIFOCNT:
103 value = DSIPCWriteFIFOCNT(dscore, value);
104 break;
105
106 // Cart bus
107 case DS_REG_AUXSPICNT:
108 if (dscore->memory.slot1Access) {
109 value = DSSlot1Configure(dscore->p, value);
110 dscore->ipc->memory.io[address >> 1] = value;
111 } else {
112 mLOG(DS_IO, GAME_ERROR, "Invalid cart access");
113 return 0;
114 }
115 break;
116 case DS_REG_AUXSPIDATA:
117 if (dscore->memory.slot1Access) {
118 DSSlot1WriteSPI(dscore, value);
119 dscore->ipc->memory.io[address >> 1] = value;
120 } else {
121 mLOG(DS_IO, GAME_ERROR, "Invalid cart access");
122 return 0;
123 }
124 break;
125 case DS_REG_ROMCNT_HI:
126 if (dscore->memory.slot1Access) {
127 DSSlot1ROMCNT cnt = value << 16;
128 cnt |= dscore->memory.io[(address - 2) >> 1];
129 cnt = DSSlot1Control(dscore->p, cnt);
130 value = cnt >> 16;
131 dscore->ipc->memory.io[address >> 1] = value;
132 } else {
133 mLOG(DS_IO, GAME_ERROR, "Invalid cart access");
134 return 0;
135 }
136 break;
137 case DS_REG_ROMCNT_LO:
138 case DS_REG_ROMCMD_0:
139 case DS_REG_ROMCMD_2:
140 case DS_REG_ROMCMD_4:
141 case DS_REG_ROMCMD_6:
142 if (dscore->memory.slot1Access) {
143 dscore->ipc->memory.io[address >> 1] = value;
144 } else {
145 mLOG(DS_IO, GAME_ERROR, "Invalid cart access");
146 return 0;
147 }
148 break;
149
150 // Interrupts
151 case DS_REG_IME:
152 DSWriteIME(dscore->cpu, dscore->memory.io, value);
153 break;
154 case 0x20A:
155 value = 0;
156 // Some bad interrupt libraries will write to this
157 break;
158 case DS_REG_IF_LO:
159 case DS_REG_IF_HI:
160 value = dscore->memory.io[address >> 1] & ~value;
161 DSGXUpdateGXSTAT(&dscore->p->gx);
162 break;
163 default:
164 return 0;
165 }
166 return value | 0x10000;
167}
168
169uint32_t DSIOWrite32(struct DSCommon* dscore, uint32_t address, uint32_t value) {
170 switch (address) {
171 case DS_REG_DMA0SAD_LO:
172 value = DSDMAWriteSAD(dscore, 0, value);
173 break;
174 case DS_REG_DMA1SAD_LO:
175 value = DSDMAWriteSAD(dscore, 1, value);
176 break;
177 case DS_REG_DMA2SAD_LO:
178 value = DSDMAWriteSAD(dscore, 2, value);
179 break;
180 case DS_REG_DMA3SAD_LO:
181 value = DSDMAWriteSAD(dscore, 3, value);
182 break;
183
184 case DS_REG_DMA0DAD_LO:
185 value = DSDMAWriteDAD(dscore, 0, value);
186 break;
187 case DS_REG_DMA1DAD_LO:
188 value = DSDMAWriteDAD(dscore, 1, value);
189 break;
190 case DS_REG_DMA2DAD_LO:
191 value = DSDMAWriteDAD(dscore, 2, value);
192 break;
193 case DS_REG_DMA3DAD_LO:
194 value = DSDMAWriteDAD(dscore, 3, value);
195 break;
196
197 case DS_REG_IPCFIFOSEND_LO:
198 DSIPCWriteFIFO(dscore, value);
199 break;
200 case DS_REG_IE_LO:
201 DSWriteIE(dscore->cpu, dscore->memory.io, value);
202 break;
203 }
204
205 return value;
206}
207
208static uint16_t DSIOReadExKeyInput(struct DS* ds) {
209 uint16_t input = 0;
210 if (ds->keyCallback) {
211 input = ds->keyCallback->readKeys(ds->keyCallback);
212 } else if (ds->keySource) {
213 input = *ds->keySource;
214 }
215 input = ~(input >> 10) & 0x3;
216 input |= 0x3C;
217 input |= ds->memory.io7[DS7_REG_EXTKEYIN >> 1] & 0xC0;
218 return input;
219}
220
221static uint16_t DSIOReadKeyInput(struct DS* ds) {
222 uint16_t input = 0;
223 if (ds->keyCallback) {
224 input = ds->keyCallback->readKeys(ds->keyCallback);
225 } else if (ds->keySource) {
226 input = *ds->keySource;
227 }
228 // TODO: Put back
229 /*if (!dscore->p->allowOpposingDirections) {
230 unsigned rl = input & 0x030;
231 unsigned ud = input & 0x0C0;
232 input &= 0x30F;
233 if (rl != 0x030) {
234 input |= rl;
235 }
236 if (ud != 0x0C0) {
237 input |= ud;
238 }
239 }*/
240 return ~input & 0x3FF;
241}
242
243static void DSIOUpdateTimer(struct DSCommon* dscore, uint32_t address) {
244 switch (address) {
245 case DS_REG_TM0CNT_LO:
246 GBATimerUpdateRegisterInternal(&dscore->timers[0], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
247 break;
248 case DS_REG_TM1CNT_LO:
249 GBATimerUpdateRegisterInternal(&dscore->timers[1], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
250 break;
251 case DS_REG_TM2CNT_LO:
252 GBATimerUpdateRegisterInternal(&dscore->timers[2], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
253 break;
254 case DS_REG_TM3CNT_LO:
255 GBATimerUpdateRegisterInternal(&dscore->timers[3], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
256 break;
257 }
258}
259
260void DS7IOInit(struct DS* ds) {
261 memset(ds->memory.io7, 0, sizeof(ds->memory.io7));
262 ds->memory.io7[DS_REG_IPCFIFOCNT >> 1] = 0x0101;
263 ds->memory.io7[DS_REG_POSTFLG >> 1] = 0x0001;
264 ds->memory.io7[DS7_REG_EXTKEYIN >> 1] = 0x007F;
265}
266
267void DS7IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
268 switch (address) {
269 case DS7_REG_SPICNT:
270 value &= 0xCF83;
271 value = DSSPIWriteControl(ds, value);
272 break;
273 case DS7_REG_SPIDATA:
274 DSSPIWrite(ds, value);
275 break;
276 case DS7_REG_RTC:
277 value = DSWriteRTC(ds, value);
278 break;
279 case DS7_REG_SOUND0CNT_LO:
280 case DS7_REG_SOUND1CNT_LO:
281 case DS7_REG_SOUND2CNT_LO:
282 case DS7_REG_SOUND3CNT_LO:
283 case DS7_REG_SOUND4CNT_LO:
284 case DS7_REG_SOUND5CNT_LO:
285 case DS7_REG_SOUND6CNT_LO:
286 case DS7_REG_SOUND7CNT_LO:
287 case DS7_REG_SOUND8CNT_LO:
288 case DS7_REG_SOUND9CNT_LO:
289 case DS7_REG_SOUNDACNT_LO:
290 case DS7_REG_SOUNDBCNT_LO:
291 case DS7_REG_SOUNDCCNT_LO:
292 case DS7_REG_SOUNDDCNT_LO:
293 case DS7_REG_SOUNDECNT_LO:
294 case DS7_REG_SOUNDFCNT_LO:
295 value &= 0x837F;
296 DSAudioWriteSOUNDCNT_LO(&ds->audio, (address - DS7_REG_SOUND0CNT_LO) >> 4, value);
297 break;
298 case DS7_REG_SOUND0CNT_HI:
299 case DS7_REG_SOUND1CNT_HI:
300 case DS7_REG_SOUND2CNT_HI:
301 case DS7_REG_SOUND3CNT_HI:
302 case DS7_REG_SOUND4CNT_HI:
303 case DS7_REG_SOUND5CNT_HI:
304 case DS7_REG_SOUND6CNT_HI:
305 case DS7_REG_SOUND7CNT_HI:
306 case DS7_REG_SOUND8CNT_HI:
307 case DS7_REG_SOUND9CNT_HI:
308 case DS7_REG_SOUNDACNT_HI:
309 case DS7_REG_SOUNDBCNT_HI:
310 case DS7_REG_SOUNDCCNT_HI:
311 case DS7_REG_SOUNDDCNT_HI:
312 case DS7_REG_SOUNDECNT_HI:
313 case DS7_REG_SOUNDFCNT_HI:
314 value &= 0xFF7F;
315 DSAudioWriteSOUNDCNT_HI(&ds->audio, (address - DS7_REG_SOUND0CNT_HI) >> 4, value);
316 break;
317 case DS7_REG_SOUND0TMR:
318 case DS7_REG_SOUND1TMR:
319 case DS7_REG_SOUND2TMR:
320 case DS7_REG_SOUND3TMR:
321 case DS7_REG_SOUND4TMR:
322 case DS7_REG_SOUND5TMR:
323 case DS7_REG_SOUND6TMR:
324 case DS7_REG_SOUND7TMR:
325 case DS7_REG_SOUND8TMR:
326 case DS7_REG_SOUND9TMR:
327 case DS7_REG_SOUNDATMR:
328 case DS7_REG_SOUNDBTMR:
329 case DS7_REG_SOUNDCTMR:
330 case DS7_REG_SOUNDDTMR:
331 case DS7_REG_SOUNDETMR:
332 case DS7_REG_SOUNDFTMR:
333 DSAudioWriteSOUNDTMR(&ds->audio, (address - DS7_REG_SOUND0TMR) >> 4, value);
334 break;
335 case DS7_REG_SOUND0PNT:
336 case DS7_REG_SOUND1PNT:
337 case DS7_REG_SOUND2PNT:
338 case DS7_REG_SOUND3PNT:
339 case DS7_REG_SOUND4PNT:
340 case DS7_REG_SOUND5PNT:
341 case DS7_REG_SOUND6PNT:
342 case DS7_REG_SOUND7PNT:
343 case DS7_REG_SOUND8PNT:
344 case DS7_REG_SOUND9PNT:
345 case DS7_REG_SOUNDAPNT:
346 case DS7_REG_SOUNDBPNT:
347 case DS7_REG_SOUNDCPNT:
348 case DS7_REG_SOUNDDPNT:
349 case DS7_REG_SOUNDEPNT:
350 case DS7_REG_SOUNDFPNT:
351 DSAudioWriteSOUNDPNT(&ds->audio, (address - DS7_REG_SOUND0PNT) >> 4, value);
352 break;
353 default:
354 {
355 uint32_t v2 = DSIOWrite(&ds->ds7, address, value);
356 if (v2 & 0x10000) {
357 value = v2;
358 break;
359 } else if (v2 & 0x20000) {
360 return;
361 }
362 }
363 if (address >= DS7_IO_BASE_WIFI && address < DS7_IO_END_WIFI) {
364 DSWifiWriteIO(ds, address & 0x7FFF, value);
365 return;
366 }
367 mLOG(DS_IO, STUB, "Stub DS7 I/O register write: %06X:%04X", address, value);
368 if (address >= DS7_REG_MAX) {
369 mLOG(DS_IO, GAME_ERROR, "Write to unused DS7 I/O register: %06X:%04X", address, value);
370 return;
371 }
372 break;
373 }
374 ds->memory.io7[address >> 1] = value;
375}
376
377void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
378 if (address == DS7_REG_HALTCNT) {
379 _DSHaltCNT(&ds->ds7, value);
380 return;
381 }
382 if (address < DS7_REG_MAX) {
383 uint16_t value16 = value << (8 * (address & 1));
384 value16 |= (ds->ds7.memory.io[(address & 0xFFF) >> 1]) & ~(0xFF << (8 * (address & 1)));
385 DS7IOWrite(ds, address & 0xFFFFFFFE, value16);
386 } else {
387 mLOG(DS, STUB, "Writing to unknown DS7 register: %08X:%02X", address, value);
388 }
389}
390
391void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
392 switch (address) {
393 case DS_REG_DMA0SAD_LO:
394 case DS_REG_DMA1SAD_LO:
395 case DS_REG_DMA2SAD_LO:
396 case DS_REG_DMA3SAD_LO:
397 case DS_REG_DMA0DAD_LO:
398 case DS_REG_DMA1DAD_LO:
399 case DS_REG_DMA2DAD_LO:
400 case DS_REG_DMA3DAD_LO:
401 case DS_REG_IPCFIFOSEND_LO:
402 case DS_REG_IE_LO:
403 value = DSIOWrite32(&ds->ds7, address, value);
404 break;
405
406 case DS_REG_DMA0CNT_LO:
407 DS7DMAWriteCNT(&ds->ds7, 0, value);
408 break;
409 case DS_REG_DMA1CNT_LO:
410 DS7DMAWriteCNT(&ds->ds7, 1, value);
411 break;
412 case DS_REG_DMA2CNT_LO:
413 DS7DMAWriteCNT(&ds->ds7, 2, value);
414 break;
415 case DS_REG_DMA3CNT_LO:
416 DS7DMAWriteCNT(&ds->ds7, 3, value);
417 break;
418
419 case DS7_REG_SOUND0SAD_LO:
420 case DS7_REG_SOUND1SAD_LO:
421 case DS7_REG_SOUND2SAD_LO:
422 case DS7_REG_SOUND3SAD_LO:
423 case DS7_REG_SOUND4SAD_LO:
424 case DS7_REG_SOUND5SAD_LO:
425 case DS7_REG_SOUND6SAD_LO:
426 case DS7_REG_SOUND7SAD_LO:
427 case DS7_REG_SOUND8SAD_LO:
428 case DS7_REG_SOUND9SAD_LO:
429 case DS7_REG_SOUNDASAD_LO:
430 case DS7_REG_SOUNDBSAD_LO:
431 case DS7_REG_SOUNDCSAD_LO:
432 case DS7_REG_SOUNDDSAD_LO:
433 case DS7_REG_SOUNDESAD_LO:
434 case DS7_REG_SOUNDFSAD_LO:
435 DSAudioWriteSOUNDSAD(&ds->audio, (address - DS7_REG_SOUND0SAD_LO) >> 4, value);
436 break;
437
438 case DS7_REG_SOUND0LEN_LO:
439 case DS7_REG_SOUND1LEN_LO:
440 case DS7_REG_SOUND2LEN_LO:
441 case DS7_REG_SOUND3LEN_LO:
442 case DS7_REG_SOUND4LEN_LO:
443 case DS7_REG_SOUND5LEN_LO:
444 case DS7_REG_SOUND6LEN_LO:
445 case DS7_REG_SOUND7LEN_LO:
446 case DS7_REG_SOUND8LEN_LO:
447 case DS7_REG_SOUND9LEN_LO:
448 case DS7_REG_SOUNDALEN_LO:
449 case DS7_REG_SOUNDBLEN_LO:
450 case DS7_REG_SOUNDCLEN_LO:
451 case DS7_REG_SOUNDDLEN_LO:
452 case DS7_REG_SOUNDELEN_LO:
453 case DS7_REG_SOUNDFLEN_LO:
454 value &= 0x3FFFFF;
455 DSAudioWriteSOUNDLEN(&ds->audio, (address - DS7_REG_SOUND0LEN_LO) >> 4, value);
456 break;
457
458 default:
459 DS7IOWrite(ds, address, value & 0xFFFF);
460 DS7IOWrite(ds, address | 2, value >> 16);
461 return;
462 }
463 ds->ds7.memory.io[address >> 1] = value;
464 ds->ds7.memory.io[(address >> 1) + 1] = value >> 16;
465}
466
467uint16_t DS7IORead(struct DS* ds, uint32_t address) {
468 switch (address) {
469 case DS_REG_TM0CNT_LO:
470 case DS_REG_TM1CNT_LO:
471 case DS_REG_TM2CNT_LO:
472 case DS_REG_TM3CNT_LO:
473 DSIOUpdateTimer(&ds->ds7, address);
474 break;
475 case DS_REG_KEYINPUT:
476 return DSIOReadKeyInput(ds);
477 case DS7_REG_EXTKEYIN:
478 return DSIOReadExKeyInput(ds);
479 case DS_REG_VCOUNT:
480 case DS_REG_DMA0FILL_LO:
481 case DS_REG_DMA0FILL_HI:
482 case DS_REG_DMA1FILL_LO:
483 case DS_REG_DMA1FILL_HI:
484 case DS_REG_DMA2FILL_LO:
485 case DS_REG_DMA2FILL_HI:
486 case DS_REG_DMA3FILL_LO:
487 case DS_REG_DMA3FILL_HI:
488 case DS_REG_TM0CNT_HI:
489 case DS_REG_TM1CNT_HI:
490 case DS_REG_TM2CNT_HI:
491 case DS_REG_TM3CNT_HI:
492 case DS7_REG_SPICNT:
493 case DS7_REG_SPIDATA:
494 case DS_REG_IPCSYNC:
495 case DS_REG_IPCFIFOCNT:
496 case DS_REG_ROMCNT_LO:
497 case DS_REG_ROMCNT_HI:
498 case DS_REG_IME:
499 case 0x20A:
500 case DS_REG_IE_LO:
501 case DS_REG_IE_HI:
502 case DS_REG_IF_LO:
503 case DS_REG_IF_HI:
504 case DS_REG_POSTFLG:
505 case DS7_REG_SOUND0CNT_LO:
506 case DS7_REG_SOUND1CNT_LO:
507 case DS7_REG_SOUND2CNT_LO:
508 case DS7_REG_SOUND3CNT_LO:
509 case DS7_REG_SOUND4CNT_LO:
510 case DS7_REG_SOUND5CNT_LO:
511 case DS7_REG_SOUND6CNT_LO:
512 case DS7_REG_SOUND7CNT_LO:
513 case DS7_REG_SOUND8CNT_LO:
514 case DS7_REG_SOUND9CNT_LO:
515 case DS7_REG_SOUNDACNT_LO:
516 case DS7_REG_SOUNDBCNT_LO:
517 case DS7_REG_SOUNDCCNT_LO:
518 case DS7_REG_SOUNDDCNT_LO:
519 case DS7_REG_SOUNDECNT_LO:
520 case DS7_REG_SOUNDFCNT_LO:
521 case DS7_REG_SOUND0CNT_HI:
522 case DS7_REG_SOUND1CNT_HI:
523 case DS7_REG_SOUND2CNT_HI:
524 case DS7_REG_SOUND3CNT_HI:
525 case DS7_REG_SOUND4CNT_HI:
526 case DS7_REG_SOUND5CNT_HI:
527 case DS7_REG_SOUND6CNT_HI:
528 case DS7_REG_SOUND7CNT_HI:
529 case DS7_REG_SOUND8CNT_HI:
530 case DS7_REG_SOUND9CNT_HI:
531 case DS7_REG_SOUNDACNT_HI:
532 case DS7_REG_SOUNDBCNT_HI:
533 case DS7_REG_SOUNDCCNT_HI:
534 case DS7_REG_SOUNDDCNT_HI:
535 case DS7_REG_SOUNDECNT_HI:
536 case DS7_REG_SOUNDFCNT_HI:
537 // Handled transparently by the registers
538 break;
539 case DS_REG_AUXSPICNT:
540 case DS_REG_AUXSPIDATA:
541 if (ds->ds7.memory.slot1Access) {
542 break;
543 } else {
544 mLOG(DS_IO, GAME_ERROR, "Invalid cart access");
545 return 0;
546 }
547 default:
548 if (address >= DS7_IO_BASE_WIFI && address < DS7_IO_END_WIFI) {
549 return DSWifiReadIO(ds, address & 0x7FFF);
550 }
551 mLOG(DS_IO, STUB, "Stub DS7 I/O register read: %06X", address);
552 }
553 if (address < DS7_REG_MAX) {
554 return ds->memory.io7[address >> 1];
555 }
556
557 return 0;
558}
559
560uint32_t DS7IORead32(struct DS* ds, uint32_t address) {
561 switch (address) {
562 case DS_REG_IPCFIFORECV_LO:
563 return DSIPCReadFIFO(&ds->ds7);
564 case DS_REG_ROMDATA_0:
565 if (ds->ds7.memory.slot1Access) {
566 return DSSlot1Read(ds);
567 } else {
568 mLOG(DS_IO, GAME_ERROR, "Invalid cart access");
569 return 0;
570 }
571 default:
572 return DS7IORead(ds, address & 0x00FFFFFC) | (DS7IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
573 }
574}
575
576void DS9IOInit(struct DS* ds) {
577 memset(ds->memory.io9, 0, sizeof(ds->memory.io9));
578 ds->memory.io9[DS_REG_IPCFIFOCNT >> 1] = 0x0101;
579 ds->memory.io9[DS_REG_POSTFLG >> 1] = 0x0001;
580 ds->memory.io9[DS9_REG_GXSTAT_HI >> 1] = 0x0600;
581 DS9IOWrite(ds, DS9_REG_VRAMCNT_G, 0x0300);
582}
583
584void DS9IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
585 if ((address <= DS9_REG_A_BLDY && address > DS_REG_VCOUNT) || address == DS9_REG_A_DISPCNT_LO || address == DS9_REG_A_DISPCNT_HI || address == DS9_REG_A_MASTER_BRIGHT) {
586 value = ds->video.renderer->writeVideoRegister(ds->video.renderer, address, value);
587 } else if ((address >= DS9_REG_B_DISPCNT_LO && address <= DS9_REG_B_BLDY) || address == DS9_REG_B_MASTER_BRIGHT) {
588 value = ds->video.renderer->writeVideoRegister(ds->video.renderer, address, value);
589 } else if ((address >= DS9_REG_RDLINES_COUNT && address <= DS9_REG_VECMTX_RESULT_12) || address == DS9_REG_DISP3DCNT) {
590 value = DSGXWriteRegister(&ds->gx, address, value);
591 } else {
592 uint16_t oldValue;
593 switch (address) {
594 // Other video
595 case DS9_REG_DISPCAPCNT_LO:
596 value &= 0x1F1F;
597 break;
598 case DS9_REG_DISPCAPCNT_HI:
599 value &= 0xEF3F;
600 break;
601
602 // VRAM control
603 case DS9_REG_VRAMCNT_A:
604 case DS9_REG_VRAMCNT_C:
605 case DS9_REG_VRAMCNT_E:
606 oldValue = ds->memory.io9[address >> 1];
607 value &= 0x9F9F;
608 DSVideoConfigureVRAM(ds, address - DS9_REG_VRAMCNT_A, value & 0xFF, oldValue & 0xFF);
609 DSVideoConfigureVRAM(ds, address - DS9_REG_VRAMCNT_A + 1, value >> 8, oldValue >> 8);
610 break;
611 case DS9_REG_VRAMCNT_G:
612 oldValue = ds->memory.io9[address >> 1];
613 value &= 0x039F;
614 DSVideoConfigureVRAM(ds, 6, value & 0xFF, oldValue & 0xFF);
615 DSConfigureWRAM(&ds->memory, value >> 8);
616 break;
617 case DS9_REG_VRAMCNT_H:
618 oldValue = ds->memory.io9[address >> 1];
619 value &= 0x9F9F;
620 DSVideoConfigureVRAM(ds, 7, value & 0xFF, oldValue & 0xFF);
621 DSVideoConfigureVRAM(ds, 8, value >> 8, oldValue >> 8);
622 break;
623
624 case DS9_REG_EXMEMCNT:
625 value &= 0xE8FF;
626 DSConfigureExternalMemory(ds, value);
627 break;
628
629 // Math
630 case DS9_REG_DIVCNT:
631 value = _scheduleDiv(ds, value);
632 break;
633 case DS9_REG_DIV_NUMER_0:
634 case DS9_REG_DIV_NUMER_1:
635 case DS9_REG_DIV_NUMER_2:
636 case DS9_REG_DIV_NUMER_3:
637 case DS9_REG_DIV_DENOM_0:
638 case DS9_REG_DIV_DENOM_1:
639 case DS9_REG_DIV_DENOM_2:
640 case DS9_REG_DIV_DENOM_3:
641 ds->memory.io9[DS9_REG_DIVCNT >> 1] = _scheduleDiv(ds, ds->memory.io9[DS9_REG_DIVCNT >> 1]);
642 break;
643 case DS9_REG_SQRTCNT:
644 value = _scheduleSqrt(ds, value);
645 break;
646 case DS9_REG_SQRT_PARAM_0:
647 case DS9_REG_SQRT_PARAM_1:
648 case DS9_REG_SQRT_PARAM_2:
649 case DS9_REG_SQRT_PARAM_3:
650 ds->memory.io9[DS9_REG_SQRTCNT >> 1] = _scheduleSqrt(ds, ds->memory.io9[DS9_REG_SQRTCNT >> 1]);
651 break;
652
653 // High Video
654 case DS9_REG_POWCNT1:
655 value = ds->video.renderer->writeVideoRegister(ds->video.renderer, address, value);
656 break;
657
658 default:
659 {
660 uint32_t v2 = DSIOWrite(&ds->ds9, address, value);
661 if (v2 & 0x10000) {
662 value = v2;
663 break;
664 } else if (v2 & 0x20000) {
665 return;
666 }
667 }
668 mLOG(DS_IO, STUB, "Stub DS9 I/O register write: %06X:%04X", address, value);
669 if (address >= DS7_REG_MAX) {
670 mLOG(DS_IO, GAME_ERROR, "Write to unused DS9 I/O register: %06X:%04X", address, value);
671 return;
672 }
673 break;
674 }
675 }
676 ds->memory.io9[address >> 1] = value;
677}
678
679void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
680 if (address < DS9_REG_MAX) {
681 uint16_t value16 = value << (8 * (address & 1));
682 value16 |= (ds->memory.io9[(address & 0x1FFF) >> 1]) & ~(0xFF << (8 * (address & 1)));
683 DS9IOWrite(ds, address & 0xFFFFFFFE, value16);
684 } else {
685 mLOG(DS, STUB, "Writing to unknown DS9 register: %08X:%02X", address, value);
686 }
687}
688
689void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
690 if ((address >= DS9_REG_RDLINES_COUNT && address <= DS9_REG_VECMTX_RESULT_12) || address == DS9_REG_DISP3DCNT) {
691 value = DSGXWriteRegister32(&ds->gx, address, value);
692 } else {
693 switch (address) {
694 case DS_REG_DMA0SAD_LO:
695 case DS_REG_DMA1SAD_LO:
696 case DS_REG_DMA2SAD_LO:
697 case DS_REG_DMA3SAD_LO:
698 case DS_REG_DMA0DAD_LO:
699 case DS_REG_DMA1DAD_LO:
700 case DS_REG_DMA2DAD_LO:
701 case DS_REG_DMA3DAD_LO:
702 case DS_REG_IPCFIFOSEND_LO:
703 case DS_REG_IE_LO:
704 value = DSIOWrite32(&ds->ds9, address, value);
705 break;
706
707 case DS_REG_DMA0CNT_LO:
708 DS9DMAWriteCNT(&ds->ds9, 0, value);
709 break;
710 case DS_REG_DMA1CNT_LO:
711 DS9DMAWriteCNT(&ds->ds9, 1, value);
712 break;
713 case DS_REG_DMA2CNT_LO:
714 DS9DMAWriteCNT(&ds->ds9, 2, value);
715 break;
716 case DS_REG_DMA3CNT_LO:
717 DS9DMAWriteCNT(&ds->ds9, 3, value);
718 break;
719
720 default:
721 DS9IOWrite(ds, address, value & 0xFFFF);
722 DS9IOWrite(ds, address | 2, value >> 16);
723 return;
724 }
725 }
726 ds->ds9.memory.io[address >> 1] = value;
727 ds->ds9.memory.io[(address >> 1) + 1] = value >> 16;
728}
729
730uint16_t DS9IORead(struct DS* ds, uint32_t address) {
731 switch (address) {
732 case DS_REG_TM0CNT_LO:
733 case DS_REG_TM1CNT_LO:
734 case DS_REG_TM2CNT_LO:
735 case DS_REG_TM3CNT_LO:
736 DSIOUpdateTimer(&ds->ds9, address);
737 break;
738 case DS_REG_KEYINPUT:
739 return DSIOReadKeyInput(ds);
740 case DS_REG_VCOUNT:
741 case DS_REG_DMA0FILL_LO:
742 case DS_REG_DMA0FILL_HI:
743 case DS_REG_DMA1FILL_LO:
744 case DS_REG_DMA1FILL_HI:
745 case DS_REG_DMA2FILL_LO:
746 case DS_REG_DMA2FILL_HI:
747 case DS_REG_DMA3FILL_LO:
748 case DS_REG_DMA3FILL_HI:
749 case DS_REG_TM0CNT_HI:
750 case DS_REG_TM1CNT_HI:
751 case DS_REG_TM2CNT_HI:
752 case DS_REG_TM3CNT_HI:
753 case DS_REG_IPCSYNC:
754 case DS_REG_IPCFIFOCNT:
755 case DS_REG_ROMCNT_LO:
756 case DS_REG_ROMCNT_HI:
757 case DS_REG_IME:
758 case 0x20A:
759 case DS_REG_IE_LO:
760 case DS_REG_IE_HI:
761 case DS_REG_IF_LO:
762 case DS_REG_IF_HI:
763 case DS9_REG_DIVCNT:
764 case DS9_REG_DIV_NUMER_0:
765 case DS9_REG_DIV_NUMER_1:
766 case DS9_REG_DIV_NUMER_2:
767 case DS9_REG_DIV_NUMER_3:
768 case DS9_REG_DIV_DENOM_0:
769 case DS9_REG_DIV_DENOM_1:
770 case DS9_REG_DIV_DENOM_2:
771 case DS9_REG_DIV_DENOM_3:
772 case DS9_REG_DIV_RESULT_0:
773 case DS9_REG_DIV_RESULT_1:
774 case DS9_REG_DIV_RESULT_2:
775 case DS9_REG_DIV_RESULT_3:
776 case DS9_REG_DIVREM_RESULT_0:
777 case DS9_REG_DIVREM_RESULT_1:
778 case DS9_REG_DIVREM_RESULT_2:
779 case DS9_REG_DIVREM_RESULT_3:
780 case DS9_REG_SQRTCNT:
781 case DS9_REG_SQRT_PARAM_0:
782 case DS9_REG_SQRT_PARAM_1:
783 case DS9_REG_SQRT_PARAM_2:
784 case DS9_REG_SQRT_PARAM_3:
785 case DS9_REG_SQRT_RESULT_LO:
786 case DS9_REG_SQRT_RESULT_HI:
787 case DS_REG_POSTFLG:
788 case DS9_REG_GXSTAT_LO:
789 case DS9_REG_GXSTAT_HI:
790 case DS9_REG_CLIPMTX_RESULT_00:
791 case DS9_REG_CLIPMTX_RESULT_01:
792 case DS9_REG_CLIPMTX_RESULT_02:
793 case DS9_REG_CLIPMTX_RESULT_03:
794 case DS9_REG_CLIPMTX_RESULT_04:
795 case DS9_REG_CLIPMTX_RESULT_05:
796 case DS9_REG_CLIPMTX_RESULT_06:
797 case DS9_REG_CLIPMTX_RESULT_07:
798 case DS9_REG_CLIPMTX_RESULT_08:
799 case DS9_REG_CLIPMTX_RESULT_09:
800 case DS9_REG_CLIPMTX_RESULT_0A:
801 case DS9_REG_CLIPMTX_RESULT_0B:
802 case DS9_REG_CLIPMTX_RESULT_0C:
803 case DS9_REG_CLIPMTX_RESULT_0D:
804 case DS9_REG_CLIPMTX_RESULT_0E:
805 case DS9_REG_CLIPMTX_RESULT_0F:
806 case DS9_REG_CLIPMTX_RESULT_10:
807 case DS9_REG_CLIPMTX_RESULT_11:
808 case DS9_REG_CLIPMTX_RESULT_12:
809 case DS9_REG_CLIPMTX_RESULT_13:
810 case DS9_REG_CLIPMTX_RESULT_14:
811 case DS9_REG_CLIPMTX_RESULT_15:
812 case DS9_REG_CLIPMTX_RESULT_16:
813 case DS9_REG_CLIPMTX_RESULT_17:
814 case DS9_REG_CLIPMTX_RESULT_18:
815 case DS9_REG_CLIPMTX_RESULT_19:
816 case DS9_REG_CLIPMTX_RESULT_1A:
817 case DS9_REG_CLIPMTX_RESULT_1B:
818 case DS9_REG_CLIPMTX_RESULT_1C:
819 case DS9_REG_CLIPMTX_RESULT_1D:
820 case DS9_REG_CLIPMTX_RESULT_1E:
821 case DS9_REG_CLIPMTX_RESULT_1F:
822 // Handled transparently by the registers
823 break;
824 case DS_REG_AUXSPICNT:
825 case DS_REG_AUXSPIDATA:
826 if (ds->ds9.memory.slot1Access) {
827 break;
828 } else {
829 mLOG(DS_IO, GAME_ERROR, "Invalid cart access");
830 return 0;
831 }
832 default:
833 mLOG(DS_IO, STUB, "Stub DS9 I/O register read: %06X", address);
834 }
835 if (address < DS9_REG_MAX) {
836 return ds->ds9.memory.io[address >> 1];
837 }
838 return 0;
839}
840
841uint32_t DS9IORead32(struct DS* ds, uint32_t address) {
842 switch (address) {
843 case DS_REG_IPCFIFORECV_LO:
844 return DSIPCReadFIFO(&ds->ds9);
845 case DS_REG_ROMDATA_0:
846 if (ds->ds9.memory.slot1Access) {
847 return DSSlot1Read(ds);
848 } else {
849 mLOG(DS_IO, GAME_ERROR, "Invalid cart access");
850 return 0;
851 }
852 default:
853 return DS9IORead(ds, address & 0x00FFFFFC) | (DS9IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
854 }
855}