src/lr35902/isa-lr35902.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-lr35902.h"
7
8#include "lr35902/emitter-lr35902.h"
9#include "lr35902/lr35902.h"
10
11#define DEFINE_INSTRUCTION_LR35902(NAME, BODY) \
12 static void _LR35902Instruction ## NAME (struct LR35902Core* cpu) { \
13 UNUSED(cpu); \
14 BODY; \
15 }
16
17DEFINE_INSTRUCTION_LR35902(NOP,);
18
19#define DEFINE_CONDITIONAL_INSTRUCTION_LR35902(NAME) \
20 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(, true) \
21 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(C, cpu->f.c) \
22 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(Z, cpu->f.z) \
23 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(NC, !cpu->f.c) \
24 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(NZ, !cpu->f.z)
25
26DEFINE_INSTRUCTION_LR35902(JPFinish,
27 if (cpu->condition) {
28 cpu->pc = (cpu->bus << 8) | cpu->index;
29 cpu->memory.setActiveRegion(cpu, cpu->pc);
30 cpu->executionState = LR35902_CORE_STALL;
31 })
32
33DEFINE_INSTRUCTION_LR35902(JPDelay,
34 cpu->executionState = LR35902_CORE_READ_PC;
35 cpu->instruction = _LR35902InstructionJPFinish;
36 cpu->index = cpu->bus;)
37
38#define DEFINE_JP_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
39 DEFINE_INSTRUCTION_LR35902(JP ## CONDITION_NAME, \
40 cpu->executionState = LR35902_CORE_READ_PC; \
41 cpu->instruction = _LR35902InstructionJPDelay; \
42 cpu->condition = CONDITION;)
43
44DEFINE_CONDITIONAL_INSTRUCTION_LR35902(JP);
45
46DEFINE_INSTRUCTION_LR35902(JPHL,
47 cpu->pc = LR35902ReadHL(cpu);
48 cpu->memory.setActiveRegion(cpu, cpu->pc);)
49
50DEFINE_INSTRUCTION_LR35902(JRFinish,
51 if (cpu->condition) {
52 cpu->pc += (int8_t) cpu->bus;
53 cpu->memory.setActiveRegion(cpu, cpu->pc);
54 cpu->executionState = LR35902_CORE_STALL;
55 })
56
57#define DEFINE_JR_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
58 DEFINE_INSTRUCTION_LR35902(JR ## CONDITION_NAME, \
59 cpu->executionState = LR35902_CORE_READ_PC; \
60 cpu->instruction = _LR35902InstructionJRFinish; \
61 cpu->condition = CONDITION;)
62
63DEFINE_CONDITIONAL_INSTRUCTION_LR35902(JR);
64
65DEFINE_INSTRUCTION_LR35902(CALLFinish,
66 if (cpu->condition) {
67 cpu->pc = (cpu->bus << 8) | cpu->index;
68 cpu->memory.setActiveRegion(cpu, cpu->pc);
69 cpu->executionState = LR35902_CORE_STALL;
70 })
71
72DEFINE_INSTRUCTION_LR35902(CALLUpdatePC,
73 cpu->executionState = LR35902_CORE_READ_PC;
74 cpu->index = cpu->bus;
75 cpu->instruction = _LR35902InstructionCALLFinish;)
76
77DEFINE_INSTRUCTION_LR35902(CALLUpdateSPL,
78 cpu->executionState = LR35902_CORE_READ_PC; \
79 cpu->instruction = _LR35902InstructionCALLUpdatePC;)
80
81DEFINE_INSTRUCTION_LR35902(CALLUpdateSPH,
82 cpu->index = cpu->sp + 1;
83 cpu->bus = (cpu->pc + 2) >> 8;
84 cpu->executionState = LR35902_CORE_MEMORY_STORE;
85 cpu->instruction = _LR35902InstructionCALLUpdateSPL;)
86
87#define DEFINE_CALL_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
88 DEFINE_INSTRUCTION_LR35902(CALL ## CONDITION_NAME, \
89 cpu->condition = CONDITION; \
90 if (CONDITION) { \
91 cpu->sp -= 2; /* TODO: Atomic incrementing? */ \
92 cpu->index = cpu->sp; \
93 cpu->bus = cpu->pc + 2; \
94 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
95 cpu->instruction = _LR35902InstructionCALLUpdateSPH; \
96 } else { \
97 cpu->executionState = LR35902_CORE_READ_PC; \
98 cpu->instruction = _LR35902InstructionCALLUpdatePC; \
99 })
100
101DEFINE_CONDITIONAL_INSTRUCTION_LR35902(CALL)
102
103DEFINE_INSTRUCTION_LR35902(RETUpdateSPL,
104 cpu->pc |= cpu->bus << 8;
105 cpu->sp += 2; /* TODO: Atomic incrementing? */
106 cpu->memory.setActiveRegion(cpu, cpu->pc);
107 cpu->executionState = LR35902_CORE_STALL;)
108
109DEFINE_INSTRUCTION_LR35902(RETUpdateSPH,
110 if (cpu->condition) {
111 cpu->index = cpu->sp + 1;
112 cpu->pc = cpu->bus;
113 cpu->executionState = LR35902_CORE_MEMORY_LOAD;
114 cpu->instruction = _LR35902InstructionRETUpdateSPL;
115 })
116
117#define DEFINE_RET_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
118 DEFINE_INSTRUCTION_LR35902(RET ## CONDITION_NAME, \
119 cpu->condition = CONDITION; \
120 cpu->index = cpu->sp; \
121 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
122 cpu->instruction = _LR35902InstructionRETUpdateSPH;)
123
124DEFINE_INSTRUCTION_LR35902(RETI,
125 cpu->condition = true;
126 cpu->index = cpu->sp;
127 cpu->executionState = LR35902_CORE_MEMORY_LOAD;
128 cpu->irqh.setInterrupts(cpu, true);
129 cpu->instruction = _LR35902InstructionRETUpdateSPH;)
130
131DEFINE_CONDITIONAL_INSTRUCTION_LR35902(RET)
132
133#define DEFINE_AND_INSTRUCTION_LR35902(NAME, OPERAND) \
134 DEFINE_INSTRUCTION_LR35902(AND ## NAME, \
135 cpu->a &= OPERAND; \
136 cpu->f.z = !cpu->a; \
137 cpu->f.n = 0; \
138 cpu->f.c = 0; \
139 cpu->f.h = 1;)
140
141#define DEFINE_XOR_INSTRUCTION_LR35902(NAME, OPERAND) \
142 DEFINE_INSTRUCTION_LR35902(XOR ## NAME, \
143 cpu->a ^= OPERAND; \
144 cpu->f.z = !cpu->a; \
145 cpu->f.n = 0; \
146 cpu->f.c = 0; \
147 cpu->f.h = 0;)
148
149#define DEFINE_OR_INSTRUCTION_LR35902(NAME, OPERAND) \
150 DEFINE_INSTRUCTION_LR35902(OR ## NAME, \
151 cpu->a |= OPERAND; \
152 cpu->f.z = !cpu->a; \
153 cpu->f.n = 0; \
154 cpu->f.c = 0; \
155 cpu->f.h = 0;)
156
157#define DEFINE_CP_INSTRUCTION_LR35902(NAME, OPERAND) \
158 DEFINE_INSTRUCTION_LR35902(CP ## NAME, \
159 int diff = cpu->a - OPERAND; \
160 cpu->f.n = 1; \
161 cpu->f.z = !diff; \
162 cpu->f.c = diff < 0; \
163 /* TODO: Find explanation of H flag */)
164
165#define DEFINE_LDB__INSTRUCTION_LR35902(NAME, OPERAND) \
166 DEFINE_INSTRUCTION_LR35902(LDB_ ## NAME, \
167 cpu->b = OPERAND;)
168
169#define DEFINE_LDC__INSTRUCTION_LR35902(NAME, OPERAND) \
170 DEFINE_INSTRUCTION_LR35902(LDC_ ## NAME, \
171 cpu->c = OPERAND;)
172
173#define DEFINE_LDD__INSTRUCTION_LR35902(NAME, OPERAND) \
174 DEFINE_INSTRUCTION_LR35902(LDD_ ## NAME, \
175 cpu->d = OPERAND;)
176
177#define DEFINE_LDE__INSTRUCTION_LR35902(NAME, OPERAND) \
178 DEFINE_INSTRUCTION_LR35902(LDE_ ## NAME, \
179 cpu->e = OPERAND;)
180
181#define DEFINE_LDH__INSTRUCTION_LR35902(NAME, OPERAND) \
182 DEFINE_INSTRUCTION_LR35902(LDH_ ## NAME, \
183 cpu->h = OPERAND;)
184
185#define DEFINE_LDL__INSTRUCTION_LR35902(NAME, OPERAND) \
186 DEFINE_INSTRUCTION_LR35902(LDL_ ## NAME, \
187 cpu->l = OPERAND;)
188
189#define DEFINE_LDHL__INSTRUCTION_LR35902(NAME, OPERAND) \
190 DEFINE_INSTRUCTION_LR35902(LDHL_ ## NAME, \
191 cpu->bus = OPERAND; \
192 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
193 cpu->instruction = _LR35902InstructionLDHL_Bus;)
194
195#define DEFINE_LDA__INSTRUCTION_LR35902(NAME, OPERAND) \
196 DEFINE_INSTRUCTION_LR35902(LDA_ ## NAME, \
197 cpu->a = OPERAND;)
198
199#define DEFINE_ALU_INSTRUCTION_LR35902_NOHL(NAME) \
200 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(A, cpu->a); \
201 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(B, cpu->b); \
202 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(C, cpu->c); \
203 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(D, cpu->d); \
204 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(E, cpu->e); \
205 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(H, cpu->h); \
206 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(L, cpu->l);
207
208DEFINE_INSTRUCTION_LR35902(LDHL_Bus, \
209 cpu->index = LR35902ReadHL(cpu); \
210 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
211 cpu->instruction = _LR35902InstructionNOP;)
212
213DEFINE_INSTRUCTION_LR35902(LDHL_, \
214 cpu->executionState = LR35902_CORE_READ_PC; \
215 cpu->instruction = _LR35902InstructionLDHL_Bus;)
216
217DEFINE_INSTRUCTION_LR35902(LDHL_SPDelay,
218 int diff = cpu->sp + (int8_t) cpu->bus;
219 LR35902WriteHL(cpu, diff);
220 cpu->executionState = LR35902_CORE_STALL;
221 cpu->f.z = 0;
222 cpu->f.n = 0;
223 cpu->f.c = !!(diff & 0xFFFF0000);
224 /* Figure out h flag*/)
225
226DEFINE_INSTRUCTION_LR35902(LDHL_SP,
227 cpu->executionState = LR35902_CORE_READ_PC;
228 cpu->instruction = _LR35902InstructionLDHL_SPDelay;)
229
230DEFINE_INSTRUCTION_LR35902(LDSP_HL,
231 cpu->sp = LR35902ReadHL(cpu);
232 cpu->executionState = LR35902_CORE_STALL;)
233
234#define DEFINE_ALU_INSTRUCTION_LR35902_MEM(NAME, REG) \
235 DEFINE_INSTRUCTION_LR35902(NAME ## REG, \
236 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
237 cpu->index = LR35902Read ## REG (cpu); \
238 cpu->instruction = _LR35902Instruction ## NAME ## Bus;)
239
240#define DEFINE_ALU_INSTRUCTION_LR35902(NAME) \
241 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(Bus, cpu->bus); \
242 DEFINE_ALU_INSTRUCTION_LR35902_MEM(NAME, HL) \
243 DEFINE_INSTRUCTION_LR35902(NAME, \
244 cpu->executionState = LR35902_CORE_READ_PC; \
245 cpu->instruction = _LR35902Instruction ## NAME ## Bus;) \
246 DEFINE_ALU_INSTRUCTION_LR35902_NOHL(NAME)
247
248DEFINE_ALU_INSTRUCTION_LR35902(AND);
249DEFINE_ALU_INSTRUCTION_LR35902(XOR);
250DEFINE_ALU_INSTRUCTION_LR35902(OR);
251DEFINE_ALU_INSTRUCTION_LR35902(CP);
252
253static void _LR35902InstructionLDB_Bus(struct LR35902Core*);
254static void _LR35902InstructionLDC_Bus(struct LR35902Core*);
255static void _LR35902InstructionLDD_Bus(struct LR35902Core*);
256static void _LR35902InstructionLDE_Bus(struct LR35902Core*);
257static void _LR35902InstructionLDH_Bus(struct LR35902Core*);
258static void _LR35902InstructionLDL_Bus(struct LR35902Core*);
259static void _LR35902InstructionLDHL_Bus(struct LR35902Core*);
260static void _LR35902InstructionLDA_Bus(struct LR35902Core*);
261
262#define DEFINE_ADD_INSTRUCTION_LR35902(NAME, OPERAND) \
263 DEFINE_INSTRUCTION_LR35902(ADD ## NAME, \
264 int diff = cpu->a + OPERAND; \
265 cpu->a = diff; \
266 cpu->f.n = 0; \
267 cpu->f.z = !diff; \
268 cpu->f.c = diff >= 0x100; \
269 /* TODO: Find explanation of H flag */)
270
271#define DEFINE_ADC_INSTRUCTION_LR35902(NAME, OPERAND) \
272 DEFINE_INSTRUCTION_LR35902(ADC ## NAME, \
273 int diff = cpu->a + OPERAND + cpu->f.c; \
274 cpu->a = diff; \
275 cpu->f.n = 0; \
276 cpu->f.z = !diff; \
277 cpu->f.c = diff > 0x100; \
278 /* TODO: Find explanation of H flag */)
279
280#define DEFINE_SUB_INSTRUCTION_LR35902(NAME, OPERAND) \
281 DEFINE_INSTRUCTION_LR35902(SUB ## NAME, \
282 int diff = cpu->a - OPERAND; \
283 cpu->a = diff; \
284 cpu->f.n = 1; \
285 cpu->f.z = !diff; \
286 cpu->f.c = diff < 0; \
287 /* TODO: Find explanation of H flag */)
288
289#define DEFINE_SBC_INSTRUCTION_LR35902(NAME, OPERAND) \
290 DEFINE_INSTRUCTION_LR35902(SBC ## NAME, \
291 int diff = cpu->a - OPERAND - cpu->f.c; \
292 cpu->a = diff; \
293 cpu->f.n = 1; \
294 cpu->f.z = !diff; \
295 cpu->f.c = diff < 0; \
296 /* TODO: Find explanation of H flag */)
297
298DEFINE_ALU_INSTRUCTION_LR35902(LDB_);
299DEFINE_ALU_INSTRUCTION_LR35902(LDC_);
300DEFINE_ALU_INSTRUCTION_LR35902(LDD_);
301DEFINE_ALU_INSTRUCTION_LR35902(LDE_);
302DEFINE_ALU_INSTRUCTION_LR35902(LDH_);
303DEFINE_ALU_INSTRUCTION_LR35902(LDL_);
304DEFINE_ALU_INSTRUCTION_LR35902_NOHL(LDHL_);
305DEFINE_ALU_INSTRUCTION_LR35902(LDA_);
306DEFINE_ALU_INSTRUCTION_LR35902_MEM(LDA_, BC);
307DEFINE_ALU_INSTRUCTION_LR35902_MEM(LDA_, DE);
308DEFINE_ALU_INSTRUCTION_LR35902(ADD);
309DEFINE_ALU_INSTRUCTION_LR35902(ADC);
310DEFINE_ALU_INSTRUCTION_LR35902(SUB);
311DEFINE_ALU_INSTRUCTION_LR35902(SBC);
312
313DEFINE_INSTRUCTION_LR35902(LDBCDelay, \
314 cpu->c = cpu->bus; \
315 cpu->executionState = LR35902_CORE_READ_PC; \
316 cpu->instruction = _LR35902InstructionLDB_Bus;)
317
318DEFINE_INSTRUCTION_LR35902(LDBC, \
319 cpu->executionState = LR35902_CORE_READ_PC; \
320 cpu->instruction = _LR35902InstructionLDBCDelay;)
321
322DEFINE_INSTRUCTION_LR35902(LDBC_A, \
323 cpu->index = LR35902ReadBC(cpu); \
324 cpu->bus = cpu->a; \
325 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
326 cpu->instruction = _LR35902InstructionNOP;)
327
328DEFINE_INSTRUCTION_LR35902(LDDEDelay, \
329 cpu->e = cpu->bus; \
330 cpu->executionState = LR35902_CORE_READ_PC; \
331 cpu->instruction = _LR35902InstructionLDD_Bus;)
332
333DEFINE_INSTRUCTION_LR35902(LDDE, \
334 cpu->executionState = LR35902_CORE_READ_PC; \
335 cpu->instruction = _LR35902InstructionLDDEDelay;)
336
337DEFINE_INSTRUCTION_LR35902(LDDE_A, \
338 cpu->index = LR35902ReadDE(cpu); \
339 cpu->bus = cpu->a; \
340 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
341 cpu->instruction = _LR35902InstructionNOP;)
342
343DEFINE_INSTRUCTION_LR35902(LDHLDelay, \
344 cpu->l = cpu->bus; \
345 cpu->executionState = LR35902_CORE_READ_PC; \
346 cpu->instruction = _LR35902InstructionLDH_Bus;)
347
348DEFINE_INSTRUCTION_LR35902(LDHL, \
349 cpu->executionState = LR35902_CORE_READ_PC; \
350 cpu->instruction = _LR35902InstructionLDHLDelay;)
351
352DEFINE_INSTRUCTION_LR35902(LDSPFinish, cpu->sp |= cpu->bus << 8;)
353
354DEFINE_INSTRUCTION_LR35902(LDSPDelay, \
355 cpu->sp = cpu->bus; \
356 cpu->executionState = LR35902_CORE_READ_PC; \
357 cpu->instruction = _LR35902InstructionLDSPFinish;)
358
359DEFINE_INSTRUCTION_LR35902(LDSP, \
360 cpu->executionState = LR35902_CORE_READ_PC; \
361 cpu->instruction = _LR35902InstructionLDSPDelay;)
362
363DEFINE_INSTRUCTION_LR35902(LDIHLA, \
364 cpu->index = LR35902ReadHL(cpu); \
365 LR35902WriteHL(cpu, cpu->index + 1); \
366 cpu->bus = cpu->a; \
367 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
368 cpu->instruction = _LR35902InstructionNOP;)
369
370DEFINE_INSTRUCTION_LR35902(LDDHLA, \
371 cpu->index = LR35902ReadHL(cpu); \
372 LR35902WriteHL(cpu, cpu->index - 1); \
373 cpu->bus = cpu->a; \
374 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
375 cpu->instruction = _LR35902InstructionNOP;)
376
377DEFINE_INSTRUCTION_LR35902(LDA_IHL, \
378 cpu->index = LR35902ReadHL(cpu); \
379 LR35902WriteHL(cpu, cpu->index + 1); \
380 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
381 cpu->instruction = _LR35902InstructionLDA_Bus;)
382
383DEFINE_INSTRUCTION_LR35902(LDA_DHL, \
384 cpu->index = LR35902ReadHL(cpu); \
385 LR35902WriteHL(cpu, cpu->index - 1); \
386 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
387 cpu->instruction = _LR35902InstructionLDA_Bus;)
388
389DEFINE_INSTRUCTION_LR35902(LDIAFinish, \
390 cpu->index |= cpu->bus << 8;
391 cpu->bus = cpu->a; \
392 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
393 cpu->instruction = _LR35902InstructionNOP;)
394
395DEFINE_INSTRUCTION_LR35902(LDIADelay, \
396 cpu->index = cpu->bus;
397 cpu->executionState = LR35902_CORE_READ_PC; \
398 cpu->instruction = _LR35902InstructionLDIAFinish;)
399
400DEFINE_INSTRUCTION_LR35902(LDIA, \
401 cpu->executionState = LR35902_CORE_READ_PC; \
402 cpu->instruction = _LR35902InstructionLDIADelay;)
403
404DEFINE_INSTRUCTION_LR35902(LDAIFinish, \
405 cpu->index |= cpu->bus << 8;
406 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
407 cpu->instruction = _LR35902InstructionLDA_Bus;)
408
409DEFINE_INSTRUCTION_LR35902(LDAIDelay, \
410 cpu->index = cpu->bus;
411 cpu->executionState = LR35902_CORE_READ_PC; \
412 cpu->instruction = _LR35902InstructionLDAIFinish;)
413
414DEFINE_INSTRUCTION_LR35902(LDAI, \
415 cpu->executionState = LR35902_CORE_READ_PC; \
416 cpu->instruction = _LR35902InstructionLDAIDelay;)
417
418DEFINE_INSTRUCTION_LR35902(LDAIOC, \
419 cpu->index = 0xFF00 | cpu->c; \
420 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
421 cpu->instruction = _LR35902InstructionLDA_Bus;)
422
423DEFINE_INSTRUCTION_LR35902(LDIOCA, \
424 cpu->index = 0xFF00 | cpu->c; \
425 cpu->bus = cpu->a; \
426 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
427 cpu->instruction = _LR35902InstructionNOP;)
428
429DEFINE_INSTRUCTION_LR35902(LDAIODelay, \
430 cpu->index = 0xFF00 | cpu->bus; \
431 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
432 cpu->instruction = _LR35902InstructionLDA_Bus;)
433
434DEFINE_INSTRUCTION_LR35902(LDAIO, \
435 cpu->executionState = LR35902_CORE_READ_PC; \
436 cpu->instruction = _LR35902InstructionLDAIODelay;)
437
438DEFINE_INSTRUCTION_LR35902(LDIOADelay, \
439 cpu->index = 0xFF00 | cpu->bus; \
440 cpu->bus = cpu->a; \
441 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
442 cpu->instruction = _LR35902InstructionNOP;)
443
444DEFINE_INSTRUCTION_LR35902(LDIOA, \
445 cpu->executionState = LR35902_CORE_READ_PC; \
446 cpu->instruction = _LR35902InstructionLDIOADelay;)
447
448#define DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(REG) \
449 DEFINE_INSTRUCTION_LR35902(INC ## REG, \
450 uint16_t reg = LR35902Read ## REG (cpu); \
451 LR35902Write ## REG (cpu, reg + 1); \
452 cpu->executionState = LR35902_CORE_STALL;) \
453 DEFINE_INSTRUCTION_LR35902(DEC ## REG, \
454 uint16_t reg = LR35902Read ## REG (cpu); \
455 LR35902Write ## REG (cpu, reg - 1); \
456 cpu->executionState = LR35902_CORE_STALL;)
457
458DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(BC);
459DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(DE);
460DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(HL);
461
462#define DEFINE_ADD_HL_INSTRUCTION_LR35902(REG, L, H) \
463 DEFINE_INSTRUCTION_LR35902(ADDHL_ ## REG ## Finish, \
464 int diff = H + cpu->h + cpu->f.c; \
465 cpu->h = diff; \
466 cpu->f.c = diff >= 0x100; \
467 cpu->f.n = 0; \
468 /* TODO: Find explanation of H flag */) \
469 DEFINE_INSTRUCTION_LR35902(ADDHL_ ## REG, \
470 int diff = L + cpu->l; \
471 cpu->l = diff; \
472 cpu->f.c = diff >= 0x100; \
473 cpu->executionState = LR35902_CORE_OP2; \
474 cpu->instruction = _LR35902InstructionADDHL_ ## REG ## Finish;)
475
476DEFINE_ADD_HL_INSTRUCTION_LR35902(BC, cpu->c, cpu->b);
477DEFINE_ADD_HL_INSTRUCTION_LR35902(DE, cpu->e, cpu->d);
478DEFINE_ADD_HL_INSTRUCTION_LR35902(HL, cpu->l, cpu->h);
479DEFINE_ADD_HL_INSTRUCTION_LR35902(SP, (cpu->sp & 0xFF), (cpu->sp >> 8));
480
481
482#define DEFINE_INC_INSTRUCTION_LR35902(NAME, OPERAND) \
483 DEFINE_INSTRUCTION_LR35902(INC ## NAME, \
484 int diff = OPERAND + 1; \
485 OPERAND = diff; \
486 cpu->f.n = 0; \
487 cpu->f.z = !diff; \
488 /* TODO: Find explanation of H flag */)
489
490#define DEFINE_DEC_INSTRUCTION_LR35902(NAME, OPERAND) \
491 DEFINE_INSTRUCTION_LR35902(DEC ## NAME, \
492 int diff = OPERAND - 1; \
493 OPERAND = diff; \
494 cpu->f.n = 1; \
495 cpu->f.z = !diff; \
496 /* TODO: Find explanation of H flag */)
497
498DEFINE_ALU_INSTRUCTION_LR35902_NOHL(INC);
499DEFINE_ALU_INSTRUCTION_LR35902_NOHL(DEC);
500
501DEFINE_INSTRUCTION_LR35902(INC_HLDelay,
502 int diff = cpu->bus + 1;
503 cpu->bus = diff;
504 cpu->f.n = 0;
505 cpu->f.z = !diff;
506 /* TODO: Find explanation of H flag */
507 cpu->instruction = _LR35902InstructionNOP;
508 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
509
510DEFINE_INSTRUCTION_LR35902(INC_HL,
511 cpu->index = LR35902ReadHL(cpu);
512 cpu->instruction = _LR35902InstructionINC_HLDelay;
513 cpu->executionState = LR35902_CORE_MEMORY_LOAD;)
514
515DEFINE_INSTRUCTION_LR35902(DEC_HLDelay,
516 int diff = cpu->bus - 1;
517 cpu->bus = diff;
518 cpu->f.n = 1;
519 cpu->f.z = !diff;
520 /* TODO: Find explanation of H flag */
521 cpu->instruction = _LR35902InstructionNOP;
522 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
523
524DEFINE_INSTRUCTION_LR35902(DEC_HL,
525 cpu->index = LR35902ReadHL(cpu);
526 cpu->instruction = _LR35902InstructionDEC_HLDelay;
527 cpu->executionState = LR35902_CORE_MEMORY_LOAD;)
528
529DEFINE_INSTRUCTION_LR35902(INCSP,
530 ++cpu->sp;
531 cpu->executionState = LR35902_CORE_STALL;)
532
533DEFINE_INSTRUCTION_LR35902(DECSP,
534 --cpu->sp;
535 cpu->executionState = LR35902_CORE_STALL;)
536
537DEFINE_INSTRUCTION_LR35902(SCF,
538 cpu->f.c = 1;
539 cpu->f.h = 0;
540 cpu->f.n = 0;)
541
542DEFINE_INSTRUCTION_LR35902(CCF,
543 cpu->f.c ^= 1;
544 cpu->f.h = 0;
545 cpu->f.n = 0;)
546
547DEFINE_INSTRUCTION_LR35902(CPL_,
548 cpu->a ^= 0xFF;
549 cpu->f.h = 1;
550 cpu->f.n = 1;)
551
552#define DEFINE_POPPUSH_INSTRUCTION_LR35902(REG, HH, H, L) \
553 DEFINE_INSTRUCTION_LR35902(POP ## REG ## Delay, \
554 cpu-> L = cpu->bus; \
555 cpu->index = cpu->sp; \
556 ++cpu->sp; \
557 cpu->instruction = _LR35902InstructionLD ## HH ## _Bus; \
558 cpu->executionState = LR35902_CORE_MEMORY_LOAD;) \
559 DEFINE_INSTRUCTION_LR35902(POP ## REG, \
560 cpu->index = cpu->sp; \
561 ++cpu->sp; \
562 cpu->instruction = _LR35902InstructionPOP ## REG ## Delay; \
563 cpu->executionState = LR35902_CORE_MEMORY_LOAD;) \
564 DEFINE_INSTRUCTION_LR35902(PUSH ## REG ## Finish, \
565 cpu->executionState = LR35902_CORE_STALL;) \
566 DEFINE_INSTRUCTION_LR35902(PUSH ## REG ## Delay, \
567 --cpu->sp; \
568 cpu->index = cpu->sp; \
569 cpu->bus = cpu-> L; \
570 cpu->instruction = _LR35902InstructionPUSH ## REG ## Finish; \
571 cpu->executionState = LR35902_CORE_MEMORY_STORE;) \
572 DEFINE_INSTRUCTION_LR35902(PUSH ## REG, \
573 --cpu->sp; \
574 cpu->index = cpu->sp; \
575 cpu->bus = cpu-> H; \
576 cpu->instruction = _LR35902InstructionPUSH ## REG ## Delay; \
577 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
578
579DEFINE_POPPUSH_INSTRUCTION_LR35902(BC, B, b, c);
580DEFINE_POPPUSH_INSTRUCTION_LR35902(DE, D, d, e);
581DEFINE_POPPUSH_INSTRUCTION_LR35902(HL, H, h, l);
582DEFINE_POPPUSH_INSTRUCTION_LR35902(AF, A, a, f.packed);
583
584#define DEFINE_CB_2_INSTRUCTION_LR35902(NAME, BODY) \
585 DEFINE_INSTRUCTION_LR35902(NAME ## B, uint8_t reg = cpu->b; BODY; cpu->b = reg) \
586 DEFINE_INSTRUCTION_LR35902(NAME ## C, uint8_t reg = cpu->c; BODY; cpu->c = reg) \
587 DEFINE_INSTRUCTION_LR35902(NAME ## D, uint8_t reg = cpu->d; BODY; cpu->d = reg) \
588 DEFINE_INSTRUCTION_LR35902(NAME ## E, uint8_t reg = cpu->e; BODY; cpu->e = reg) \
589 DEFINE_INSTRUCTION_LR35902(NAME ## H, uint8_t reg = cpu->h; BODY; cpu->h = reg) \
590 DEFINE_INSTRUCTION_LR35902(NAME ## L, uint8_t reg = cpu->l; BODY; cpu->l = reg) \
591 DEFINE_INSTRUCTION_LR35902(NAME ## HLDelay, \
592 uint8_t reg = cpu->bus; \
593 BODY; \
594 cpu->bus = reg; \
595 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
596 cpu->instruction = _LR35902InstructionNOP;) \
597 DEFINE_INSTRUCTION_LR35902(NAME ## HL, \
598 cpu->index = LR35902ReadHL(cpu); \
599 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
600 cpu->instruction = _LR35902Instruction ## NAME ## HLDelay;) \
601 DEFINE_INSTRUCTION_LR35902(NAME ## A, uint8_t reg = cpu->a; BODY; cpu->a = reg)
602
603#define DEFINE_CB_INSTRUCTION_LR35902(NAME, BODY) \
604 DEFINE_CB_2_INSTRUCTION_LR35902(NAME ## 0, uint8_t bit = 1; BODY) \
605 DEFINE_CB_2_INSTRUCTION_LR35902(NAME ## 1, uint8_t bit = 2; BODY) \
606 DEFINE_CB_2_INSTRUCTION_LR35902(NAME ## 2, uint8_t bit = 4; BODY) \
607 DEFINE_CB_2_INSTRUCTION_LR35902(NAME ## 3, uint8_t bit = 8; BODY) \
608 DEFINE_CB_2_INSTRUCTION_LR35902(NAME ## 4, uint8_t bit = 16; BODY) \
609 DEFINE_CB_2_INSTRUCTION_LR35902(NAME ## 5, uint8_t bit = 32; BODY) \
610 DEFINE_CB_2_INSTRUCTION_LR35902(NAME ## 6, uint8_t bit = 64; BODY) \
611 DEFINE_CB_2_INSTRUCTION_LR35902(NAME ## 7, uint8_t bit = 128; BODY)
612
613DEFINE_CB_INSTRUCTION_LR35902(BIT, cpu->f.n = 0; cpu->f.h = 1; cpu->f.z = !(reg & bit))
614DEFINE_CB_INSTRUCTION_LR35902(RES, reg &= ~bit)
615DEFINE_CB_INSTRUCTION_LR35902(SET, reg |= bit)
616
617#define DEFINE_CB_ALU_INSTRUCTION_LR35902(NAME, BODY) \
618 DEFINE_CB_2_INSTRUCTION_LR35902(NAME, \
619 BODY; \
620 cpu->f.n = 0; \
621 cpu->f.h = 0; \
622 cpu->f.z = !reg;)
623
624DEFINE_CB_ALU_INSTRUCTION_LR35902(RL, int wide = (reg << 1) | cpu->f.c; reg = wide; cpu->f.c = wide >> 8)
625DEFINE_CB_ALU_INSTRUCTION_LR35902(RLC, reg = (reg << 1) | (reg >> 7); cpu->f.c = reg & 1)
626DEFINE_CB_ALU_INSTRUCTION_LR35902(RR, int low = reg & 1; reg = (reg >> 1) | (cpu->f.c << 7); cpu->f.c = low)
627DEFINE_CB_ALU_INSTRUCTION_LR35902(RRC, int low = reg & 1; reg = (reg >> 1) | (low << 7); cpu->f.c = low)
628DEFINE_CB_ALU_INSTRUCTION_LR35902(SLA, cpu->f.c = reg >> 7; reg <<= 1)
629DEFINE_CB_ALU_INSTRUCTION_LR35902(SRA, reg = ((int8_t) reg) >> 1; cpu->f.c = 0)
630DEFINE_CB_ALU_INSTRUCTION_LR35902(SRL, cpu->f.c = reg & 1; reg >>= 1)
631DEFINE_CB_ALU_INSTRUCTION_LR35902(SWAP, reg = (reg << 4) | (reg >> 4); cpu->f.c = 0)
632
633DEFINE_INSTRUCTION_LR35902(RLA_,
634 int wide = (cpu->a << 1) | cpu->f.c;
635 cpu->a = wide;
636 cpu->f.z = 0;
637 cpu->f.h = 0;
638 cpu->f.n = 0;
639 cpu->f.c = wide >> 8;)
640
641DEFINE_INSTRUCTION_LR35902(RLCA_,
642 cpu->a = (cpu->a << 1) | (cpu->a >> 7);
643 cpu->f.z = 0;
644 cpu->f.h = 0;
645 cpu->f.n = 0;
646 cpu->f.c = cpu->a & 1;)
647
648DEFINE_INSTRUCTION_LR35902(RRA_,
649 int low = cpu->a & 1;
650 cpu->a = (cpu->a >> 1) | (cpu->f.c << 7);
651 cpu->f.z = 0;
652 cpu->f.h = 0;
653 cpu->f.n = 0;
654 cpu->f.c = cpu->f.c = low;)
655
656DEFINE_INSTRUCTION_LR35902(RRCA_,
657 int low = cpu->a & 1;
658 cpu->a = (cpu->a >> 1) | (low << 7);
659 cpu->f.z = 0;
660 cpu->f.h = 0;
661 cpu->f.n = 0;
662 cpu->f.c = low;)
663
664DEFINE_INSTRUCTION_LR35902(DI, cpu->irqh.setInterrupts(cpu, false));
665DEFINE_INSTRUCTION_LR35902(EI, cpu->irqh.setInterrupts(cpu, true));
666DEFINE_INSTRUCTION_LR35902(HALT, cpu->cycles = cpu->nextEvent);
667
668DEFINE_INSTRUCTION_LR35902(RST00, LR35902RaiseIRQ(cpu, 0x00));
669DEFINE_INSTRUCTION_LR35902(RST08, LR35902RaiseIRQ(cpu, 0x08));
670DEFINE_INSTRUCTION_LR35902(RST10, LR35902RaiseIRQ(cpu, 0x10));
671DEFINE_INSTRUCTION_LR35902(RST18, LR35902RaiseIRQ(cpu, 0x18));
672DEFINE_INSTRUCTION_LR35902(RST20, LR35902RaiseIRQ(cpu, 0x20));
673DEFINE_INSTRUCTION_LR35902(RST28, LR35902RaiseIRQ(cpu, 0x28));
674DEFINE_INSTRUCTION_LR35902(RST30, LR35902RaiseIRQ(cpu, 0x30));
675DEFINE_INSTRUCTION_LR35902(RST38, LR35902RaiseIRQ(cpu, 0x38));
676
677DEFINE_INSTRUCTION_LR35902(STUB, cpu->irqh.hitStub(cpu));
678
679static const LR35902Instruction _lr35902CBInstructionTable[0x100] = {
680 DECLARE_LR35902_CB_EMITTER_BLOCK(_LR35902Instruction)
681};
682
683DEFINE_INSTRUCTION_LR35902(CBDelegate, _lr35902CBInstructionTable[cpu->bus](cpu))
684
685DEFINE_INSTRUCTION_LR35902(CB, \
686 cpu->executionState = LR35902_CORE_READ_PC; \
687 cpu->instruction = _LR35902InstructionCBDelegate;)
688
689const LR35902Instruction _lr35902InstructionTable[0x100] = {
690 DECLARE_LR35902_EMITTER_BLOCK(_LR35902Instruction)
691};