src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-gpio.h"
4#include "gba-io.h"
5#include "hle-bios.h"
6
7#include <limits.h>
8#include <string.h>
9#include <sys/mman.h>
10
11static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
12static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count);
13
14static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
15static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
16static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
17static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
18static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
19static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
20static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
21
22void GBAMemoryInit(struct GBAMemory* memory) {
23 memory->d.load32 = GBALoad32;
24 memory->d.load16 = GBALoad16;
25 memory->d.loadU16 = GBALoadU16;
26 memory->d.load8 = GBALoad8;
27 memory->d.loadU8 = GBALoadU8;
28 memory->d.store32 = GBAStore32;
29 memory->d.store16 = GBAStore16;
30 memory->d.store8 = GBAStore8;
31
32 memory->bios = (uint32_t*) hleBios;
33 memory->fullBios = 0;
34 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
35 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
36 memory->rom = 0;
37 memory->gpio.p = memory->p;
38 memset(memory->io, 0, sizeof(memory->io));
39 memset(memory->dma, 0, sizeof(memory->dma));
40
41 if (!memory->wram || !memory->iwram) {
42 GBAMemoryDeinit(memory);
43 GBALog(memory->p, GBA_LOG_ERROR, "Could not map memory");
44 return;
45 }
46
47 int i;
48 for (i = 0; i < 16; ++i) {
49 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
50 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
51 memory->waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
52 memory->waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
53 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
54 memory->waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
55 }
56 for (; i < 256; ++i) {
57 memory->waitstates16[i] = 0;
58 memory->waitstatesSeq16[i] = 0;
59 memory->waitstatesPrefetch16[i] = 0;
60 memory->waitstates32[i] = 0;
61 memory->waitstatesSeq32[i] = 0;
62 memory->waitstatesPrefetch32[i] = 0;
63 }
64
65 memory->activeRegion = -1;
66 memory->d.activeRegion = 0;
67 memory->d.activeMask = 0;
68 memory->d.setActiveRegion = GBASetActiveRegion;
69 memory->d.activePrefetchCycles32 = 0;
70 memory->d.activePrefetchCycles16 = 0;
71 memory->biosPrefetch = 0;
72 memory->d.waitMultiple = GBAWaitMultiple;
73}
74
75void GBAMemoryDeinit(struct GBAMemory* memory) {
76 munmap(memory->wram, SIZE_WORKING_RAM);
77 munmap(memory->iwram, SIZE_WORKING_IRAM);
78 GBASavedataDeinit(&memory->savedata);
79}
80
81static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
82 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
83
84 int newRegion = address >> BASE_OFFSET;
85 if (newRegion == gbaMemory->activeRegion) {
86 return;
87 }
88 if (gbaMemory->activeRegion == REGION_BIOS) {
89 gbaMemory->biosPrefetch = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
90 }
91 gbaMemory->activeRegion = newRegion;
92 memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[gbaMemory->activeRegion];
93 memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[gbaMemory->activeRegion];
94 memory->activeNonseqCycles32 = gbaMemory->waitstates32[gbaMemory->activeRegion];
95 memory->activeNonseqCycles16 = gbaMemory->waitstates16[gbaMemory->activeRegion];
96 switch (address & ~OFFSET_MASK) {
97 case BASE_BIOS:
98 memory->activeRegion = gbaMemory->bios;
99 memory->activeMask = SIZE_BIOS - 1;
100 break;
101 case BASE_WORKING_RAM:
102 memory->activeRegion = gbaMemory->wram;
103 memory->activeMask = SIZE_WORKING_RAM - 1;
104 break;
105 case BASE_WORKING_IRAM:
106 memory->activeRegion = gbaMemory->iwram;
107 memory->activeMask = SIZE_WORKING_IRAM - 1;
108 break;
109 case BASE_CART0:
110 case BASE_CART0_EX:
111 case BASE_CART1:
112 case BASE_CART1_EX:
113 case BASE_CART2:
114 case BASE_CART2_EX:
115 memory->activeRegion = gbaMemory->rom;
116 memory->activeMask = SIZE_CART0 - 1;
117 break;
118 default:
119 memory->activeRegion = 0;
120 memory->activeMask = 0;
121 break;
122 }
123}
124
125int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
126 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
127 uint32_t value = 0;
128 int wait = 0;
129
130 switch (address & ~OFFSET_MASK) {
131 case BASE_BIOS:
132 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
133 if (address < SIZE_BIOS) {
134 LOAD_32(value, address, gbaMemory->bios);
135 } else {
136 value = 0;
137 }
138 } else {
139 value = gbaMemory->biosPrefetch;
140 }
141 break;
142 case BASE_WORKING_RAM:
143 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
144 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
145 break;
146 case BASE_WORKING_IRAM:
147 LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
148 break;
149 case BASE_IO:
150 value = GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
151 break;
152 case BASE_PALETTE_RAM:
153 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
154 break;
155 case BASE_VRAM:
156 LOAD_32(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
157 break;
158 case BASE_OAM:
159 LOAD_32(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
160 break;
161 case BASE_CART0:
162 case BASE_CART0_EX:
163 case BASE_CART1:
164 case BASE_CART1_EX:
165 case BASE_CART2:
166 case BASE_CART2_EX:
167 wait = gbaMemory->waitstates32[address >> BASE_OFFSET];
168 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
169 LOAD_32(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
170 }
171 break;
172 case BASE_CART_SRAM:
173 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
174 break;
175 default:
176 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
177 if (gbaMemory->p->cpu.executionMode == MODE_ARM) {
178 value = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
179 } else {
180 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_THUMB * 2, 0);
181 value |= value << 16;
182 }
183 break;
184 }
185
186
187 if (cycleCounter) {
188 *cycleCounter += 2 + wait;
189 }
190 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
191 int rotate = (address & 3) << 3;
192 return (value >> rotate) | (value << (32 - rotate));
193}
194
195uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
196 return GBALoad16(memory, address, cycleCounter);
197}
198
199int16_t GBALoad16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
200 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
201 uint16_t value = 0;
202 int wait = 0;
203
204 switch (address & ~OFFSET_MASK) {
205 case BASE_BIOS:
206 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
207 if (address < SIZE_BIOS) {
208 LOAD_16(value, address, gbaMemory->bios);
209 } else {
210 value = 0;
211 }
212 } else {
213 value = gbaMemory->biosPrefetch;
214 }
215 break;
216 case BASE_WORKING_RAM:
217 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
218 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
219 break;
220 case BASE_WORKING_IRAM:
221 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
222 break;
223 case BASE_IO:
224 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
225 break;
226 case BASE_PALETTE_RAM:
227 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
228 break;
229 case BASE_VRAM:
230 LOAD_16(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
231 break;
232 case BASE_OAM:
233 LOAD_16(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
234 break;
235 case BASE_CART0:
236 case BASE_CART0_EX:
237 case BASE_CART1:
238 case BASE_CART1_EX:
239 case BASE_CART2:
240 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
241 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
242 LOAD_16(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
243 }
244 break;
245 case BASE_CART2_EX:
246 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
247 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
248 value = GBASavedataReadEEPROM(&gbaMemory->savedata);
249 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
250 LOAD_16(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
251 }
252 break;
253 case BASE_CART_SRAM:
254 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
255 break;
256 default:
257 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
258 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0);
259 break;
260 }
261
262 if (cycleCounter) {
263 *cycleCounter += 2 + wait;
264 }
265 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
266 int rotate = (address & 1) << 3;
267 return (value >> rotate) | (value << (16 - rotate));
268}
269
270uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
271 return GBALoad8(memory, address, cycleCounter);
272}
273
274int8_t GBALoad8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
275 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
276 int8_t value = 0;
277 int wait = 0;
278
279 switch (address & ~OFFSET_MASK) {
280 case BASE_BIOS:
281 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
282 if (address < SIZE_BIOS) {
283 value = ((int8_t*) gbaMemory->bios)[address];
284 } else {
285 value = 0;
286 }
287 } else {
288 value = gbaMemory->biosPrefetch;
289 }
290 break;
291 case BASE_WORKING_RAM:
292 value = ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
293 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
294 break;
295 case BASE_WORKING_IRAM:
296 value = ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
297 break;
298 case BASE_IO:
299 value = (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
300 break;
301 case BASE_PALETTE_RAM:
302 value = ((int8_t*) gbaMemory->p->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
303 break;
304 case BASE_VRAM:
305 value = ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x0001FFFF];
306 break;
307 case BASE_OAM:
308 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
309 break;
310 case BASE_CART0:
311 case BASE_CART0_EX:
312 case BASE_CART1:
313 case BASE_CART1_EX:
314 case BASE_CART2:
315 case BASE_CART2_EX:
316 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
317 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
318 value = ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
319 }
320 break;
321 case BASE_CART_SRAM:
322 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
323 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
324 GBASavedataInitSRAM(&gbaMemory->savedata);
325 }
326 if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
327 value = gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
328 } else if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
329 value = GBASavedataReadFlash(&gbaMemory->savedata, address);
330 }
331 break;
332 default:
333 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
334 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0) >> ((address & 1) << 3);
335 break;
336 }
337
338 if (cycleCounter) {
339 *cycleCounter += 2 + wait;
340 }
341 return value;
342}
343
344void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value, int* cycleCounter) {
345 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
346 int wait = 0;
347
348 switch (address & ~OFFSET_MASK) {
349 case BASE_WORKING_RAM:
350 STORE_32(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
351 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
352 break;
353 case BASE_WORKING_IRAM:
354 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
355 break;
356 case BASE_IO:
357 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
358 break;
359 case BASE_PALETTE_RAM:
360 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
361 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
362 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
363 break;
364 case BASE_VRAM:
365 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
366 STORE_32(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
367 }
368 break;
369 case BASE_OAM:
370 STORE_32(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
371 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
372 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
373 break;
374 case BASE_CART0:
375 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
376 break;
377 case BASE_CART_SRAM:
378 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
379 break;
380 default:
381 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
382 break;
383 }
384
385 if (cycleCounter) {
386 *cycleCounter += 1 + wait;
387 }
388}
389
390void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value, int* cycleCounter) {
391 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
392 int wait = 0;
393
394 switch (address & ~OFFSET_MASK) {
395 case BASE_WORKING_RAM:
396 STORE_16(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
397 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
398 break;
399 case BASE_WORKING_IRAM:
400 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
401 break;
402 case BASE_IO:
403 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
404 break;
405 case BASE_PALETTE_RAM:
406 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
407 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
408 break;
409 case BASE_VRAM:
410 if ((address & OFFSET_MASK) < SIZE_VRAM) {
411 STORE_16(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
412 }
413 break;
414 case BASE_OAM:
415 STORE_16(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
416 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
417 break;
418 case BASE_CART0:
419 if (IS_GPIO_REGISTER(address & 0xFFFFFF)) {
420 uint32_t reg = address & 0xFFFFFF;
421 GBAGPIOWrite(&gbaMemory->gpio, reg, value);
422 } else {
423 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
424 }
425 break;
426 case BASE_CART2_EX:
427 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
428 GBASavedataInitEEPROM(&gbaMemory->savedata);
429 }
430 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
431 break;
432 case BASE_CART_SRAM:
433 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
434 break;
435 default:
436 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
437 break;
438 }
439
440 if (cycleCounter) {
441 *cycleCounter += 1 + wait;
442 }
443}
444
445void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value, int* cycleCounter) {
446 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
447 int wait = 0;
448
449 switch (address & ~OFFSET_MASK) {
450 case BASE_WORKING_RAM:
451 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
452 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
453 break;
454 case BASE_WORKING_IRAM:
455 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
456 break;
457 case BASE_IO:
458 GBAIOWrite8(gbaMemory->p, address & (SIZE_IO - 1), value);
459 break;
460 case BASE_PALETTE_RAM:
461 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
462 break;
463 case BASE_VRAM:
464 if (address >= 0x06018000) {
465 // TODO: check BG mode
466 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
467 break;
468 }
469 ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x1FFFE] = value;
470 ((int8_t*) gbaMemory->p->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
471 break;
472 case BASE_OAM:
473 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
474 break;
475 case BASE_CART0:
476 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
477 break;
478 case BASE_CART_SRAM:
479 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
480 if (address == SAVEDATA_FLASH_BASE) {
481 GBASavedataInitFlash(&gbaMemory->savedata);
482 } else {
483 GBASavedataInitSRAM(&gbaMemory->savedata);
484 }
485 }
486 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
487 GBASavedataWriteFlash(&gbaMemory->savedata, address, value);
488 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
489 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
490 }
491 wait = gbaMemory->waitstates16[REGION_CART_SRAM];
492 break;
493 default:
494 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
495 break;
496 }
497
498 if (cycleCounter) {
499 *cycleCounter += 1 + wait;
500 }
501}
502
503static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count) {
504 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
505 int wait = 1 + gbaMemory->waitstates32[startAddress >> BASE_OFFSET];
506 wait += (1 + gbaMemory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
507 return wait;
508}
509
510void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
511 int sram = parameters & 0x0003;
512 int ws0 = (parameters & 0x000C) >> 2;
513 int ws0seq = (parameters & 0x0010) >> 4;
514 int ws1 = (parameters & 0x0060) >> 5;
515 int ws1seq = (parameters & 0x0080) >> 7;
516 int ws2 = (parameters & 0x0300) >> 8;
517 int ws2seq = (parameters & 0x0400) >> 10;
518 int prefetch = parameters & 0x4000;
519
520 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
521 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
522 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
523 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
524
525 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
526 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
527 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
528
529 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
530 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
531 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
532
533 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
534 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
535 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
536
537 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
538 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
539 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
540
541 if (!prefetch) {
542 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
543 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
544 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
545
546 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
547 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
548 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
549 } else {
550 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
551 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
552 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
553
554 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
555 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
556 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
557 }
558
559 memory->d.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
560 memory->d.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
561 memory->d.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
562 memory->d.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
563}
564
565int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
566 struct GBADMA* dma;
567 int32_t test = INT_MAX;
568
569 dma = &memory->dma[0];
570 dma->nextIRQ -= cycles;
571 if (dma->enable && dma->doIrq && dma->nextIRQ) {
572 if (dma->nextIRQ <= 0) {
573 dma->nextIRQ = INT_MAX;
574 GBARaiseIRQ(memory->p, IRQ_DMA0);
575 } else if (dma->nextIRQ < test) {
576 test = dma->nextIRQ;
577 }
578 }
579
580 dma = &memory->dma[1];
581 dma->nextIRQ -= cycles;
582 if (dma->enable && dma->doIrq && dma->nextIRQ) {
583 if (dma->nextIRQ <= 0) {
584 dma->nextIRQ = INT_MAX;
585 GBARaiseIRQ(memory->p, IRQ_DMA1);
586 } else if (dma->nextIRQ < test) {
587 test = dma->nextIRQ;
588 }
589 }
590
591 dma = &memory->dma[2];
592 dma->nextIRQ -= cycles;
593 if (dma->enable && dma->doIrq && dma->nextIRQ) {
594 if (dma->nextIRQ <= 0) {
595 dma->nextIRQ = INT_MAX;
596 GBARaiseIRQ(memory->p, IRQ_DMA2);
597 } else if (dma->nextIRQ < test) {
598 test = dma->nextIRQ;
599 }
600 }
601
602 dma = &memory->dma[3];
603 dma->nextIRQ -= cycles;
604 if (dma->enable && dma->doIrq && dma->nextIRQ) {
605 if (dma->nextIRQ <= 0) {
606 dma->nextIRQ = INT_MAX;
607 GBARaiseIRQ(memory->p, IRQ_DMA3);
608 } else if (dma->nextIRQ < test) {
609 test = dma->nextIRQ;
610 }
611 }
612
613 return test;
614}
615
616void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
617 memory->dma[dma].source = address & 0xFFFFFFFE;
618}
619
620void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
621 memory->dma[dma].dest = address & 0xFFFFFFFE;
622}
623
624void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
625 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
626}
627
628uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
629 struct GBADMA* currentDma = &memory->dma[dma];
630 int wasEnabled = currentDma->enable;
631 currentDma->packed = control;
632 currentDma->nextIRQ = 0;
633
634 if (currentDma->drq) {
635 GBALog(memory->p, GBA_LOG_STUB, "DRQ not implemented");
636 }
637
638 if (!wasEnabled && currentDma->enable) {
639 currentDma->nextSource = currentDma->source;
640 currentDma->nextDest = currentDma->dest;
641 currentDma->nextCount = currentDma->count;
642 GBAMemoryScheduleDMA(memory, dma, currentDma);
643 }
644 // If the DMA has already occurred, this value might have changed since the function started
645 return currentDma->packed;
646};
647
648void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
649 switch (info->timing) {
650 case DMA_TIMING_NOW:
651 GBAMemoryServiceDMA(memory, number, info);
652 break;
653 case DMA_TIMING_HBLANK:
654 // Handled implicitly
655 break;
656 case DMA_TIMING_VBLANK:
657 // Handled implicitly
658 break;
659 case DMA_TIMING_CUSTOM:
660 switch (number) {
661 case 0:
662 GBALog(memory->p, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
663 break;
664 case 1:
665 case 2:
666 GBAAudioScheduleFifoDma(&memory->p->audio, number, info);
667 break;
668 case 3:
669 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
670 break;
671 }
672 }
673}
674
675void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
676 struct GBADMA* dma;
677 int i;
678 for (i = 0; i < 4; ++i) {
679 dma = &memory->dma[i];
680 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
681 GBAMemoryServiceDMA(memory, i, dma);
682 }
683 }
684}
685
686void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
687 struct GBADMA* dma;
688 int i;
689 for (i = 0; i < 4; ++i) {
690 dma = &memory->dma[i];
691 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
692 GBAMemoryServiceDMA(memory, i, dma);
693 }
694 }
695}
696
697void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
698 if (!info->enable) {
699 // There was a DMA scheduled that got canceled
700 return;
701 }
702
703 uint32_t width = info->width ? 4 : 2;
704 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
705 int destOffset = DMA_OFFSET[info->dstControl] * width;
706 int32_t wordsRemaining = info->nextCount;
707 uint32_t source = info->nextSource;
708 uint32_t dest = info->nextDest;
709 uint32_t sourceRegion = source >> BASE_OFFSET;
710 uint32_t destRegion = dest >> BASE_OFFSET;
711
712 if (width == 4) {
713 int32_t word;
714 source &= 0xFFFFFFFC;
715 dest &= 0xFFFFFFFC;
716 while (wordsRemaining--) {
717 word = memory->d.load32(&memory->d, source, 0);
718 memory->d.store32(&memory->d, dest, word, 0);
719 source += sourceOffset;
720 dest += destOffset;
721 }
722 } else {
723 uint16_t word;
724 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
725 while (wordsRemaining--) {
726 word = GBASavedataReadEEPROM(&memory->savedata);
727 memory->d.store16(&memory->d, dest, word, 0);
728 source += sourceOffset;
729 dest += destOffset;
730 }
731 } else if (destRegion == REGION_CART2_EX) {
732 if (memory->savedata.type == SAVEDATA_NONE) {
733 GBASavedataInitEEPROM(&memory->savedata);
734 }
735 while (wordsRemaining) {
736 word = memory->d.load16(&memory->d, source, 0);
737 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
738 source += sourceOffset;
739 dest += destOffset;
740 --wordsRemaining;
741 }
742 } else {
743 while (wordsRemaining--) {
744 word = memory->d.load16(&memory->d, source, 0);
745 memory->d.store16(&memory->d, dest, word, 0);
746 source += sourceOffset;
747 dest += destOffset;
748 }
749 }
750 }
751
752 if (info->doIrq) {
753 info->nextIRQ = memory->p->cpu.cycles + 2;
754 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
755 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
756 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
757 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
758 }
759
760 info->nextSource = source;
761 info->nextDest = dest;
762 info->nextCount = wordsRemaining;
763
764 if (!info->repeat) {
765 info->enable = 0;
766
767 // Clear the enable bit in memory
768 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
769 } else {
770 info->nextCount = info->count;
771 if (info->dstControl == DMA_INCREMENT_RELOAD) {
772 info->nextDest = info->dest;
773 }
774 GBAMemoryScheduleDMA(memory, number, info);
775 }
776}