src/gba/bios.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gba/bios.h>
7
8#include <mgba/internal/arm/isa-inlines.h>
9#include <mgba/internal/arm/macros.h>
10#include <mgba/internal/gba/gba.h>
11#include <mgba/internal/gba/io.h>
12#include <mgba/internal/gba/memory.h>
13#include <mgba-util/math.h>
14
15const uint32_t GBA_BIOS_CHECKSUM = 0xBAAE187F;
16const uint32_t GBA_DS_BIOS_CHECKSUM = 0xBAAE1880;
17
18mLOG_DEFINE_CATEGORY(GBA_BIOS, "GBA BIOS", "gba.bios");
19
20static void _unLz77(struct GBA* gba, int width);
21static void _unHuffman(struct GBA* gba);
22static void _unRl(struct GBA* gba, int width);
23static void _unFilter(struct GBA* gba, int inwidth, int outwidth);
24static void _unBitPack(struct GBA* gba);
25
26static int _mulWait(int32_t r) {
27 if ((r & 0xFFFFFF00) == 0xFFFFFF00 || !(r & 0xFFFFFF00)) {
28 return 1;
29 } else if ((r & 0xFFFF0000) == 0xFFFF0000 || !(r & 0xFFFF0000)) {
30 return 2;
31 } else if ((r & 0xFF000000) == 0xFF000000 || !(r & 0xFF000000)) {
32 return 3;
33 } else {
34 return 4;
35 }
36}
37
38static void _SoftReset(struct GBA* gba) {
39 struct ARMCore* cpu = gba->cpu;
40 ARMSetPrivilegeMode(cpu, MODE_IRQ);
41 cpu->spsr.packed = 0;
42 cpu->gprs[ARM_LR] = 0;
43 cpu->gprs[ARM_SP] = SP_BASE_IRQ;
44 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
45 cpu->spsr.packed = 0;
46 cpu->gprs[ARM_LR] = 0;
47 cpu->gprs[ARM_SP] = SP_BASE_SUPERVISOR;
48 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
49 cpu->gprs[ARM_LR] = 0;
50 cpu->gprs[ARM_SP] = SP_BASE_SYSTEM;
51 int8_t flag = ((int8_t*) gba->memory.iwram)[0x7FFA];
52 memset(((int8_t*) gba->memory.iwram) + SIZE_WORKING_IRAM - 0x200, 0, 0x200);
53 if (flag) {
54 cpu->gprs[ARM_PC] = BASE_WORKING_RAM;
55 } else {
56 cpu->gprs[ARM_PC] = BASE_CART0;
57 }
58 _ARMSetMode(cpu, MODE_ARM);
59 ARMWritePC(cpu);
60}
61
62static void _RegisterRamReset(struct GBA* gba) {
63 uint32_t registers = gba->cpu->gprs[0];
64 struct ARMCore* cpu = gba->cpu;
65 cpu->memory.store16(cpu, BASE_IO | REG_DISPCNT, 0x0080, 0);
66 if (registers & 0x01) {
67 memset(gba->memory.wram, 0, SIZE_WORKING_RAM);
68 }
69 if (registers & 0x02) {
70 memset(gba->memory.iwram, 0, SIZE_WORKING_IRAM - 0x200);
71 }
72 if (registers & 0x04) {
73 memset(gba->video.palette, 0, SIZE_PALETTE_RAM);
74 }
75 if (registers & 0x08) {
76 memset(gba->video.vram, 0, SIZE_VRAM);
77 }
78 if (registers & 0x10) {
79 memset(gba->video.oam.raw, 0, SIZE_OAM);
80 }
81 if (registers & 0x20) {
82 cpu->memory.store16(cpu, BASE_IO | REG_SIOCNT, 0x0000, 0);
83 cpu->memory.store16(cpu, BASE_IO | REG_RCNT, RCNT_INITIAL, 0);
84 cpu->memory.store16(cpu, BASE_IO | REG_SIOMLT_SEND, 0, 0);
85 cpu->memory.store16(cpu, BASE_IO | REG_JOYCNT, 0, 0);
86 cpu->memory.store32(cpu, BASE_IO | REG_JOY_RECV_LO, 0, 0);
87 cpu->memory.store32(cpu, BASE_IO | REG_JOY_TRANS_LO, 0, 0);
88 }
89 if (registers & 0x40) {
90 cpu->memory.store16(cpu, BASE_IO | REG_SOUND1CNT_LO, 0, 0);
91 cpu->memory.store16(cpu, BASE_IO | REG_SOUND1CNT_HI, 0, 0);
92 cpu->memory.store16(cpu, BASE_IO | REG_SOUND1CNT_X, 0, 0);
93 cpu->memory.store16(cpu, BASE_IO | REG_SOUND2CNT_LO, 0, 0);
94 cpu->memory.store16(cpu, BASE_IO | REG_SOUND2CNT_HI, 0, 0);
95 cpu->memory.store16(cpu, BASE_IO | REG_SOUND3CNT_LO, 0, 0);
96 cpu->memory.store16(cpu, BASE_IO | REG_SOUND3CNT_HI, 0, 0);
97 cpu->memory.store16(cpu, BASE_IO | REG_SOUND3CNT_X, 0, 0);
98 cpu->memory.store16(cpu, BASE_IO | REG_SOUND4CNT_LO, 0, 0);
99 cpu->memory.store16(cpu, BASE_IO | REG_SOUND4CNT_HI, 0, 0);
100 cpu->memory.store16(cpu, BASE_IO | REG_SOUNDCNT_LO, 0, 0);
101 cpu->memory.store16(cpu, BASE_IO | REG_SOUNDCNT_HI, 0, 0);
102 cpu->memory.store16(cpu, BASE_IO | REG_SOUNDCNT_X, 0, 0);
103 cpu->memory.store16(cpu, BASE_IO | REG_SOUNDBIAS, 0x200, 0);
104 memset(gba->audio.psg.ch3.wavedata32, 0, sizeof(gba->audio.psg.ch3.wavedata32));
105 }
106 if (registers & 0x80) {
107 cpu->memory.store16(cpu, BASE_IO | 0x04, 0, 0);
108 cpu->memory.store16(cpu, BASE_IO | 0x06, 0, 0);
109 cpu->memory.store16(cpu, BASE_IO | 0x08, 0, 0);
110 cpu->memory.store16(cpu, BASE_IO | 0x0A, 0, 0);
111 cpu->memory.store16(cpu, BASE_IO | 0x0C, 0, 0);
112 cpu->memory.store16(cpu, BASE_IO | 0x0E, 0, 0);
113 cpu->memory.store16(cpu, BASE_IO | 0x10, 0, 0);
114 cpu->memory.store16(cpu, BASE_IO | 0x12, 0, 0);
115 cpu->memory.store16(cpu, BASE_IO | 0x14, 0, 0);
116 cpu->memory.store16(cpu, BASE_IO | 0x16, 0, 0);
117 cpu->memory.store16(cpu, BASE_IO | 0x18, 0, 0);
118 cpu->memory.store16(cpu, BASE_IO | 0x1A, 0, 0);
119 cpu->memory.store16(cpu, BASE_IO | 0x1C, 0, 0);
120 cpu->memory.store16(cpu, BASE_IO | 0x1E, 0, 0);
121 cpu->memory.store16(cpu, BASE_IO | REG_BG2PA, 0x100, 0);
122 cpu->memory.store16(cpu, BASE_IO | REG_BG2PB, 0, 0);
123 cpu->memory.store16(cpu, BASE_IO | REG_BG2PC, 0, 0);
124 cpu->memory.store16(cpu, BASE_IO | REG_BG2PD, 0x100, 0);
125 cpu->memory.store32(cpu, BASE_IO | 0x28, 0, 0);
126 cpu->memory.store32(cpu, BASE_IO | 0x2C, 0, 0);
127 cpu->memory.store16(cpu, BASE_IO | REG_BG3PA, 0x100, 0);
128 cpu->memory.store16(cpu, BASE_IO | REG_BG3PB, 0, 0);
129 cpu->memory.store16(cpu, BASE_IO | REG_BG3PC, 0, 0);
130 cpu->memory.store16(cpu, BASE_IO | REG_BG3PD, 0x100, 0);
131 cpu->memory.store32(cpu, BASE_IO | 0x38, 0, 0);
132 cpu->memory.store32(cpu, BASE_IO | 0x3C, 0, 0);
133 cpu->memory.store16(cpu, BASE_IO | 0x40, 0, 0);
134 cpu->memory.store16(cpu, BASE_IO | 0x42, 0, 0);
135 cpu->memory.store16(cpu, BASE_IO | 0x44, 0, 0);
136 cpu->memory.store16(cpu, BASE_IO | 0x46, 0, 0);
137 cpu->memory.store16(cpu, BASE_IO | 0x48, 0, 0);
138 cpu->memory.store16(cpu, BASE_IO | 0x4A, 0, 0);
139 cpu->memory.store16(cpu, BASE_IO | 0x4C, 0, 0);
140 cpu->memory.store16(cpu, BASE_IO | 0x50, 0, 0);
141 cpu->memory.store16(cpu, BASE_IO | 0x52, 0, 0);
142 cpu->memory.store16(cpu, BASE_IO | 0x54, 0, 0);
143 cpu->memory.store16(cpu, BASE_IO | 0xB0, 0, 0);
144 cpu->memory.store16(cpu, BASE_IO | 0xB2, 0, 0);
145 cpu->memory.store16(cpu, BASE_IO | 0xB4, 0, 0);
146 cpu->memory.store16(cpu, BASE_IO | 0xB6, 0, 0);
147 cpu->memory.store16(cpu, BASE_IO | 0xB8, 0, 0);
148 cpu->memory.store16(cpu, BASE_IO | 0xBA, 0, 0);
149 cpu->memory.store16(cpu, BASE_IO | 0xBC, 0, 0);
150 cpu->memory.store16(cpu, BASE_IO | 0xBE, 0, 0);
151 cpu->memory.store16(cpu, BASE_IO | 0xC0, 0, 0);
152 cpu->memory.store16(cpu, BASE_IO | 0xC2, 0, 0);
153 cpu->memory.store16(cpu, BASE_IO | 0xC4, 0, 0);
154 cpu->memory.store16(cpu, BASE_IO | 0xC6, 0, 0);
155 cpu->memory.store16(cpu, BASE_IO | 0xC8, 0, 0);
156 cpu->memory.store16(cpu, BASE_IO | 0xCA, 0, 0);
157 cpu->memory.store16(cpu, BASE_IO | 0xCC, 0, 0);
158 cpu->memory.store16(cpu, BASE_IO | 0xCE, 0, 0);
159 cpu->memory.store16(cpu, BASE_IO | 0xD0, 0, 0);
160 cpu->memory.store16(cpu, BASE_IO | 0xD2, 0, 0);
161 cpu->memory.store16(cpu, BASE_IO | 0xD4, 0, 0);
162 cpu->memory.store16(cpu, BASE_IO | 0xD6, 0, 0);
163 cpu->memory.store16(cpu, BASE_IO | 0xD8, 0, 0);
164 cpu->memory.store16(cpu, BASE_IO | 0xDA, 0, 0);
165 cpu->memory.store16(cpu, BASE_IO | 0xDC, 0, 0);
166 cpu->memory.store16(cpu, BASE_IO | 0xDE, 0, 0);
167 cpu->memory.store16(cpu, BASE_IO | 0x100, 0, 0);
168 cpu->memory.store16(cpu, BASE_IO | 0x102, 0, 0);
169 cpu->memory.store16(cpu, BASE_IO | 0x104, 0, 0);
170 cpu->memory.store16(cpu, BASE_IO | 0x106, 0, 0);
171 cpu->memory.store16(cpu, BASE_IO | 0x108, 0, 0);
172 cpu->memory.store16(cpu, BASE_IO | 0x10A, 0, 0);
173 cpu->memory.store16(cpu, BASE_IO | 0x10C, 0, 0);
174 cpu->memory.store16(cpu, BASE_IO | 0x10E, 0, 0);
175 cpu->memory.store16(cpu, BASE_IO | 0x200, 0, 0);
176 cpu->memory.store16(cpu, BASE_IO | 0x202, 0xFFFF, 0);
177 cpu->memory.store16(cpu, BASE_IO | 0x204, 0, 0);
178 cpu->memory.store16(cpu, BASE_IO | 0x208, 0, 0);
179 }
180}
181
182static void _BgAffineSet(struct GBA* gba) {
183 struct ARMCore* cpu = gba->cpu;
184 int i = cpu->gprs[2];
185 float ox, oy;
186 float cx, cy;
187 float sx, sy;
188 float theta;
189 int offset = cpu->gprs[0];
190 int destination = cpu->gprs[1];
191 float a, b, c, d;
192 float rx, ry;
193 while (i--) {
194 // [ sx 0 0 ] [ cos(theta) -sin(theta) 0 ] [ 1 0 cx - ox ] [ A B rx ]
195 // [ 0 sy 0 ] * [ sin(theta) cos(theta) 0 ] * [ 0 1 cy - oy ] = [ C D ry ]
196 // [ 0 0 1 ] [ 0 0 1 ] [ 0 0 1 ] [ 0 0 1 ]
197 ox = (int32_t) cpu->memory.load32(cpu, offset, 0) / 256.f;
198 oy = (int32_t) cpu->memory.load32(cpu, offset + 4, 0) / 256.f;
199 cx = (int16_t) cpu->memory.load16(cpu, offset + 8, 0);
200 cy = (int16_t) cpu->memory.load16(cpu, offset + 10, 0);
201 sx = (int16_t) cpu->memory.load16(cpu, offset + 12, 0) / 256.f;
202 sy = (int16_t) cpu->memory.load16(cpu, offset + 14, 0) / 256.f;
203 theta = (cpu->memory.load16(cpu, offset + 16, 0) >> 8) / 128.f * M_PI;
204 offset += 20;
205 // Rotation
206 a = d = cosf(theta);
207 b = c = sinf(theta);
208 // Scale
209 a *= sx;
210 b *= -sx;
211 c *= sy;
212 d *= sy;
213 // Translate
214 rx = ox - (a * cx + b * cy);
215 ry = oy - (c * cx + d * cy);
216 cpu->memory.store16(cpu, destination, a * 256, 0);
217 cpu->memory.store16(cpu, destination + 2, b * 256, 0);
218 cpu->memory.store16(cpu, destination + 4, c * 256, 0);
219 cpu->memory.store16(cpu, destination + 6, d * 256, 0);
220 cpu->memory.store32(cpu, destination + 8, rx * 256, 0);
221 cpu->memory.store32(cpu, destination + 12, ry * 256, 0);
222 destination += 16;
223 }
224}
225
226static void _ObjAffineSet(struct GBA* gba) {
227 struct ARMCore* cpu = gba->cpu;
228 int i = cpu->gprs[2];
229 float sx, sy;
230 float theta;
231 int offset = cpu->gprs[0];
232 int destination = cpu->gprs[1];
233 int diff = cpu->gprs[3];
234 float a, b, c, d;
235 while (i--) {
236 // [ sx 0 ] [ cos(theta) -sin(theta) ] [ A B ]
237 // [ 0 sy ] * [ sin(theta) cos(theta) ] = [ C D ]
238 sx = (int16_t) cpu->memory.load16(cpu, offset, 0) / 256.f;
239 sy = (int16_t) cpu->memory.load16(cpu, offset + 2, 0) / 256.f;
240 theta = (cpu->memory.load16(cpu, offset + 4, 0) >> 8) / 128.f * M_PI;
241 offset += 8;
242 // Rotation
243 a = d = cosf(theta);
244 b = c = sinf(theta);
245 // Scale
246 a *= sx;
247 b *= -sx;
248 c *= sy;
249 d *= sy;
250 cpu->memory.store16(cpu, destination, a * 256, 0);
251 cpu->memory.store16(cpu, destination + diff, b * 256, 0);
252 cpu->memory.store16(cpu, destination + diff * 2, c * 256, 0);
253 cpu->memory.store16(cpu, destination + diff * 3, d * 256, 0);
254 destination += diff * 4;
255 }
256}
257
258static void _MidiKey2Freq(struct GBA* gba) {
259 struct ARMCore* cpu = gba->cpu;
260
261 int oldRegion = gba->memory.activeRegion;
262 gba->memory.activeRegion = REGION_BIOS;
263 uint32_t key = cpu->memory.load32(cpu, cpu->gprs[0] + 4, 0);
264 gba->memory.activeRegion = oldRegion;
265
266 cpu->gprs[0] = key / exp2f((180.f - cpu->gprs[1] - cpu->gprs[2] / 256.f) / 12.f);
267}
268
269static void _Div(struct GBA* gba, int32_t num, int32_t denom) {
270 struct ARMCore* cpu = gba->cpu;
271 if (denom != 0 && (denom != -1 || num != INT32_MIN)) {
272 div_t result = div(num, denom);
273 cpu->gprs[0] = result.quot;
274 cpu->gprs[1] = result.rem;
275 cpu->gprs[3] = abs(result.quot);
276 } else if (denom == 0) {
277 mLOG(GBA_BIOS, GAME_ERROR, "Attempting to divide %i by zero!", num);
278 // If abs(num) > 1, this should hang, but that would be painful to
279 // emulate in HLE, and no game will get into a state where it hangs...
280 cpu->gprs[0] = (num < 0) ? -1 : 1;
281 cpu->gprs[1] = num;
282 cpu->gprs[3] = 1;
283 } else {
284 mLOG(GBA_BIOS, GAME_ERROR, "Attempting to divide INT_MIN by -1!");
285 cpu->gprs[0] = INT32_MIN;
286 cpu->gprs[1] = 0;
287 cpu->gprs[3] = INT32_MIN;
288 }
289 int loops = clz32(denom) - clz32(num);
290 if (loops < 1) {
291 loops = 1;
292 }
293 cpu->cycles += 4 /* prologue */ + 13 * loops + 7 /* epilogue */;
294}
295
296static int16_t _ArcTan(int32_t i, int32_t* r1, int32_t* r3, int32_t* cycles) {
297 int currentCycles = 37;
298 currentCycles += _mulWait(i * i);
299 int32_t a = -((i * i) >> 14);
300 currentCycles += _mulWait(0xA9 * a);
301 int32_t b = ((0xA9 * a) >> 14) + 0x390;
302 currentCycles += _mulWait(b * a);
303 b = ((b * a) >> 14) + 0x91C;
304 currentCycles += _mulWait(b * a);
305 b = ((b * a) >> 14) + 0xFB6;
306 currentCycles += _mulWait(b * a);
307 b = ((b * a) >> 14) + 0x16AA;
308 currentCycles += _mulWait(b * a);
309 b = ((b * a) >> 14) + 0x2081;
310 currentCycles += _mulWait(b * a);
311 b = ((b * a) >> 14) + 0x3651;
312 currentCycles += _mulWait(b * a);
313 b = ((b * a) >> 14) + 0xA2F9;
314 if (r1) {
315 *r1 = a;
316 }
317 if (r3) {
318 *r3 = b;
319 }
320 *cycles += currentCycles;
321 return (i * b) >> 16;
322}
323
324static int16_t _ArcTan2(int32_t x, int32_t y, int32_t* r1, int32_t* cycles) {
325 if (!y) {
326 if (x >= 0) {
327 return 0;
328 }
329 return 0x8000;
330 }
331 if (!x) {
332 if (y >= 0) {
333 return 0x4000;
334 }
335 return 0xC000;
336 }
337 if (y >= 0) {
338 if (x >= 0) {
339 if (x >= y) {
340 return _ArcTan((y << 14) / x, r1, NULL, cycles);
341 }
342 } else if (-x >= y) {
343 return _ArcTan((y << 14) / x, r1, NULL, cycles) + 0x8000;
344 }
345 return 0x4000 - _ArcTan((x << 14) / y, r1, NULL, cycles);
346 } else {
347 if (x <= 0) {
348 if (-x > -y) {
349 return _ArcTan((y << 14) / x, r1, NULL, cycles) + 0x8000;
350 }
351 } else if (x >= -y) {
352 return _ArcTan((y << 14) / x, r1, NULL, cycles) + 0x10000;
353 }
354 return 0xC000 - _ArcTan((x << 14) / y, r1, NULL, cycles);
355 }
356}
357
358static int32_t _Sqrt(uint32_t x, int32_t* cycles) {
359 if (!x) {
360 *cycles += 53;
361 return 0;
362 }
363 int32_t currentCycles = 15;
364 uint32_t lower;
365 uint32_t upper = x;
366 uint32_t bound = 1;
367 while (bound < upper) {
368 upper >>= 1;
369 bound <<= 1;
370 currentCycles += 6;
371 }
372 while (true) {
373 currentCycles += 6;
374 upper = x;
375 uint32_t accum = 0;
376 lower = bound;
377 while (true) {
378 currentCycles += 5;
379 uint32_t oldLower = lower;
380 if (lower <= upper >> 1) {
381 lower <<= 1;
382 }
383 if (oldLower >= upper >> 1) {
384 break;
385 }
386 }
387 while (true) {
388 currentCycles += 8;
389 accum <<= 1;
390 if (upper >= lower) {
391 ++accum;
392 upper -= lower;
393 }
394 if (lower == bound) {
395 break;
396 }
397 lower >>= 1;
398 }
399 uint32_t oldBound = bound;
400 bound += accum;
401 bound >>= 1;
402 if (bound >= oldBound) {
403 bound = oldBound;
404 break;
405 }
406 }
407 *cycles += currentCycles;
408 return bound;
409}
410
411void GBASwi16(struct ARMCore* cpu, int immediate) {
412 struct GBA* gba = (struct GBA*) cpu->master;
413 mLOG(GBA_BIOS, DEBUG, "SWI: %02X r0: %08X r1: %08X r2: %08X r3: %08X",
414 immediate, cpu->gprs[0], cpu->gprs[1], cpu->gprs[2], cpu->gprs[3]);
415
416 switch (immediate) {
417 case 0xFA:
418 GBAPrintFlush(gba);
419 return;
420 }
421
422 if (gba->memory.fullBios) {
423 ARMRaiseSWI(cpu);
424 return;
425 }
426 switch (immediate) {
427 case GBA_SWI_SOFT_RESET:
428 _SoftReset(gba);
429 break;
430 case GBA_SWI_REGISTER_RAM_RESET:
431 _RegisterRamReset(gba);
432 break;
433 case GBA_SWI_HALT:
434 GBAHalt(gba);
435 break;
436 case GBA_SWI_STOP:
437 GBAStop(gba);
438 break;
439 case GBA_SWI_VBLANK_INTR_WAIT:
440 // VBlankIntrWait
441 // Fall through:
442 case GBA_SWI_INTR_WAIT:
443 // IntrWait
444 ARMRaiseSWI(cpu);
445 break;
446 case GBA_SWI_DIV:
447 _Div(gba, cpu->gprs[0], cpu->gprs[1]);
448 break;
449 case GBA_SWI_DIV_ARM:
450 _Div(gba, cpu->gprs[1], cpu->gprs[0]);
451 break;
452 case GBA_SWI_SQRT:
453 cpu->gprs[0] = _Sqrt(cpu->gprs[0], &cpu->cycles);
454 break;
455 case GBA_SWI_ARCTAN:
456 cpu->gprs[0] = _ArcTan(cpu->gprs[0], &cpu->gprs[1], &cpu->gprs[3], &cpu->cycles);
457 break;
458 case GBA_SWI_ARCTAN2:
459 cpu->gprs[0] = (uint16_t) _ArcTan2(cpu->gprs[0], cpu->gprs[1], &cpu->gprs[1], &cpu->cycles);
460 cpu->gprs[3] = 0x170;
461 break;
462 case GBA_SWI_CPU_SET:
463 case GBA_SWI_CPU_FAST_SET:
464 if (cpu->gprs[0] >> BASE_OFFSET < REGION_WORKING_RAM) {
465 mLOG(GBA_BIOS, GAME_ERROR, "Cannot CpuSet from BIOS");
466 break;
467 }
468 if (cpu->gprs[0] & (cpu->gprs[2] & (1 << 26) ? 3 : 1)) {
469 mLOG(GBA_BIOS, GAME_ERROR, "Misaligned CpuSet source");
470 }
471 if (cpu->gprs[1] & (cpu->gprs[2] & (1 << 26) ? 3 : 1)) {
472 mLOG(GBA_BIOS, GAME_ERROR, "Misaligned CpuSet destination");
473 }
474 ARMRaiseSWI(cpu);
475 break;
476 case GBA_SWI_GET_BIOS_CHECKSUM:
477 cpu->gprs[0] = GBA_BIOS_CHECKSUM;
478 cpu->gprs[1] = 1;
479 cpu->gprs[3] = SIZE_BIOS;
480 break;
481 case GBA_SWI_BG_AFFINE_SET:
482 _BgAffineSet(gba);
483 break;
484 case GBA_SWI_OBJ_AFFINE_SET:
485 _ObjAffineSet(gba);
486 break;
487 case GBA_SWI_BIT_UNPACK:
488 if (cpu->gprs[0] < BASE_WORKING_RAM) {
489 mLOG(GBA_BIOS, GAME_ERROR, "Bad BitUnPack source");
490 break;
491 }
492 switch (cpu->gprs[1] >> BASE_OFFSET) {
493 default:
494 mLOG(GBA_BIOS, GAME_ERROR, "Bad BitUnPack destination");
495 // Fall through
496 case REGION_WORKING_RAM:
497 case REGION_WORKING_IRAM:
498 case REGION_VRAM:
499 _unBitPack(gba);
500 break;
501 }
502 break;
503 case GBA_SWI_LZ77_UNCOMP_WRAM:
504 case GBA_SWI_LZ77_UNCOMP_VRAM:
505 if (cpu->gprs[0] < BASE_WORKING_RAM) {
506 mLOG(GBA_BIOS, GAME_ERROR, "Bad LZ77 source");
507 break;
508 }
509 switch (cpu->gprs[1] >> BASE_OFFSET) {
510 default:
511 mLOG(GBA_BIOS, GAME_ERROR, "Bad LZ77 destination");
512 // Fall through
513 case REGION_WORKING_RAM:
514 case REGION_WORKING_IRAM:
515 case REGION_VRAM:
516 _unLz77(gba, immediate == GBA_SWI_LZ77_UNCOMP_WRAM ? 1 : 2);
517 break;
518 }
519 break;
520 case GBA_SWI_HUFFMAN_UNCOMP:
521 if (cpu->gprs[0] < BASE_WORKING_RAM) {
522 mLOG(GBA_BIOS, GAME_ERROR, "Bad Huffman source");
523 break;
524 }
525 switch (cpu->gprs[1] >> BASE_OFFSET) {
526 default:
527 mLOG(GBA_BIOS, GAME_ERROR, "Bad Huffman destination");
528 // Fall through
529 case REGION_WORKING_RAM:
530 case REGION_WORKING_IRAM:
531 case REGION_VRAM:
532 _unHuffman(gba);
533 break;
534 }
535 break;
536 case GBA_SWI_RL_UNCOMP_WRAM:
537 case GBA_SWI_RL_UNCOMP_VRAM:
538 if (cpu->gprs[0] < BASE_WORKING_RAM) {
539 mLOG(GBA_BIOS, GAME_ERROR, "Bad RL source");
540 break;
541 }
542 switch (cpu->gprs[1] >> BASE_OFFSET) {
543 default:
544 mLOG(GBA_BIOS, GAME_ERROR, "Bad RL destination");
545 // Fall through
546 case REGION_WORKING_RAM:
547 case REGION_WORKING_IRAM:
548 case REGION_VRAM:
549 _unRl(gba, immediate == GBA_SWI_RL_UNCOMP_WRAM ? 1 : 2);
550 break;
551 }
552 break;
553 case GBA_SWI_DIFF_8BIT_UNFILTER_WRAM:
554 case GBA_SWI_DIFF_8BIT_UNFILTER_VRAM:
555 case GBA_SWI_DIFF_16BIT_UNFILTER:
556 if (cpu->gprs[0] < BASE_WORKING_RAM) {
557 mLOG(GBA_BIOS, GAME_ERROR, "Bad UnFilter source");
558 break;
559 }
560 switch (cpu->gprs[1] >> BASE_OFFSET) {
561 default:
562 mLOG(GBA_BIOS, GAME_ERROR, "Bad UnFilter destination");
563 // Fall through
564 case REGION_WORKING_RAM:
565 case REGION_WORKING_IRAM:
566 case REGION_VRAM:
567 _unFilter(gba, immediate == GBA_SWI_DIFF_16BIT_UNFILTER ? 2 : 1, immediate == GBA_SWI_DIFF_8BIT_UNFILTER_WRAM ? 1 : 2);
568 break;
569 }
570 break;
571 case GBA_SWI_SOUND_BIAS:
572 // SoundBias is mostly meaningless here
573 mLOG(GBA_BIOS, STUB, "Stub software interrupt: SoundBias (19)");
574 break;
575 case GBA_SWI_MIDI_KEY_2_FREQ:
576 _MidiKey2Freq(gba);
577 break;
578 case GBA_SWI_SOUND_DRIVER_GET_JUMP_LIST:
579 ARMRaiseSWI(cpu);
580 break;
581 default:
582 mLOG(GBA_BIOS, STUB, "Stub software interrupt: %02X", immediate);
583 }
584 gba->cpu->cycles += 45 + cpu->memory.activeNonseqCycles16 /* 8 bit load for SWI # */;
585 // Return cycles
586 if (gba->cpu->executionMode == MODE_ARM) {
587 gba->cpu->cycles += cpu->memory.activeNonseqCycles32 + cpu->memory.activeSeqCycles32;
588 } else {
589 gba->cpu->cycles += cpu->memory.activeNonseqCycles16 + cpu->memory.activeSeqCycles16;
590 }
591 gba->memory.biosPrefetch = 0xE3A02004;
592}
593
594void GBASwi32(struct ARMCore* cpu, int immediate) {
595 GBASwi16(cpu, immediate >> 16);
596}
597
598uint32_t GBAChecksum(uint32_t* memory, size_t size) {
599 size_t i;
600 uint32_t sum = 0;
601 for (i = 0; i < size; i += 4) {
602 sum += memory[i >> 2];
603 }
604 return sum;
605}
606
607static void _unLz77(struct GBA* gba, int width) {
608 struct ARMCore* cpu = gba->cpu;
609 uint32_t source = cpu->gprs[0];
610 uint32_t dest = cpu->gprs[1];
611 int remaining = (cpu->memory.load32(cpu, source, 0) & 0xFFFFFF00) >> 8;
612 // We assume the signature byte (0x10) is correct
613 int blockheader = 0; // Some compilers warn if this isn't set, even though it's trivially provably always set
614 source += 4;
615 int blocksRemaining = 0;
616 uint32_t disp;
617 int bytes;
618 int byte;
619 int halfword = 0;
620 while (remaining > 0) {
621 if (blocksRemaining) {
622 if (blockheader & 0x80) {
623 // Compressed
624 int block = cpu->memory.load8(cpu, source + 1, 0) | (cpu->memory.load8(cpu, source, 0) << 8);
625 source += 2;
626 disp = dest - (block & 0x0FFF) - 1;
627 bytes = (block >> 12) + 3;
628 while (bytes--) {
629 if (remaining) {
630 --remaining;
631 }
632 if (width == 2) {
633 byte = (int16_t) cpu->memory.load16(cpu, disp & ~1, 0);
634 if (dest & 1) {
635 byte >>= (disp & 1) * 8;
636 halfword |= byte << 8;
637 cpu->memory.store16(cpu, dest ^ 1, halfword, 0);
638 } else {
639 byte >>= (disp & 1) * 8;
640 halfword = byte & 0xFF;
641 }
642 } else {
643 byte = cpu->memory.load8(cpu, disp, 0);
644 cpu->memory.store8(cpu, dest, byte, 0);
645 }
646 ++disp;
647 ++dest;
648 }
649 } else {
650 // Uncompressed
651 byte = cpu->memory.load8(cpu, source, 0);
652 ++source;
653 if (width == 2) {
654 if (dest & 1) {
655 halfword |= byte << 8;
656 cpu->memory.store16(cpu, dest ^ 1, halfword, 0);
657 } else {
658 halfword = byte;
659 }
660 } else {
661 cpu->memory.store8(cpu, dest, byte, 0);
662 }
663 ++dest;
664 --remaining;
665 }
666 blockheader <<= 1;
667 --blocksRemaining;
668 } else {
669 blockheader = cpu->memory.load8(cpu, source, 0);
670 ++source;
671 blocksRemaining = 8;
672 }
673 }
674 cpu->gprs[0] = source;
675 cpu->gprs[1] = dest;
676 cpu->gprs[3] = 0;
677}
678
679DECL_BITFIELD(HuffmanNode, uint8_t);
680DECL_BITS(HuffmanNode, Offset, 0, 6);
681DECL_BIT(HuffmanNode, RTerm, 6);
682DECL_BIT(HuffmanNode, LTerm, 7);
683
684static void _unHuffman(struct GBA* gba) {
685 struct ARMCore* cpu = gba->cpu;
686 uint32_t source = cpu->gprs[0] & 0xFFFFFFFC;
687 uint32_t dest = cpu->gprs[1];
688 uint32_t header = cpu->memory.load32(cpu, source, 0);
689 int remaining = header >> 8;
690 unsigned bits = header & 0xF;
691 if (bits == 0) {
692 mLOG(GBA_BIOS, GAME_ERROR, "Invalid Huffman bits");
693 bits = 8;
694 }
695 if (32 % bits || bits == 1) {
696 mLOG(GBA_BIOS, STUB, "Unimplemented unaligned Huffman");
697 return;
698 }
699 // We assume the signature byte (0x20) is correct
700 int treesize = (cpu->memory.load8(cpu, source + 4, 0) << 1) + 1;
701 int block = 0;
702 uint32_t treeBase = source + 5;
703 source += 5 + treesize;
704 uint32_t nPointer = treeBase;
705 HuffmanNode node;
706 int bitsRemaining;
707 int readBits;
708 int bitsSeen = 0;
709 node = cpu->memory.load8(cpu, nPointer, 0);
710 while (remaining > 0) {
711 uint32_t bitstream = cpu->memory.load32(cpu, source, 0);
712 source += 4;
713 for (bitsRemaining = 32; bitsRemaining > 0 && remaining > 0; --bitsRemaining, bitstream <<= 1) {
714 uint32_t next = (nPointer & ~1) + HuffmanNodeGetOffset(node) * 2 + 2;
715 if (bitstream & 0x80000000) {
716 // Go right
717 if (HuffmanNodeIsRTerm(node)) {
718 readBits = cpu->memory.load8(cpu, next + 1, 0);
719 } else {
720 nPointer = next + 1;
721 node = cpu->memory.load8(cpu, nPointer, 0);
722 continue;
723 }
724 } else {
725 // Go left
726 if (HuffmanNodeIsLTerm(node)) {
727 readBits = cpu->memory.load8(cpu, next, 0);
728 } else {
729 nPointer = next;
730 node = cpu->memory.load8(cpu, nPointer, 0);
731 continue;
732 }
733 }
734
735 block |= (readBits & ((1 << bits) - 1)) << bitsSeen;
736 bitsSeen += bits;
737 nPointer = treeBase;
738 node = cpu->memory.load8(cpu, nPointer, 0);
739 if (bitsSeen == 32) {
740 bitsSeen = 0;
741 cpu->memory.store32(cpu, dest, block, 0);
742 dest += 4;
743 remaining -= 4;
744 block = 0;
745 }
746 }
747 }
748 cpu->gprs[0] = source;
749 cpu->gprs[1] = dest;
750}
751
752static void _unRl(struct GBA* gba, int width) {
753 struct ARMCore* cpu = gba->cpu;
754 uint32_t source = cpu->gprs[0];
755 int remaining = (cpu->memory.load32(cpu, source & 0xFFFFFFFC, 0) & 0xFFFFFF00) >> 8;
756 int padding = (4 - remaining) & 0x3;
757 // We assume the signature byte (0x30) is correct
758 int blockheader;
759 int block;
760 source += 4;
761 uint32_t dest = cpu->gprs[1];
762 int halfword = 0;
763 while (remaining > 0) {
764 blockheader = cpu->memory.load8(cpu, source, 0);
765 ++source;
766 if (blockheader & 0x80) {
767 // Compressed
768 blockheader &= 0x7F;
769 blockheader += 3;
770 block = cpu->memory.load8(cpu, source, 0);
771 ++source;
772 while (blockheader-- && remaining) {
773 --remaining;
774 if (width == 2) {
775 if (dest & 1) {
776 halfword |= block << 8;
777 cpu->memory.store16(cpu, dest ^ 1, halfword, 0);
778 } else {
779 halfword = block;
780 }
781 } else {
782 cpu->memory.store8(cpu, dest, block, 0);
783 }
784 ++dest;
785 }
786 } else {
787 // Uncompressed
788 blockheader++;
789 while (blockheader-- && remaining) {
790 --remaining;
791 int byte = cpu->memory.load8(cpu, source, 0);
792 ++source;
793 if (width == 2) {
794 if (dest & 1) {
795 halfword |= byte << 8;
796 cpu->memory.store16(cpu, dest ^ 1, halfword, 0);
797 } else {
798 halfword = byte;
799 }
800 } else {
801 cpu->memory.store8(cpu, dest, byte, 0);
802 }
803 ++dest;
804 }
805 }
806 }
807 if (width == 2) {
808 if (dest & 1) {
809 --padding;
810 ++dest;
811 }
812 for (; padding > 0; padding -= 2, dest += 2) {
813 cpu->memory.store16(cpu, dest, 0, 0);
814 }
815 } else {
816 while (padding--) {
817 cpu->memory.store8(cpu, dest, 0, 0);
818 ++dest;
819 }
820 }
821 cpu->gprs[0] = source;
822 cpu->gprs[1] = dest;
823}
824
825static void _unFilter(struct GBA* gba, int inwidth, int outwidth) {
826 struct ARMCore* cpu = gba->cpu;
827 uint32_t source = cpu->gprs[0] & 0xFFFFFFFC;
828 uint32_t dest = cpu->gprs[1];
829 uint32_t header = cpu->memory.load32(cpu, source, 0);
830 int remaining = header >> 8;
831 // We assume the signature nybble (0x8) is correct
832 uint16_t halfword = 0;
833 uint16_t old = 0;
834 source += 4;
835 while (remaining > 0) {
836 uint16_t new;
837 if (inwidth == 1) {
838 new = cpu->memory.load8(cpu, source, 0);
839 } else {
840 new = cpu->memory.load16(cpu, source, 0);
841 }
842 new += old;
843 if (outwidth > inwidth) {
844 halfword >>= 8;
845 halfword |= (new << 8);
846 if (source & 1) {
847 cpu->memory.store16(cpu, dest, halfword, 0);
848 dest += outwidth;
849 remaining -= outwidth;
850 }
851 } else if (outwidth == 1) {
852 cpu->memory.store8(cpu, dest, new, 0);
853 dest += outwidth;
854 remaining -= outwidth;
855 } else {
856 cpu->memory.store16(cpu, dest, new, 0);
857 dest += outwidth;
858 remaining -= outwidth;
859 }
860 old = new;
861 source += inwidth;
862 }
863 cpu->gprs[0] = source;
864 cpu->gprs[1] = dest;
865}
866
867static void _unBitPack(struct GBA* gba) {
868 struct ARMCore* cpu = gba->cpu;
869 uint32_t source = cpu->gprs[0];
870 uint32_t dest = cpu->gprs[1];
871 uint32_t info = cpu->gprs[2];
872 unsigned sourceLen = cpu->memory.load16(cpu, info, 0);
873 unsigned sourceWidth = cpu->memory.load8(cpu, info + 2, 0);
874 unsigned destWidth = cpu->memory.load8(cpu, info + 3, 0);
875 switch (sourceWidth) {
876 case 1:
877 case 2:
878 case 4:
879 case 8:
880 break;
881 default:
882 mLOG(GBA_BIOS, GAME_ERROR, "Bad BitUnPack source width: %u", sourceWidth);
883 return;
884 }
885 switch (destWidth) {
886 case 1:
887 case 2:
888 case 4:
889 case 8:
890 case 16:
891 case 32:
892 break;
893 default:
894 mLOG(GBA_BIOS, GAME_ERROR, "Bad BitUnPack destination width: %u", destWidth);
895 return;
896 }
897 uint32_t bias = cpu->memory.load32(cpu, info + 4, 0);
898 uint8_t in = 0;
899 uint32_t out = 0;
900 int bitsRemaining = 0;
901 int bitsEaten = 0;
902 while (sourceLen > 0 || bitsRemaining) {
903 if (!bitsRemaining) {
904 in = cpu->memory.load8(cpu, source, 0);
905 bitsRemaining = 8;
906 ++source;
907 --sourceLen;
908 }
909 unsigned scaled = in & ((1 << sourceWidth) - 1);
910 in >>= sourceWidth;
911 if (scaled || bias & 0x80000000) {
912 scaled += bias & 0x7FFFFFFF;
913 }
914 bitsRemaining -= sourceWidth;
915 out |= scaled << bitsEaten;
916 bitsEaten += destWidth;
917 if (bitsEaten == 32) {
918 cpu->memory.store32(cpu, dest, out, 0);
919 bitsEaten = 0;
920 out = 0;
921 dest += 4;
922 }
923 }
924 cpu->gprs[0] = source;
925 cpu->gprs[1] = dest;
926}