src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32
33static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
34static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
35
36void GBMBCSwitchBank(struct GB* gb, int bank) {
37 size_t bankStart = bank * GB_SIZE_CART_BANK0;
38 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
39 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
40 bankStart &= (gb->memory.romSize - 1);
41 bank = bankStart / GB_SIZE_CART_BANK0;
42 }
43 gb->memory.romBank = &gb->memory.rom[bankStart];
44 gb->memory.currentBank = bank;
45 if (gb->cpu->pc < GB_BASE_VRAM) {
46 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
47 }
48}
49
50void GBMBCSwitchBank0(struct GB* gb, int bank) {
51 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
52 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
53 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
54 bankStart &= (gb->memory.romSize - 1);
55 }
56 gb->memory.romBase = &gb->memory.rom[bankStart];
57 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
58 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
59 }
60}
61
62static bool _isMulticart(const uint8_t* mem) {
63 bool success = true;
64 struct VFile* vf;
65
66 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
67 success = success && GBIsROM(vf);
68 vf->close(vf);
69
70 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
71 success = success && GBIsROM(vf);
72 vf->close(vf);
73
74 return success;
75}
76
77void GBMBCSwitchSramBank(struct GB* gb, int bank) {
78 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
79 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
80 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
81 bankStart &= (gb->sramSize - 1);
82 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
83 }
84 gb->memory.sramBank = &gb->memory.sram[bankStart];
85 gb->memory.sramCurrentBank = bank;
86}
87
88void GBMBCInit(struct GB* gb) {
89 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
90 if (gb->memory.rom) {
91 switch (cart->ramSize) {
92 case 0:
93 gb->sramSize = 0;
94 break;
95 case 1:
96 gb->sramSize = 0x800;
97 break;
98 default:
99 case 2:
100 gb->sramSize = 0x2000;
101 break;
102 case 3:
103 gb->sramSize = 0x8000;
104 break;
105 case 4:
106 gb->sramSize = 0x20000;
107 break;
108 case 5:
109 gb->sramSize = 0x10000;
110 break;
111 }
112
113 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
114 switch (cart->type) {
115 case 0:
116 case 8:
117 case 9:
118 gb->memory.mbcType = GB_MBC_NONE;
119 break;
120 case 1:
121 case 2:
122 case 3:
123 gb->memory.mbcType = GB_MBC1;
124 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
125 gb->memory.mbcState.mbc1.multicartStride = 4;
126 } else {
127 gb->memory.mbcState.mbc1.multicartStride = 5;
128 }
129 break;
130 case 5:
131 case 6:
132 gb->memory.mbcType = GB_MBC2;
133 break;
134 case 0x0F:
135 case 0x10:
136 gb->memory.mbcType = GB_MBC3_RTC;
137 break;
138 case 0x11:
139 case 0x12:
140 case 0x13:
141 gb->memory.mbcType = GB_MBC3;
142 break;
143 default:
144 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
145 // Fall through
146 case 0x19:
147 case 0x1A:
148 case 0x1B:
149 gb->memory.mbcType = GB_MBC5;
150 break;
151 case 0x1C:
152 case 0x1D:
153 case 0x1E:
154 gb->memory.mbcType = GB_MBC5_RUMBLE;
155 break;
156 case 0x20:
157 gb->memory.mbcType = GB_MBC6;
158 break;
159 case 0x22:
160 gb->memory.mbcType = GB_MBC7;
161 break;
162 case 0xFC:
163 gb->memory.mbcType = GB_POCKETCAM;
164 break;
165 case 0xFD:
166 gb->memory.mbcType = GB_HuC1;
167 break;
168 case 0xFE:
169 gb->memory.mbcType = GB_HuC3;
170 break;
171 }
172 }
173 } else {
174 gb->memory.mbcType = GB_MBC_NONE;
175 }
176 gb->memory.mbcRead = NULL;
177 switch (gb->memory.mbcType) {
178 case GB_MBC_NONE:
179 gb->memory.mbcWrite = _GBMBCNone;
180 break;
181 case GB_MBC1:
182 gb->memory.mbcWrite = _GBMBC1;
183 break;
184 case GB_MBC2:
185 gb->memory.mbcWrite = _GBMBC2;
186 gb->sramSize = 0x200;
187 break;
188 case GB_MBC3:
189 gb->memory.mbcWrite = _GBMBC3;
190 break;
191 default:
192 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
193 // Fall through
194 case GB_MBC5:
195 gb->memory.mbcWrite = _GBMBC5;
196 break;
197 case GB_MBC6:
198 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
199 gb->memory.mbcWrite = _GBMBC6;
200 break;
201 case GB_MBC7:
202 gb->memory.mbcWrite = _GBMBC7;
203 gb->memory.mbcRead = _GBMBC7Read;
204 gb->sramSize = 0x100;
205 break;
206 case GB_MMM01:
207 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
208 gb->memory.mbcWrite = _GBMBC1;
209 break;
210 case GB_HuC1:
211 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
212 gb->memory.mbcWrite = _GBMBC1;
213 break;
214 case GB_HuC3:
215 gb->memory.mbcWrite = _GBHuC3;
216 break;
217 case GB_MBC3_RTC:
218 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
219 gb->memory.mbcWrite = _GBMBC3;
220 break;
221 case GB_MBC5_RUMBLE:
222 gb->memory.mbcWrite = _GBMBC5;
223 break;
224 case GB_POCKETCAM:
225 gb->memory.mbcWrite = _GBPocketCam;
226 gb->memory.mbcRead = _GBPocketCamRead;
227 break;
228 }
229
230 gb->memory.currentBank = 1;
231 gb->memory.sramCurrentBank = 0;
232 gb->memory.sramAccess = false;
233 gb->memory.rtcAccess = false;
234 gb->memory.activeRtcReg = 0;
235 gb->memory.rtcLatched = false;
236 gb->memory.rtcLastLatch = 0;
237 if (gb->memory.rtc) {
238 if (gb->memory.rtc->sample) {
239 gb->memory.rtc->sample(gb->memory.rtc);
240 }
241 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
242 } else {
243 gb->memory.rtcLastLatch = time(0);
244 }
245 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
246
247 GBResizeSram(gb, gb->sramSize);
248
249 if (gb->memory.mbcType == GB_MBC3_RTC) {
250 GBMBCRTCRead(gb);
251 }
252}
253
254static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
255 time_t t;
256 if (rtc) {
257 if (rtc->sample) {
258 rtc->sample(rtc);
259 }
260 t = rtc->unixTime(rtc);
261 } else {
262 t = time(0);
263 }
264 time_t currentLatch = t;
265 t -= *rtcLastLatch;
266 *rtcLastLatch = currentLatch;
267
268 int64_t diff;
269 diff = rtcRegs[0] + t % 60;
270 if (diff < 0) {
271 diff += 60;
272 t -= 60;
273 }
274 rtcRegs[0] = diff % 60;
275 t /= 60;
276 t += diff / 60;
277
278 diff = rtcRegs[1] + t % 60;
279 if (diff < 0) {
280 diff += 60;
281 t -= 60;
282 }
283 rtcRegs[1] = diff % 60;
284 t /= 60;
285 t += diff / 60;
286
287 diff = rtcRegs[2] + t % 24;
288 if (diff < 0) {
289 diff += 24;
290 t -= 24;
291 }
292 rtcRegs[2] = diff % 24;
293 t /= 24;
294 t += diff / 24;
295
296 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
297 rtcRegs[3] = diff;
298 rtcRegs[4] &= 0xFE;
299 rtcRegs[4] |= (diff >> 8) & 1;
300 if (diff & 0x200) {
301 rtcRegs[4] |= 0x80;
302 }
303}
304
305void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
306 struct GBMemory* memory = &gb->memory;
307 int bank = value & 0x1F;
308 int stride = 1 << memory->mbcState.mbc1.multicartStride;
309 switch (address >> 13) {
310 case 0x0:
311 switch (value) {
312 case 0:
313 memory->sramAccess = false;
314 break;
315 case 0xA:
316 memory->sramAccess = true;
317 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
318 break;
319 default:
320 // TODO
321 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
322 break;
323 }
324 break;
325 case 0x1:
326 if (!bank) {
327 ++bank;
328 }
329 bank &= stride - 1;
330 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
331 break;
332 case 0x2:
333 bank &= 3;
334 if (memory->mbcState.mbc1.mode) {
335 GBMBCSwitchBank0(gb, bank);
336 GBMBCSwitchSramBank(gb, bank);
337 }
338 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
339 break;
340 case 0x3:
341 memory->mbcState.mbc1.mode = value & 1;
342 if (memory->mbcState.mbc1.mode) {
343 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
344 } else {
345 GBMBCSwitchBank0(gb, 0);
346 GBMBCSwitchSramBank(gb, 0);
347 }
348 break;
349 default:
350 // TODO
351 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
352 break;
353 }
354}
355
356void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
357 struct GBMemory* memory = &gb->memory;
358 int bank = value & 0xF;
359 switch (address >> 13) {
360 case 0x0:
361 switch (value) {
362 case 0:
363 memory->sramAccess = false;
364 break;
365 case 0xA:
366 memory->sramAccess = true;
367 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
368 break;
369 default:
370 // TODO
371 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
372 break;
373 }
374 break;
375 case 0x1:
376 if (!bank) {
377 ++bank;
378 }
379 GBMBCSwitchBank(gb, bank);
380 break;
381 default:
382 // TODO
383 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
384 break;
385 }
386}
387
388void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
389 struct GBMemory* memory = &gb->memory;
390 int bank = value & 0x7F;
391 switch (address >> 13) {
392 case 0x0:
393 switch (value) {
394 case 0:
395 memory->sramAccess = false;
396 break;
397 case 0xA:
398 memory->sramAccess = true;
399 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
400 break;
401 default:
402 // TODO
403 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
404 break;
405 }
406 break;
407 case 0x1:
408 if (!bank) {
409 ++bank;
410 }
411 GBMBCSwitchBank(gb, bank);
412 break;
413 case 0x2:
414 if (value < 4) {
415 GBMBCSwitchSramBank(gb, value);
416 memory->rtcAccess = false;
417 } else if (value >= 8 && value <= 0xC) {
418 memory->activeRtcReg = value - 8;
419 memory->rtcAccess = true;
420 }
421 break;
422 case 0x3:
423 if (memory->rtcLatched && value == 0) {
424 memory->rtcLatched = false;
425 } else if (!memory->rtcLatched && value == 1) {
426 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
427 memory->rtcLatched = true;
428 }
429 break;
430 }
431}
432
433void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
434 struct GBMemory* memory = &gb->memory;
435 int bank;
436 switch (address >> 12) {
437 case 0x0:
438 case 0x1:
439 switch (value) {
440 case 0:
441 memory->sramAccess = false;
442 break;
443 case 0xA:
444 memory->sramAccess = true;
445 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
446 break;
447 default:
448 // TODO
449 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
450 break;
451 }
452 break;
453 case 0x2:
454 bank = (memory->currentBank & 0x100) | value;
455 GBMBCSwitchBank(gb, bank);
456 break;
457 case 0x3:
458 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
459 GBMBCSwitchBank(gb, bank);
460 break;
461 case 0x4:
462 case 0x5:
463 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
464 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
465 value &= ~8;
466 }
467 GBMBCSwitchSramBank(gb, value & 0xF);
468 break;
469 default:
470 // TODO
471 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
472 break;
473 }
474}
475
476void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
477 // TODO
478 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
479 UNUSED(gb);
480 UNUSED(address);
481 UNUSED(value);
482}
483
484void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
485 int bank = value & 0x7F;
486 switch (address >> 13) {
487 case 0x0:
488 switch (value) {
489 default:
490 case 0:
491 gb->memory.mbcState.mbc7.access = 0;
492 break;
493 case 0xA:
494 gb->memory.mbcState.mbc7.access |= 1;
495 break;
496 }
497 break;
498 case 0x1:
499 GBMBCSwitchBank(gb, bank);
500 break;
501 case 0x2:
502 if (value == 0x40) {
503 gb->memory.mbcState.mbc7.access |= 2;
504 } else {
505 gb->memory.mbcState.mbc7.access &= ~2;
506 }
507 break;
508 default:
509 // TODO
510 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
511 break;
512 }
513}
514
515uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
516 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
517 if (mbc7->access != 3) {
518 return 0xFF;
519 }
520 switch (address & 0xF0) {
521 case 0x20:
522 if (memory->rotation && memory->rotation->readTiltX) {
523 int32_t x = -memory->rotation->readTiltX(memory->rotation);
524 x >>= 21;
525 x += 0x81D0;
526 return x;
527 }
528 return 0xFF;
529 case 0x30:
530 if (memory->rotation && memory->rotation->readTiltX) {
531 int32_t x = -memory->rotation->readTiltX(memory->rotation);
532 x >>= 21;
533 x += 0x81D0;
534 return x >> 8;
535 }
536 return 7;
537 case 0x40:
538 if (memory->rotation && memory->rotation->readTiltY) {
539 int32_t y = -memory->rotation->readTiltY(memory->rotation);
540 y >>= 21;
541 y += 0x81D0;
542 return y;
543 }
544 return 0xFF;
545 case 0x50:
546 if (memory->rotation && memory->rotation->readTiltY) {
547 int32_t y = -memory->rotation->readTiltY(memory->rotation);
548 y >>= 21;
549 y += 0x81D0;
550 return y >> 8;
551 }
552 return 7;
553 case 0x60:
554 return 0;
555 case 0x80:
556 return mbc7->eeprom;
557 default:
558 return 0xFF;
559 }
560}
561
562void GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
563 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
564 if (mbc7->access != 3) {
565 return;
566 }
567 switch (address & 0xF0) {
568 case 0x00:
569 mbc7->latch = (value & 0x55) == 0x55;
570 return;
571 case 0x10:
572 mbc7->latch |= (value & 0xAA);
573 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
574 memory->rotation->sample(memory->rotation);
575 }
576 mbc7->latch = 0;
577 return;
578 default:
579 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
580 return;
581 case 0x80:
582 break;
583 }
584 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
585 value = GBMBC7FieldFillDO(value); // Hi-Z
586 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
587 mbc7->state = GBMBC7_STATE_IDLE;
588 }
589 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
590 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
591 mbc7->sr <<= 1;
592 mbc7->sr |= GBMBC7FieldGetDI(value);
593 ++mbc7->srBits;
594 }
595 switch (mbc7->state) {
596 case GBMBC7_STATE_IDLE:
597 if (GBMBC7FieldIsDI(value)) {
598 mbc7->state = GBMBC7_STATE_READ_COMMAND;
599 mbc7->srBits = 0;
600 mbc7->sr = 0;
601 }
602 break;
603 case GBMBC7_STATE_READ_COMMAND:
604 if (mbc7->srBits == 10) {
605 mbc7->state = 0x10 | (mbc7->sr >> 6);
606 if (mbc7->state & 0xC) {
607 mbc7->state &= ~0x3;
608 }
609 mbc7->srBits = 0;
610 mbc7->address = mbc7->sr & 0x7F;
611 }
612 break;
613 case GBMBC7_STATE_DO:
614 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
615 mbc7->sr <<= 1;
616 --mbc7->srBits;
617 if (!mbc7->srBits) {
618 mbc7->state = GBMBC7_STATE_IDLE;
619 }
620 break;
621 default:
622 break;
623 }
624 switch (mbc7->state) {
625 case GBMBC7_STATE_EEPROM_EWEN:
626 mbc7->writable = true;
627 mbc7->state = GBMBC7_STATE_IDLE;
628 break;
629 case GBMBC7_STATE_EEPROM_EWDS:
630 mbc7->writable = false;
631 mbc7->state = GBMBC7_STATE_IDLE;
632 break;
633 case GBMBC7_STATE_EEPROM_WRITE:
634 if (mbc7->srBits == 16) {
635 if (mbc7->writable) {
636 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
637 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
638 }
639 mbc7->state = GBMBC7_STATE_IDLE;
640 }
641 break;
642 case GBMBC7_STATE_EEPROM_ERASE:
643 if (mbc7->writable) {
644 memory->sram[mbc7->address * 2] = 0xFF;
645 memory->sram[mbc7->address * 2 + 1] = 0xFF;
646 }
647 mbc7->state = GBMBC7_STATE_IDLE;
648 break;
649 case GBMBC7_STATE_EEPROM_READ:
650 mbc7->srBits = 16;
651 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
652 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
653 mbc7->state = GBMBC7_STATE_DO;
654 value = GBMBC7FieldClearDO(value);
655 break;
656 case GBMBC7_STATE_EEPROM_WRAL:
657 if (mbc7->srBits == 16) {
658 if (mbc7->writable) {
659 int i;
660 for (i = 0; i < 128; ++i) {
661 memory->sram[i * 2] = mbc7->sr >> 8;
662 memory->sram[i * 2 + 1] = mbc7->sr;
663 }
664 }
665 mbc7->state = GBMBC7_STATE_IDLE;
666 }
667 break;
668 case GBMBC7_STATE_EEPROM_ERAL:
669 if (mbc7->writable) {
670 int i;
671 for (i = 0; i < 128; ++i) {
672 memory->sram[i * 2] = 0xFF;
673 memory->sram[i * 2 + 1] = 0xFF;
674 }
675 }
676 mbc7->state = GBMBC7_STATE_IDLE;
677 break;
678 default:
679 break;
680 }
681 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
682 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
683 }
684 mbc7->eeprom = value;
685}
686
687void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
688 struct GBMemory* memory = &gb->memory;
689 int bank = value & 0x3F;
690 if (address & 0x1FFF) {
691 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
692 }
693
694 switch (address >> 13) {
695 case 0x0:
696 switch (value) {
697 case 0xA:
698 memory->sramAccess = true;
699 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
700 break;
701 default:
702 memory->sramAccess = false;
703 break;
704 }
705 break;
706 case 0x1:
707 GBMBCSwitchBank(gb, bank);
708 break;
709 case 0x2:
710 GBMBCSwitchSramBank(gb, bank);
711 break;
712 default:
713 // TODO
714 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
715 break;
716 }
717}
718
719void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
720 struct GBMemory* memory = &gb->memory;
721 int bank = value & 0x3F;
722 switch (address >> 13) {
723 case 0x0:
724 switch (value) {
725 case 0:
726 memory->sramAccess = false;
727 break;
728 case 0xA:
729 memory->sramAccess = true;
730 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
731 break;
732 default:
733 // TODO
734 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
735 break;
736 }
737 break;
738 case 0x1:
739 GBMBCSwitchBank(gb, bank);
740 break;
741 case 0x2:
742 if (value < 0x10) {
743 GBMBCSwitchSramBank(gb, value);
744 memory->mbcState.pocketCam.registersActive = false;
745 } else {
746 memory->mbcState.pocketCam.registersActive = true;
747 }
748 break;
749 default:
750 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
751 break;
752 }
753}
754
755uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
756 if (memory->mbcState.pocketCam.registersActive) {
757 return 0;
758 }
759 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
760}
761
762void GBMBCRTCRead(struct GB* gb) {
763 struct GBMBCRTCSaveBuffer rtcBuffer;
764 struct VFile* vf = gb->sramVf;
765 if (!vf) {
766 return;
767 }
768 vf->seek(vf, gb->sramSize, SEEK_SET);
769 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
770 return;
771 }
772
773 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
774 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
775 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
776 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
777 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
778 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
779}
780
781void GBMBCRTCWrite(struct GB* gb) {
782 struct VFile* vf = gb->sramVf;
783 if (!vf) {
784 return;
785 }
786
787 uint8_t rtcRegs[5];
788 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
789 time_t rtcLastLatch = gb->memory.rtcLastLatch;
790 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
791
792 struct GBMBCRTCSaveBuffer rtcBuffer;
793 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
794 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
795 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
796 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
797 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
798 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
799 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
800 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
801 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
802 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
803 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
804
805 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
806 // Writing past the end of the file can invalidate the file mapping
807 vf->unmap(vf, gb->memory.sram, gb->sramSize);
808 gb->memory.sram = NULL;
809 }
810 vf->seek(vf, gb->sramSize, SEEK_SET);
811 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
812 if (!gb->memory.sram) {
813 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
814 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
815 }
816}