src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int shift = cpu->gprs[rs];
23 if (rs == ARM_PC) {
24 shift += 4;
25 }
26 shift &= 0xFF;
27 int32_t shiftVal = cpu->gprs[rm];
28 if (rm == ARM_PC) {
29 shiftVal += 4;
30 }
31 if (!shift) {
32 cpu->shifterOperand = shiftVal;
33 cpu->shifterCarryOut = cpu->cpsr.c;
34 } else if (shift < 32) {
35 cpu->shifterOperand = shiftVal << shift;
36 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
37 } else if (shift == 32) {
38 cpu->shifterOperand = 0;
39 cpu->shifterCarryOut = shiftVal & 1;
40 } else {
41 cpu->shifterOperand = 0;
42 cpu->shifterCarryOut = 0;
43 }
44 } else {
45 int immediate = (opcode & 0x00000F80) >> 7;
46 if (!immediate) {
47 cpu->shifterOperand = cpu->gprs[rm];
48 cpu->shifterCarryOut = cpu->cpsr.c;
49 } else {
50 cpu->shifterOperand = cpu->gprs[rm] << immediate;
51 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
52 }
53 }
54}
55
56static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
57 int rm = opcode & 0x0000000F;
58 if (opcode & 0x00000010) {
59 int rs = (opcode >> 8) & 0x0000000F;
60 ++cpu->cycles;
61 int shift = cpu->gprs[rs];
62 if (rs == ARM_PC) {
63 shift += 4;
64 }
65 shift &= 0xFF;
66 uint32_t shiftVal = cpu->gprs[rm];
67 if (rm == ARM_PC) {
68 shiftVal += 4;
69 }
70 if (!shift) {
71 cpu->shifterOperand = shiftVal;
72 cpu->shifterCarryOut = cpu->cpsr.c;
73 } else if (shift < 32) {
74 cpu->shifterOperand = shiftVal >> shift;
75 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
76 } else if (shift == 32) {
77 cpu->shifterOperand = 0;
78 cpu->shifterCarryOut = shiftVal >> 31;
79 } else {
80 cpu->shifterOperand = 0;
81 cpu->shifterCarryOut = 0;
82 }
83 } else {
84 int immediate = (opcode & 0x00000F80) >> 7;
85 if (immediate) {
86 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
87 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
91 }
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 if (opcode & 0x00000010) {
98 int rs = (opcode >> 8) & 0x0000000F;
99 ++cpu->cycles;
100 int shift = cpu->gprs[rs];
101 if (rs == ARM_PC) {
102 shift += 4;
103 }
104 shift &= 0xFF;
105 int shiftVal = cpu->gprs[rm];
106 if (rm == ARM_PC) {
107 shiftVal += 4;
108 }
109 if (!shift) {
110 cpu->shifterOperand = shiftVal;
111 cpu->shifterCarryOut = cpu->cpsr.c;
112 } else if (shift < 32) {
113 cpu->shifterOperand = shiftVal >> shift;
114 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
115 } else if (cpu->gprs[rm] >> 31) {
116 cpu->shifterOperand = 0xFFFFFFFF;
117 cpu->shifterCarryOut = 1;
118 } else {
119 cpu->shifterOperand = 0;
120 cpu->shifterCarryOut = 0;
121 }
122 } else {
123 int immediate = (opcode & 0x00000F80) >> 7;
124 if (immediate) {
125 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
126 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
127 } else {
128 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
129 cpu->shifterOperand = cpu->shifterCarryOut;
130 }
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 if (opcode & 0x00000010) {
137 int rs = (opcode >> 8) & 0x0000000F;
138 ++cpu->cycles;
139 int shift = cpu->gprs[rs];
140 if (rs == ARM_PC) {
141 shift += 4;
142 }
143 shift &= 0xFF;
144 int shiftVal = cpu->gprs[rm];
145 if (rm == ARM_PC) {
146 shiftVal += 4;
147 }
148 int rotate = shift & 0x1F;
149 if (!shift) {
150 cpu->shifterOperand = shiftVal;
151 cpu->shifterCarryOut = cpu->cpsr.c;
152 } else if (rotate) {
153 cpu->shifterOperand = ROR(shiftVal, rotate);
154 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
155 } else {
156 cpu->shifterOperand = shiftVal;
157 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
158 }
159 } else {
160 int immediate = (opcode & 0x00000F80) >> 7;
161 if (immediate) {
162 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
163 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
164 } else {
165 // RRX
166 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
167 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
168 }
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
188 cpu->cpsr.flags = 0;
189 cpu->cpsr.n = ARM_SIGN(d);
190 cpu->cpsr.z = !d;
191 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
192 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
193}
194
195ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
196 cpu->cpsr.flags = 0;
197 cpu->cpsr.n = ARM_SIGN(d);
198 cpu->cpsr.z = !d;
199 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
200 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
201}
202
203ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
204 cpu->cpsr.n = ARM_SIGN(d);
205 cpu->cpsr.z = !d; \
206 cpu->cpsr.c = cpu->shifterCarryOut; \
207}
208
209#define ARM_ADDITION_S(M, N, D) \
210 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
211 cpu->cpsr = cpu->spsr; \
212 _ARMReadCPSR(cpu); \
213 } else { \
214 _additionS(cpu, M, N, D); \
215 }
216
217#define ARM_SUBTRACTION_S(M, N, D) \
218 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
219 cpu->cpsr = cpu->spsr; \
220 _ARMReadCPSR(cpu); \
221 } else { \
222 _subtractionS(cpu, M, N, D); \
223 }
224
225#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
226 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
227 cpu->cpsr = cpu->spsr; \
228 _ARMReadCPSR(cpu); \
229 } else { \
230 cpu->cpsr.n = ARM_SIGN(D); \
231 cpu->cpsr.z = !(D); \
232 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
233 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
234 }
235
236#define ARM_NEUTRAL_S(M, N, D) \
237 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
238 cpu->cpsr = cpu->spsr; \
239 _ARMReadCPSR(cpu); \
240 } else { \
241 _neutralS(cpu, D); \
242 }
243
244#define ARM_NEUTRAL_HI_S(DLO, DHI) \
245 cpu->cpsr.n = ARM_SIGN(DHI); \
246 cpu->cpsr.z = !((DHI) | (DLO));
247
248#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
249#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
250#define ADDR_MODE_2_ADDRESS (address)
251#define ADDR_MODE_2_RN (cpu->gprs[rn])
252#define ADDR_MODE_2_RM (cpu->gprs[rm])
253#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
254#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
255#define ADDR_MODE_2_WRITEBACK(ADDR) \
256 cpu->gprs[rn] = ADDR; \
257 if (UNLIKELY(rn == ARM_PC)) { \
258 currentCycles += ARMWritePC(cpu); \
259 }
260
261#define ADDR_MODE_2_WRITEBACK_PRE_STORE(WB)
262#define ADDR_MODE_2_WRITEBACK_POST_STORE(WB) WB
263#define ADDR_MODE_2_WRITEBACK_PRE_LOAD(WB) WB
264#define ADDR_MODE_2_WRITEBACK_POST_LOAD(WB)
265
266#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
267#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
268#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
269#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
270
271#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
272#define ADDR_MODE_3_RN ADDR_MODE_2_RN
273#define ADDR_MODE_3_RM ADDR_MODE_2_RM
274#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
275#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
276#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
277
278#define ADDR_MODE_4_WRITEBACK_LDM \
279 if (!((1 << rn) & rs)) { \
280 cpu->gprs[rn] = address; \
281 }
282
283#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
284
285#define ARM_LOAD_POST_BODY \
286 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
287 if (rd == ARM_PC) { \
288 currentCycles += ARMWritePC(cpu); \
289 }
290
291#define ARM_STORE_POST_BODY \
292 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
293
294#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
295 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
296 int currentCycles = ARM_PREFETCH_CYCLES; \
297 BODY; \
298 cpu->cycles += currentCycles; \
299 }
300
301#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
302 DEFINE_INSTRUCTION_ARM(NAME, \
303 int rd = (opcode >> 12) & 0xF; \
304 int rn = (opcode >> 16) & 0xF; \
305 UNUSED(rn); \
306 SHIFTER(cpu, opcode); \
307 BODY; \
308 S_BODY; \
309 if (rd == ARM_PC) { \
310 if (cpu->executionMode == MODE_ARM) { \
311 currentCycles += ARMWritePC(cpu); \
312 } else { \
313 currentCycles += ThumbWritePC(cpu); \
314 } \
315 })
316
317#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
322 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
323 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
324 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
328
329#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
331 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
332 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
334 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
335
336#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
337 DEFINE_INSTRUCTION_ARM(NAME, \
338 int rd = (opcode >> 16) & 0xF; \
339 int rs = (opcode >> 8) & 0xF; \
340 int rm = opcode & 0xF; \
341 if (rd == ARM_PC) { \
342 return; \
343 } \
344 ARM_WAIT_MUL(cpu->gprs[rs]); \
345 BODY; \
346 S_BODY; \
347 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
348
349#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
350 DEFINE_INSTRUCTION_ARM(NAME, \
351 int rd = (opcode >> 12) & 0xF; \
352 int rdHi = (opcode >> 16) & 0xF; \
353 int rs = (opcode >> 8) & 0xF; \
354 int rm = opcode & 0xF; \
355 if (rdHi == ARM_PC || rd == ARM_PC) { \
356 return; \
357 } \
358 currentCycles += cpu->memory.stall(cpu, WAIT); \
359 BODY; \
360 S_BODY; \
361 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
362
363#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
364 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
365 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
366
367#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
368 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
369 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
370
371#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LS, BODY) \
372 DEFINE_INSTRUCTION_ARM(NAME, \
373 uint32_t address; \
374 int rn = (opcode >> 16) & 0xF; \
375 int rd = (opcode >> 12) & 0xF; \
376 int rm = opcode & 0xF; \
377 UNUSED(rm); \
378 address = ADDRESS; \
379 ADDR_MODE_2_WRITEBACK_PRE_ ## LS (WRITEBACK); \
380 BODY; \
381 ADDR_MODE_2_WRITEBACK_POST_ ## LS (WRITEBACK);)
382
383#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
384 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), LS, BODY) \
385 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), LS, BODY) \
386 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , LS, BODY) \
387 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , LS, BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY)
390
391#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, LS, BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
402
403#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, LS, BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), LS, BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), LS, BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , LS, BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
408 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , LS, BODY) \
409 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
410 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
411 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
412 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
413 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
414 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
416
417#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), LS, BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), LS, BODY) \
420
421#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, LS, BODY) \
422 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
423 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
424 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
425 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
426 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
427 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
428
429#define ARM_MS_PRE \
430 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
431 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
432
433#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
434
435#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
436 DEFINE_INSTRUCTION_ARM(NAME, \
437 int rn = (opcode >> 16) & 0xF; \
438 int rs = opcode & 0x0000FFFF; \
439 uint32_t address = cpu->gprs[rn]; \
440 S_PRE; \
441 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
442 S_POST; \
443 POST_BODY; \
444 WRITEBACK;)
445
446
447#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
448 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
449 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
450 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
451 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
452 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
453 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
458 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
459 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
460 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
461 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
462 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
463 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
464
465// Begin ALU definitions
466
467DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
468 int32_t n = cpu->gprs[rn];
469 cpu->gprs[rd] = n + cpu->shifterOperand;)
470
471DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
472 int32_t n = cpu->gprs[rn];
473 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
474
475DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
476 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
477
478DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
479 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
480
481DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
482 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
483
484DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
485 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
486
487DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
488 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
489
490DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
491 cpu->gprs[rd] = cpu->shifterOperand;)
492
493DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
494 cpu->gprs[rd] = ~cpu->shifterOperand;)
495
496DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
497 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
498
499DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
500 int32_t n = cpu->gprs[rn];
501 cpu->gprs[rd] = cpu->shifterOperand - n;)
502
503DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
504 int32_t n = cpu->gprs[rn];
505 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
506
507DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
508 int32_t n = cpu->gprs[rn];
509 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
510
511DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
512 int32_t n = cpu->gprs[rn];
513 cpu->gprs[rd] = n - cpu->shifterOperand;)
514
515DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
516 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
517
518DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
519 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
520
521// End ALU definitions
522
523// Begin multiply definitions
524
525DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
526DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
527
528DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
529 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
530 int32_t dm = cpu->gprs[rd];
531 int32_t dn = d;
532 cpu->gprs[rd] = dm + dn;
533 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
534 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
535
536DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
537 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
538 cpu->gprs[rd] = d;
539 cpu->gprs[rdHi] = d >> 32;,
540 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
541
542DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
543 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
544 int32_t dm = cpu->gprs[rd];
545 int32_t dn = d;
546 cpu->gprs[rd] = dm + dn;
547 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
548 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
549
550DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
551 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
552 cpu->gprs[rd] = d;
553 cpu->gprs[rdHi] = d >> 32;,
554 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
555
556// End multiply definitions
557
558// Begin load/store definitions
559
560DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
561DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, LOAD, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
562DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, LOAD, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
563DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, LOAD, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
564DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, LOAD, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
565DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, STORE, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
566DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, STORE, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
567DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, STORE, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
568
569DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, LOAD,
570 enum PrivilegeMode priv = cpu->privilegeMode;
571 ARMSetPrivilegeMode(cpu, MODE_USER);
572 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
573 ARMSetPrivilegeMode(cpu, priv);
574 cpu->gprs[rd] = r;
575 ARM_LOAD_POST_BODY;)
576
577DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, LOAD,
578 enum PrivilegeMode priv = cpu->privilegeMode;
579 ARMSetPrivilegeMode(cpu, MODE_USER);
580 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
581 ARMSetPrivilegeMode(cpu, priv);
582 cpu->gprs[rd] = r;
583 ARM_LOAD_POST_BODY;)
584
585DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, STORE,
586 enum PrivilegeMode priv = cpu->privilegeMode;
587 int32_t r = cpu->gprs[rd];
588 ARMSetPrivilegeMode(cpu, MODE_USER);
589 cpu->memory.store8(cpu, address, r, ¤tCycles);
590 ARMSetPrivilegeMode(cpu, priv);
591 ARM_STORE_POST_BODY;)
592
593DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, STORE,
594 enum PrivilegeMode priv = cpu->privilegeMode;
595 int32_t r = cpu->gprs[rd];
596 ARMSetPrivilegeMode(cpu, MODE_USER);
597 cpu->memory.store32(cpu, address, r, ¤tCycles);
598 ARMSetPrivilegeMode(cpu, priv);
599 ARM_STORE_POST_BODY;)
600
601DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
602 load,
603 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
604 if ((rs & 0x8000) || !rs) {
605 currentCycles += ARMWritePC(cpu);
606 })
607
608DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
609 store,
610 ARM_STORE_POST_BODY;)
611
612DEFINE_INSTRUCTION_ARM(SWP,
613 int rm = opcode & 0xF;
614 int rd = (opcode >> 12) & 0xF;
615 int rn = (opcode >> 16) & 0xF;
616 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
617 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
618 cpu->gprs[rd] = d;)
619
620DEFINE_INSTRUCTION_ARM(SWPB,
621 int rm = opcode & 0xF;
622 int rd = (opcode >> 12) & 0xF;
623 int rn = (opcode >> 16) & 0xF;
624 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
625 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
626 cpu->gprs[rd] = d;)
627
628// End load/store definitions
629
630// Begin branch definitions
631
632DEFINE_INSTRUCTION_ARM(B,
633 int32_t offset = opcode << 8;
634 offset >>= 6;
635 cpu->gprs[ARM_PC] += offset;
636 currentCycles += ARMWritePC(cpu);)
637
638DEFINE_INSTRUCTION_ARM(BL,
639 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
640 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
641 cpu->gprs[ARM_PC] += immediate >> 6;
642 currentCycles += ARMWritePC(cpu);)
643
644DEFINE_INSTRUCTION_ARM(BX,
645 int rm = opcode & 0x0000000F;
646 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
647 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
648 if (cpu->executionMode == MODE_THUMB) {
649 currentCycles += ThumbWritePC(cpu);
650 } else {
651 currentCycles += ARMWritePC(cpu);
652 })
653
654// End branch definitions
655
656// Begin coprocessor definitions
657
658DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
659DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
660DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
661DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
662DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
663
664// Begin miscellaneous definitions
665
666DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
667DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
668
669DEFINE_INSTRUCTION_ARM(MSR,
670 int c = opcode & 0x00010000;
671 int f = opcode & 0x00080000;
672 int32_t operand = cpu->gprs[opcode & 0x0000000F];
673 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
674 if (mask & PSR_USER_MASK) {
675 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
676 }
677 if (mask & PSR_STATE_MASK) {
678 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
679 }
680 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
681 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
682 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
683 }
684 _ARMReadCPSR(cpu);
685 if (cpu->executionMode == MODE_THUMB) {
686 cpu->prefetch[0] = 0x46C0; // nop
687 cpu->prefetch[1] &= 0xFFFF;
688 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
689 } else {
690 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
691 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
692 })
693
694DEFINE_INSTRUCTION_ARM(MSRR,
695 int c = opcode & 0x00010000;
696 int f = opcode & 0x00080000;
697 int32_t operand = cpu->gprs[opcode & 0x0000000F];
698 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
699 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
700 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
701
702DEFINE_INSTRUCTION_ARM(MRS, \
703 int rd = (opcode >> 12) & 0xF; \
704 cpu->gprs[rd] = cpu->cpsr.packed;)
705
706DEFINE_INSTRUCTION_ARM(MRSR, \
707 int rd = (opcode >> 12) & 0xF; \
708 cpu->gprs[rd] = cpu->spsr.packed;)
709
710DEFINE_INSTRUCTION_ARM(MSRI,
711 int c = opcode & 0x00010000;
712 int f = opcode & 0x00080000;
713 int rotate = (opcode & 0x00000F00) >> 7;
714 int32_t operand = ROR(opcode & 0x000000FF, rotate);
715 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
716 if (mask & PSR_USER_MASK) {
717 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
718 }
719 if (mask & PSR_STATE_MASK) {
720 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
721 }
722 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
723 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
724 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
725 }
726 _ARMReadCPSR(cpu);
727 if (cpu->executionMode == MODE_THUMB) {
728 cpu->prefetch[0] = 0x46C0; // nop
729 cpu->prefetch[1] &= 0xFFFF;
730 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
731 } else {
732 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
733 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
734 })
735
736DEFINE_INSTRUCTION_ARM(MSRRI,
737 int c = opcode & 0x00010000;
738 int f = opcode & 0x00080000;
739 int rotate = (opcode & 0x00000F00) >> 7;
740 int32_t operand = ROR(opcode & 0x000000FF, rotate);
741 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
742 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
743 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
744
745DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
746
747const ARMInstruction _armTable[0x1000] = {
748 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
749};