src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
33
34static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
35static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
36
37static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
38
39static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
40
41void GBMBCSwitchBank(struct GB* gb, int bank) {
42 size_t bankStart = bank * GB_SIZE_CART_BANK0;
43 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
44 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
45 bankStart &= (gb->memory.romSize - 1);
46 bank = bankStart / GB_SIZE_CART_BANK0;
47 if (!bank) {
48 ++bank;
49 }
50 }
51 gb->memory.romBank = &gb->memory.rom[bankStart];
52 gb->memory.currentBank = bank;
53 if (gb->cpu->pc < GB_BASE_VRAM) {
54 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
55 }
56}
57
58void GBMBCSwitchBank0(struct GB* gb, int bank) {
59 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
60 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
61 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
62 bankStart &= (gb->memory.romSize - 1);
63 }
64 gb->memory.romBase = &gb->memory.rom[bankStart];
65 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
66 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
67 }
68}
69
70static bool _isMulticart(const uint8_t* mem) {
71 bool success = true;
72 struct VFile* vf;
73
74 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
75 success = success && GBIsROM(vf);
76 vf->close(vf);
77
78 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
79 success = success && GBIsROM(vf);
80 vf->close(vf);
81
82 return success;
83}
84
85void GBMBCSwitchSramBank(struct GB* gb, int bank) {
86 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
87 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
88 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
89 bankStart &= (gb->sramSize - 1);
90 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
91 }
92 gb->memory.sramBank = &gb->memory.sram[bankStart];
93 gb->memory.sramCurrentBank = bank;
94}
95
96void GBMBCInit(struct GB* gb) {
97 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
98 if (gb->memory.rom) {
99 switch (cart->ramSize) {
100 case 0:
101 gb->sramSize = 0;
102 break;
103 case 1:
104 gb->sramSize = 0x800;
105 break;
106 default:
107 case 2:
108 gb->sramSize = 0x2000;
109 break;
110 case 3:
111 gb->sramSize = 0x8000;
112 break;
113 case 4:
114 gb->sramSize = 0x20000;
115 break;
116 case 5:
117 gb->sramSize = 0x10000;
118 break;
119 }
120
121 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
122 switch (cart->type) {
123 case 0:
124 case 8:
125 case 9:
126 gb->memory.mbcType = GB_MBC_NONE;
127 break;
128 case 1:
129 case 2:
130 case 3:
131 gb->memory.mbcType = GB_MBC1;
132 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
133 gb->memory.mbcState.mbc1.multicartStride = 4;
134 } else {
135 gb->memory.mbcState.mbc1.multicartStride = 5;
136 }
137 break;
138 case 5:
139 case 6:
140 gb->memory.mbcType = GB_MBC2;
141 break;
142 case 0x0F:
143 case 0x10:
144 gb->memory.mbcType = GB_MBC3_RTC;
145 break;
146 case 0x11:
147 case 0x12:
148 case 0x13:
149 gb->memory.mbcType = GB_MBC3;
150 break;
151 default:
152 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
153 // Fall through
154 case 0x19:
155 case 0x1A:
156 case 0x1B:
157 gb->memory.mbcType = GB_MBC5;
158 break;
159 case 0x1C:
160 case 0x1D:
161 case 0x1E:
162 gb->memory.mbcType = GB_MBC5_RUMBLE;
163 break;
164 case 0x20:
165 gb->memory.mbcType = GB_MBC6;
166 break;
167 case 0x22:
168 gb->memory.mbcType = GB_MBC7;
169 break;
170 case 0xFC:
171 gb->memory.mbcType = GB_POCKETCAM;
172 break;
173 case 0xFD:
174 gb->memory.mbcType = GB_TAMA5;
175 break;
176 case 0xFE:
177 gb->memory.mbcType = GB_HuC3;
178 break;
179 case 0xFF:
180 gb->memory.mbcType = GB_HuC1;
181 break;
182 }
183 }
184 } else {
185 gb->memory.mbcType = GB_MBC_NONE;
186 }
187 gb->memory.mbcRead = NULL;
188 switch (gb->memory.mbcType) {
189 case GB_MBC_NONE:
190 gb->memory.mbcWrite = _GBMBCNone;
191 break;
192 case GB_MBC1:
193 gb->memory.mbcWrite = _GBMBC1;
194 break;
195 case GB_MBC2:
196 gb->memory.mbcWrite = _GBMBC2;
197 gb->sramSize = 0x200;
198 break;
199 case GB_MBC3:
200 gb->memory.mbcWrite = _GBMBC3;
201 break;
202 default:
203 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
204 // Fall through
205 case GB_MBC5:
206 gb->memory.mbcWrite = _GBMBC5;
207 break;
208 case GB_MBC6:
209 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
210 gb->memory.mbcWrite = _GBMBC6;
211 break;
212 case GB_MBC7:
213 gb->memory.mbcWrite = _GBMBC7;
214 gb->memory.mbcRead = _GBMBC7Read;
215 gb->sramSize = 0x100;
216 break;
217 case GB_MMM01:
218 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
219 gb->memory.mbcWrite = _GBMBC1;
220 break;
221 case GB_HuC1:
222 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
223 gb->memory.mbcWrite = _GBMBC1;
224 break;
225 case GB_HuC3:
226 gb->memory.mbcWrite = _GBHuC3;
227 break;
228 case GB_TAMA5:
229 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
230 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
231 gb->memory.mbcWrite = _GBTAMA5;
232 gb->memory.mbcRead = _GBTAMA5Read;
233 gb->sramSize = 0x20;
234 break;
235 case GB_MBC3_RTC:
236 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
237 gb->memory.mbcWrite = _GBMBC3;
238 break;
239 case GB_MBC5_RUMBLE:
240 gb->memory.mbcWrite = _GBMBC5;
241 break;
242 case GB_POCKETCAM:
243 gb->memory.mbcWrite = _GBPocketCam;
244 gb->memory.mbcRead = _GBPocketCamRead;
245 break;
246 }
247
248 gb->memory.currentBank = 1;
249 gb->memory.sramCurrentBank = 0;
250 gb->memory.sramAccess = false;
251 gb->memory.rtcAccess = false;
252 gb->memory.activeRtcReg = 0;
253 gb->memory.rtcLatched = false;
254 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
255
256 GBResizeSram(gb, gb->sramSize);
257
258 if (gb->memory.mbcType == GB_MBC3_RTC) {
259 GBMBCRTCRead(gb);
260 }
261}
262
263static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
264 time_t t;
265 if (rtc) {
266 if (rtc->sample) {
267 rtc->sample(rtc);
268 }
269 t = rtc->unixTime(rtc);
270 } else {
271 t = time(0);
272 }
273 time_t currentLatch = t;
274 t -= *rtcLastLatch;
275 *rtcLastLatch = currentLatch;
276
277 int64_t diff;
278 diff = rtcRegs[0] + t % 60;
279 if (diff < 0) {
280 diff += 60;
281 t -= 60;
282 }
283 rtcRegs[0] = diff % 60;
284 t /= 60;
285 t += diff / 60;
286
287 diff = rtcRegs[1] + t % 60;
288 if (diff < 0) {
289 diff += 60;
290 t -= 60;
291 }
292 rtcRegs[1] = diff % 60;
293 t /= 60;
294 t += diff / 60;
295
296 diff = rtcRegs[2] + t % 24;
297 if (diff < 0) {
298 diff += 24;
299 t -= 24;
300 }
301 rtcRegs[2] = diff % 24;
302 t /= 24;
303 t += diff / 24;
304
305 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
306 rtcRegs[3] = diff;
307 rtcRegs[4] &= 0xFE;
308 rtcRegs[4] |= (diff >> 8) & 1;
309 if (diff & 0x200) {
310 rtcRegs[4] |= 0x80;
311 }
312}
313
314void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
315 struct GBMemory* memory = &gb->memory;
316 int bank = value & 0x1F;
317 int stride = 1 << memory->mbcState.mbc1.multicartStride;
318 switch (address >> 13) {
319 case 0x0:
320 switch (value) {
321 case 0:
322 memory->sramAccess = false;
323 break;
324 case 0xA:
325 memory->sramAccess = true;
326 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
327 break;
328 default:
329 // TODO
330 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
331 break;
332 }
333 break;
334 case 0x1:
335 if (!bank) {
336 ++bank;
337 }
338 bank &= stride - 1;
339 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
340 break;
341 case 0x2:
342 bank &= 3;
343 if (memory->mbcState.mbc1.mode) {
344 GBMBCSwitchBank0(gb, bank);
345 GBMBCSwitchSramBank(gb, bank);
346 }
347 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
348 break;
349 case 0x3:
350 memory->mbcState.mbc1.mode = value & 1;
351 if (memory->mbcState.mbc1.mode) {
352 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
353 } else {
354 GBMBCSwitchBank0(gb, 0);
355 GBMBCSwitchSramBank(gb, 0);
356 }
357 break;
358 default:
359 // TODO
360 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
361 break;
362 }
363}
364
365void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
366 struct GBMemory* memory = &gb->memory;
367 int bank = value & 0xF;
368 switch (address >> 13) {
369 case 0x0:
370 switch (value) {
371 case 0:
372 memory->sramAccess = false;
373 break;
374 case 0xA:
375 memory->sramAccess = true;
376 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
377 break;
378 default:
379 // TODO
380 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
381 break;
382 }
383 break;
384 case 0x1:
385 if (!bank) {
386 ++bank;
387 }
388 GBMBCSwitchBank(gb, bank);
389 break;
390 default:
391 // TODO
392 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
393 break;
394 }
395}
396
397void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
398 struct GBMemory* memory = &gb->memory;
399 int bank = value & 0x7F;
400 switch (address >> 13) {
401 case 0x0:
402 switch (value) {
403 case 0:
404 memory->sramAccess = false;
405 break;
406 case 0xA:
407 memory->sramAccess = true;
408 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
409 break;
410 default:
411 // TODO
412 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
413 break;
414 }
415 break;
416 case 0x1:
417 if (!bank) {
418 ++bank;
419 }
420 GBMBCSwitchBank(gb, bank);
421 break;
422 case 0x2:
423 if (value < 4) {
424 GBMBCSwitchSramBank(gb, value);
425 memory->rtcAccess = false;
426 } else if (value >= 8 && value <= 0xC) {
427 memory->activeRtcReg = value - 8;
428 memory->rtcAccess = true;
429 }
430 break;
431 case 0x3:
432 if (memory->rtcLatched && value == 0) {
433 memory->rtcLatched = false;
434 } else if (!memory->rtcLatched && value == 1) {
435 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
436 memory->rtcLatched = true;
437 }
438 break;
439 }
440}
441
442void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
443 struct GBMemory* memory = &gb->memory;
444 int bank;
445 switch (address >> 12) {
446 case 0x0:
447 case 0x1:
448 switch (value) {
449 case 0:
450 memory->sramAccess = false;
451 break;
452 case 0xA:
453 memory->sramAccess = true;
454 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
455 break;
456 default:
457 // TODO
458 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
459 break;
460 }
461 break;
462 case 0x2:
463 bank = (memory->currentBank & 0x100) | value;
464 GBMBCSwitchBank(gb, bank);
465 break;
466 case 0x3:
467 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
468 GBMBCSwitchBank(gb, bank);
469 break;
470 case 0x4:
471 case 0x5:
472 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
473 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
474 value &= ~8;
475 }
476 GBMBCSwitchSramBank(gb, value & 0xF);
477 break;
478 default:
479 // TODO
480 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
481 break;
482 }
483}
484
485void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
486 // TODO
487 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
488 UNUSED(gb);
489 UNUSED(address);
490 UNUSED(value);
491}
492
493void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
494 int bank = value & 0x7F;
495 switch (address >> 13) {
496 case 0x0:
497 switch (value) {
498 default:
499 case 0:
500 gb->memory.mbcState.mbc7.access = 0;
501 break;
502 case 0xA:
503 gb->memory.mbcState.mbc7.access |= 1;
504 break;
505 }
506 break;
507 case 0x1:
508 GBMBCSwitchBank(gb, bank);
509 break;
510 case 0x2:
511 if (value == 0x40) {
512 gb->memory.mbcState.mbc7.access |= 2;
513 } else {
514 gb->memory.mbcState.mbc7.access &= ~2;
515 }
516 break;
517 case 0x5:
518 _GBMBC7Write(&gb->memory, address, value);
519 default:
520 // TODO
521 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
522 break;
523 }
524}
525
526uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
527 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
528 if (mbc7->access != 3) {
529 return 0xFF;
530 }
531 switch (address & 0xF0) {
532 case 0x20:
533 if (memory->rotation && memory->rotation->readTiltX) {
534 int32_t x = -memory->rotation->readTiltX(memory->rotation);
535 x >>= 21;
536 x += 0x81D0;
537 return x;
538 }
539 return 0xFF;
540 case 0x30:
541 if (memory->rotation && memory->rotation->readTiltX) {
542 int32_t x = -memory->rotation->readTiltX(memory->rotation);
543 x >>= 21;
544 x += 0x81D0;
545 return x >> 8;
546 }
547 return 7;
548 case 0x40:
549 if (memory->rotation && memory->rotation->readTiltY) {
550 int32_t y = -memory->rotation->readTiltY(memory->rotation);
551 y >>= 21;
552 y += 0x81D0;
553 return y;
554 }
555 return 0xFF;
556 case 0x50:
557 if (memory->rotation && memory->rotation->readTiltY) {
558 int32_t y = -memory->rotation->readTiltY(memory->rotation);
559 y >>= 21;
560 y += 0x81D0;
561 return y >> 8;
562 }
563 return 7;
564 case 0x60:
565 return 0;
566 case 0x80:
567 return mbc7->eeprom;
568 default:
569 return 0xFF;
570 }
571}
572
573static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
574 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
575 if (mbc7->access != 3) {
576 return;
577 }
578 switch (address & 0xF0) {
579 case 0x00:
580 mbc7->latch = (value & 0x55) == 0x55;
581 return;
582 case 0x10:
583 mbc7->latch |= (value & 0xAA);
584 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
585 memory->rotation->sample(memory->rotation);
586 }
587 mbc7->latch = 0;
588 return;
589 default:
590 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
591 return;
592 case 0x80:
593 break;
594 }
595 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
596 value = GBMBC7FieldFillDO(value); // Hi-Z
597 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
598 mbc7->state = GBMBC7_STATE_IDLE;
599 }
600 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
601 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
602 mbc7->sr <<= 1;
603 mbc7->sr |= GBMBC7FieldGetDI(value);
604 ++mbc7->srBits;
605 }
606 switch (mbc7->state) {
607 case GBMBC7_STATE_IDLE:
608 if (GBMBC7FieldIsDI(value)) {
609 mbc7->state = GBMBC7_STATE_READ_COMMAND;
610 mbc7->srBits = 0;
611 mbc7->sr = 0;
612 }
613 break;
614 case GBMBC7_STATE_READ_COMMAND:
615 if (mbc7->srBits == 10) {
616 mbc7->state = 0x10 | (mbc7->sr >> 6);
617 if (mbc7->state & 0xC) {
618 mbc7->state &= ~0x3;
619 }
620 mbc7->srBits = 0;
621 mbc7->address = mbc7->sr & 0x7F;
622 }
623 break;
624 case GBMBC7_STATE_DO:
625 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
626 mbc7->sr <<= 1;
627 --mbc7->srBits;
628 if (!mbc7->srBits) {
629 mbc7->state = GBMBC7_STATE_IDLE;
630 }
631 break;
632 default:
633 break;
634 }
635 switch (mbc7->state) {
636 case GBMBC7_STATE_EEPROM_EWEN:
637 mbc7->writable = true;
638 mbc7->state = GBMBC7_STATE_IDLE;
639 break;
640 case GBMBC7_STATE_EEPROM_EWDS:
641 mbc7->writable = false;
642 mbc7->state = GBMBC7_STATE_IDLE;
643 break;
644 case GBMBC7_STATE_EEPROM_WRITE:
645 if (mbc7->srBits == 16) {
646 if (mbc7->writable) {
647 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
648 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
649 }
650 mbc7->state = GBMBC7_STATE_IDLE;
651 }
652 break;
653 case GBMBC7_STATE_EEPROM_ERASE:
654 if (mbc7->writable) {
655 memory->sram[mbc7->address * 2] = 0xFF;
656 memory->sram[mbc7->address * 2 + 1] = 0xFF;
657 }
658 mbc7->state = GBMBC7_STATE_IDLE;
659 break;
660 case GBMBC7_STATE_EEPROM_READ:
661 mbc7->srBits = 16;
662 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
663 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
664 mbc7->state = GBMBC7_STATE_DO;
665 value = GBMBC7FieldClearDO(value);
666 break;
667 case GBMBC7_STATE_EEPROM_WRAL:
668 if (mbc7->srBits == 16) {
669 if (mbc7->writable) {
670 int i;
671 for (i = 0; i < 128; ++i) {
672 memory->sram[i * 2] = mbc7->sr >> 8;
673 memory->sram[i * 2 + 1] = mbc7->sr;
674 }
675 }
676 mbc7->state = GBMBC7_STATE_IDLE;
677 }
678 break;
679 case GBMBC7_STATE_EEPROM_ERAL:
680 if (mbc7->writable) {
681 int i;
682 for (i = 0; i < 128; ++i) {
683 memory->sram[i * 2] = 0xFF;
684 memory->sram[i * 2 + 1] = 0xFF;
685 }
686 }
687 mbc7->state = GBMBC7_STATE_IDLE;
688 break;
689 default:
690 break;
691 }
692 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
693 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
694 }
695 mbc7->eeprom = value;
696}
697
698void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
699 struct GBMemory* memory = &gb->memory;
700 int bank = value & 0x3F;
701 if (address & 0x1FFF) {
702 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
703 }
704
705 switch (address >> 13) {
706 case 0x0:
707 switch (value) {
708 case 0xA:
709 memory->sramAccess = true;
710 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
711 break;
712 default:
713 memory->sramAccess = false;
714 break;
715 }
716 break;
717 case 0x1:
718 GBMBCSwitchBank(gb, bank);
719 break;
720 case 0x2:
721 GBMBCSwitchSramBank(gb, bank);
722 break;
723 default:
724 // TODO
725 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
726 break;
727 }
728}
729
730void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
731 struct GBMemory* memory = &gb->memory;
732 int bank = value & 0x3F;
733 switch (address >> 13) {
734 case 0x0:
735 switch (value) {
736 case 0:
737 memory->sramAccess = false;
738 break;
739 case 0xA:
740 memory->sramAccess = true;
741 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
742 break;
743 default:
744 // TODO
745 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
746 break;
747 }
748 break;
749 case 0x1:
750 GBMBCSwitchBank(gb, bank);
751 break;
752 case 0x2:
753 if (value < 0x10) {
754 GBMBCSwitchSramBank(gb, value);
755 memory->mbcState.pocketCam.registersActive = false;
756 } else {
757 memory->mbcState.pocketCam.registersActive = true;
758 }
759 break;
760 default:
761 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
762 break;
763 }
764}
765
766uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
767 if (memory->mbcState.pocketCam.registersActive) {
768 return 0;
769 }
770 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
771}
772
773void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
774 struct GBMemory* memory = &gb->memory;
775 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
776 switch (address >> 13) {
777 case 0x5:
778 if (address & 1) {
779 tama5->reg = value;
780 } else {
781 value &= 0xF;
782 if (tama5->reg < GBTAMA5_MAX) {
783 tama5->registers[tama5->reg] = value;
784 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
785 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
786 switch (tama5->reg) {
787 case GBTAMA5_BANK_LO:
788 case GBTAMA5_BANK_HI:
789 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
790 break;
791 case GBTAMA5_WRITE_LO:
792 case GBTAMA5_WRITE_HI:
793 case GBTAMA5_CS:
794 break;
795 case GBTAMA5_ADDR_LO:
796 switch (tama5->registers[GBTAMA5_CS] >> 1) {
797 case 0x0: // RAM write
798 memory->sram[address] = out;
799 break;
800 case 0x1: // RAM read
801 break;
802 default:
803 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
804 }
805 break;
806 default:
807 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
808 break;
809 }
810 } else {
811 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
812 }
813 }
814 break;
815 default:
816 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
817 }
818}
819
820uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
821 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
822 if ((address & 0x1FFF) > 1) {
823 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
824 }
825 if (address & 1) {
826 return 0xFF;
827 } else {
828 uint8_t value = 0xF0;
829 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
830 switch (tama5->reg) {
831 case GBTAMA5_ACTIVE:
832 return 0xF1;
833 case GBTAMA5_READ_LO:
834 case GBTAMA5_READ_HI:
835 switch (tama5->registers[GBTAMA5_CS] >> 1) {
836 case 1:
837 value = memory->sram[address];
838 break;
839 default:
840 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
841 break;
842 }
843 if (tama5->reg == GBTAMA5_READ_HI) {
844 value >>= 4;
845 }
846 value |= 0xF0;
847 return value;
848 default:
849 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
850 return 0xF1;
851 }
852 }
853}
854
855void GBMBCRTCRead(struct GB* gb) {
856 struct GBMBCRTCSaveBuffer rtcBuffer;
857 struct VFile* vf = gb->sramVf;
858 if (!vf) {
859 return;
860 }
861 ssize_t end = vf->seek(vf, -sizeof(rtcBuffer), SEEK_END);
862 switch (end & 0x1FFF) {
863 case 0:
864 break;
865 case 0x1FFC:
866 vf->seek(vf, -sizeof(rtcBuffer) - 4, SEEK_END);
867 break;
868 default:
869 return;
870 }
871 vf->read(vf, &rtcBuffer, sizeof(rtcBuffer));
872
873 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
874 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
875 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
876 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
877 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
878 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
879}
880
881void GBMBCRTCWrite(struct GB* gb) {
882 struct VFile* vf = gb->sramVf;
883 if (!vf) {
884 return;
885 }
886
887 uint8_t rtcRegs[5];
888 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
889 time_t rtcLastLatch = gb->memory.rtcLastLatch;
890 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
891
892 struct GBMBCRTCSaveBuffer rtcBuffer;
893 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
894 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
895 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
896 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
897 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
898 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
899 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
900 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
901 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
902 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
903 STORE_64LE(rtcLastLatch, 0, &rtcBuffer.unixTime);
904
905 if (vf->size(vf) == gb->sramSize) {
906 // Writing past the end of the file can invalidate the file mapping
907 vf->unmap(vf, gb->memory.sram, gb->sramSize);
908 gb->memory.sram = NULL;
909 }
910 vf->seek(vf, gb->sramSize, SEEK_SET);
911 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
912 if (!gb->memory.sram) {
913 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
914 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
915 }
916}