1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ARM_H
  7#define ARM_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/cpu.h>
 14
 15enum {
 16	ARM_SP = 13,
 17	ARM_LR = 14,
 18	ARM_PC = 15
 19};
 20
 21enum ExecutionMode {
 22	MODE_ARM = 0,
 23	MODE_THUMB = 1
 24};
 25
 26enum PrivilegeMode {
 27	MODE_USER = 0x10,
 28	MODE_FIQ = 0x11,
 29	MODE_IRQ = 0x12,
 30	MODE_SUPERVISOR = 0x13,
 31	MODE_ABORT = 0x17,
 32	MODE_UNDEFINED = 0x1B,
 33	MODE_SYSTEM = 0x1F
 34};
 35
 36enum WordSize {
 37	WORD_SIZE_ARM = 4,
 38	WORD_SIZE_THUMB = 2
 39};
 40
 41enum ExecutionVector {
 42	BASE_RESET = 0x00000000,
 43	BASE_UNDEF = 0x00000004,
 44	BASE_SWI = 0x00000008,
 45	BASE_PABT = 0x0000000C,
 46	BASE_DABT = 0x00000010,
 47	BASE_IRQ = 0x00000018,
 48	BASE_FIQ = 0x0000001C
 49};
 50
 51enum RegisterBank {
 52	BANK_NONE = 0,
 53	BANK_FIQ = 1,
 54	BANK_IRQ = 2,
 55	BANK_SUPERVISOR = 3,
 56	BANK_ABORT = 4,
 57	BANK_UNDEFINED = 5
 58};
 59
 60enum LSMDirection {
 61	LSM_B = 1,
 62	LSM_D = 2,
 63	LSM_IA = 0,
 64	LSM_IB = 1,
 65	LSM_DA = 2,
 66	LSM_DB = 3
 67};
 68
 69struct ARMCore;
 70
 71union PSR {
 72	struct {
 73#if defined(__POWERPC__) || defined(__PPC__)
 74		unsigned n : 1;
 75		unsigned z : 1;
 76		unsigned c : 1;
 77		unsigned v : 1;
 78		unsigned unused : 20;
 79		unsigned i : 1;
 80		unsigned f : 1;
 81		unsigned t : 1;
 82		unsigned priv : 5;
 83#else
 84		unsigned priv : 5;
 85		unsigned t : 1;
 86		unsigned f : 1;
 87		unsigned i : 1;
 88		unsigned unused : 20;
 89		unsigned v : 1;
 90		unsigned c : 1;
 91		unsigned z : 1;
 92		unsigned n : 1;
 93#endif
 94	};
 95
 96	int32_t packed;
 97};
 98
 99struct ARMMemory {
100	uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
101	uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
102	uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
103
104	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
105	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
106	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
107
108	uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
109	                         int* cycleCounter);
110	uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
111	                          int* cycleCounter);
112
113	uint32_t* activeRegion;
114	uint32_t activeMask;
115	uint32_t activeSeqCycles32;
116	uint32_t activeSeqCycles16;
117	uint32_t activeNonseqCycles32;
118	uint32_t activeNonseqCycles16;
119	int32_t (*stall)(struct ARMCore*, int32_t wait);
120	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
121};
122
123struct ARMInterruptHandler {
124	void (*reset)(struct ARMCore* cpu);
125	void (*processEvents)(struct ARMCore* cpu);
126	void (*swi16)(struct ARMCore* cpu, int immediate);
127	void (*swi32)(struct ARMCore* cpu, int immediate);
128	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
129	void (*bkpt16)(struct ARMCore* cpu, int immediate);
130	void (*bkpt32)(struct ARMCore* cpu, int immediate);
131	void (*readCPSR)(struct ARMCore* cpu);
132	void (*writeCP15)(struct ARMCore*, int crn, int crm, int opcode1, int opcode2, uint32_t value);
133
134	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
135};
136
137DECL_BITFIELD(ARMCPUID, uint32_t);
138DECL_BITFIELD(ARMCacheType, uint32_t);
139DECL_BITFIELD(ARMTCMType, uint32_t);
140DECL_BITFIELD(ARMTLBType, uint32_t);
141DECL_BITFIELD(ARMMPUType, uint32_t);
142
143DECL_BITFIELD(ARMControlReg, uint32_t);
144DECL_BIT(ARMControlReg, M, 0);
145DECL_BIT(ARMControlReg, A, 1);
146DECL_BIT(ARMControlReg, C, 2);
147DECL_BIT(ARMControlReg, W, 3);
148DECL_BIT(ARMControlReg, P, 4);
149DECL_BIT(ARMControlReg, D, 5);
150DECL_BIT(ARMControlReg, L, 6);
151DECL_BIT(ARMControlReg, B, 7);
152DECL_BIT(ARMControlReg, S, 8);
153DECL_BIT(ARMControlReg, R, 9);
154DECL_BIT(ARMControlReg, F, 10);
155DECL_BIT(ARMControlReg, Z, 11);
156DECL_BIT(ARMControlReg, I, 12);
157DECL_BIT(ARMControlReg, V, 13);
158DECL_BIT(ARMControlReg, RR, 14);
159DECL_BIT(ARMControlReg, L4, 15);
160DECL_BIT(ARMControlReg, FI, 21);
161DECL_BIT(ARMControlReg, U, 22);
162DECL_BIT(ARMControlReg, XP, 23);
163DECL_BIT(ARMControlReg, VE, 24);
164DECL_BIT(ARMControlReg, EE, 25);
165DECL_BIT(ARMControlReg, L2, 26);
166
167DECL_BITFIELD(ARMCoprocessorAccess, uint32_t);
168
169DECL_BITFIELD(ARMCacheability, uint32_t);
170DECL_BIT(ARMCacheability, 0, 0);
171DECL_BIT(ARMCacheability, 1, 1);
172DECL_BIT(ARMCacheability, 2, 2);
173DECL_BIT(ARMCacheability, 3, 3);
174DECL_BIT(ARMCacheability, 4, 4);
175DECL_BIT(ARMCacheability, 5, 5);
176DECL_BIT(ARMCacheability, 6, 6);
177DECL_BIT(ARMCacheability, 7, 7);
178
179DECL_BITFIELD(ARMProtection, uint32_t);
180DECL_BIT(ARMProtection, Enable, 0);
181DECL_BITS(ARMProtection, Size, 1, 5);
182DECL_BITS(ARMProtection, Base, 12, 20);
183
184DECL_BITFIELD(ARMTCMControl, uint32_t);
185DECL_BITS(ARMTCMControl, VirtualSize, 1, 5);
186DECL_BITS(ARMTCMControl, Base, 12, 20);
187
188struct ARMCP15 {
189	struct {
190		ARMCPUID cpuid;
191		ARMCacheType cachetype;
192		ARMTCMType tcmtype;
193		ARMTLBType tlbtype;
194		ARMMPUType mputype;
195	} r0;
196	struct {
197		ARMControlReg c0;
198		uint32_t c1;
199		ARMCoprocessorAccess cpAccess;
200	} r1;
201	struct {
202		ARMCacheability d;
203		ARMCacheability i;
204	} r2;
205	struct {
206		ARMCacheability d;
207	} r3;
208	struct {
209		ARMProtection region[8];
210	} r6;
211	struct {
212		ARMTCMControl d;
213		ARMTCMControl i;
214	} r9;
215};
216
217struct ARMCore {
218	int32_t gprs[16];
219	union PSR cpsr;
220	union PSR spsr;
221
222	int32_t cycles;
223	int32_t nextEvent;
224	int halted;
225
226	int32_t bankedRegisters[6][7];
227	int32_t bankedSPSRs[6];
228
229	int32_t shifterOperand;
230	int32_t shifterCarryOut;
231
232	uint32_t prefetch[2];
233	enum ExecutionMode executionMode;
234	enum PrivilegeMode privilegeMode;
235
236	struct ARMMemory memory;
237	struct ARMInterruptHandler irqh;
238	struct ARMCP15 cp15;
239
240	struct mCPUComponent* master;
241
242	size_t numComponents;
243	struct mCPUComponent** components;
244};
245
246void ARMInit(struct ARMCore* cpu);
247void ARMDeinit(struct ARMCore* cpu);
248void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras);
249void ARMHotplugAttach(struct ARMCore* cpu, size_t slot);
250void ARMHotplugDetach(struct ARMCore* cpu, size_t slot);
251
252void ARMReset(struct ARMCore* cpu);
253void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
254void ARMRaiseIRQ(struct ARMCore*);
255void ARMRaiseSWI(struct ARMCore*);
256void ARMRaiseUndefined(struct ARMCore*);
257void ARMHalt(struct ARMCore*);
258
259void ARMv4Run(struct ARMCore* cpu);
260void ARMv4RunLoop(struct ARMCore* cpu);
261int32_t ARMv4RunCycles(struct ARMCore* cpu, int32_t cycles);
262void ARMv5Run(struct ARMCore* cpu);
263void ARMv5RunLoop(struct ARMCore* cpu);
264int32_t ARMv5RunCycles(struct ARMCore* cpu, int32_t cycles);
265void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
266
267CXX_GUARD_END
268
269#endif