src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 cpu->cpsr.n = ARM_SIGN(D); \
194 cpu->cpsr.z = !(D); \
195 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
196 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
197 }
198
199#define ARM_SUBTRACTION_S(M, N, D) \
200 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
201 cpu->cpsr = cpu->spsr; \
202 _ARMReadCPSR(cpu); \
203 } else { \
204 cpu->cpsr.n = ARM_SIGN(D); \
205 cpu->cpsr.z = !(D); \
206 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
207 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
208 }
209
210#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 cpu->cpsr.n = ARM_SIGN(D); \
216 cpu->cpsr.z = !(D); \
217 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
218 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
219 }
220
221#define ARM_NEUTRAL_S(M, N, D) \
222 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
223 cpu->cpsr = cpu->spsr; \
224 _ARMReadCPSR(cpu); \
225 } else { \
226 cpu->cpsr.n = ARM_SIGN(D); \
227 cpu->cpsr.z = !(D); \
228 cpu->cpsr.c = cpu->shifterCarryOut; \
229 }
230
231#define ARM_NEUTRAL_HI_S(DLO, DHI) \
232 cpu->cpsr.n = ARM_SIGN(DHI); \
233 cpu->cpsr.z = !((DHI) | (DLO));
234
235#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
236#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
237#define ADDR_MODE_2_ADDRESS (address)
238#define ADDR_MODE_2_RN (cpu->gprs[rn])
239#define ADDR_MODE_2_RM (cpu->gprs[rm])
240#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
241#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
242#define ADDR_MODE_2_WRITEBACK(ADDR) \
243 cpu->gprs[rn] = ADDR; \
244 if (UNLIKELY(rn == ARM_PC)) { \
245 ARM_WRITE_PC; \
246 }
247
248#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
249#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
250#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
251#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
252
253#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
254#define ADDR_MODE_3_RN ADDR_MODE_2_RN
255#define ADDR_MODE_3_RM ADDR_MODE_2_RM
256#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
257#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
258#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
259
260#define ADDR_MODE_4_WRITEBACK_LDM \
261 if (!((1 << rn) & rs)) { \
262 cpu->gprs[rn] = address; \
263 }
264
265#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
266
267#define ARM_LOAD_POST_BODY \
268 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
269 if (rd == ARM_PC) { \
270 ARM_WRITE_PC; \
271 }
272
273#define ARM_STORE_POST_BODY \
274 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
275
276#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
277 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
278 int currentCycles = ARM_PREFETCH_CYCLES; \
279 BODY; \
280 cpu->cycles += currentCycles; \
281 }
282
283#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
284 DEFINE_INSTRUCTION_ARM(NAME, \
285 int rd = (opcode >> 12) & 0xF; \
286 int rn = (opcode >> 16) & 0xF; \
287 UNUSED(rn); \
288 SHIFTER(cpu, opcode); \
289 BODY; \
290 S_BODY; \
291 if (rd == ARM_PC) { \
292 if (cpu->executionMode == MODE_ARM) { \
293 ARM_WRITE_PC; \
294 } else { \
295 THUMB_WRITE_PC; \
296 } \
297 })
298
299#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
310
311#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
317
318#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
319 DEFINE_INSTRUCTION_ARM(NAME, \
320 int rd = (opcode >> 16) & 0xF; \
321 int rs = (opcode >> 8) & 0xF; \
322 int rm = opcode & 0xF; \
323 if (rd == ARM_PC) { \
324 return; \
325 } \
326 ARM_WAIT_MUL(cpu->gprs[rs]); \
327 BODY; \
328 S_BODY; \
329 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
330
331#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
332 DEFINE_INSTRUCTION_ARM(NAME, \
333 int rd = (opcode >> 12) & 0xF; \
334 int rdHi = (opcode >> 16) & 0xF; \
335 int rs = (opcode >> 8) & 0xF; \
336 int rm = opcode & 0xF; \
337 if (rdHi == ARM_PC || rd == ARM_PC) { \
338 return; \
339 } \
340 currentCycles += cpu->memory.stall(cpu, WAIT); \
341 BODY; \
342 S_BODY; \
343 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
344
345#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
346 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
347 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
348
349#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
350 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
351 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
352
353#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
354 DEFINE_INSTRUCTION_ARM(NAME, \
355 uint32_t address; \
356 int rn = (opcode >> 16) & 0xF; \
357 int rd = (opcode >> 12) & 0xF; \
358 int rm = opcode & 0xF; \
359 UNUSED(rm); \
360 address = ADDRESS; \
361 WRITEBACK; \
362 BODY;)
363
364#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
370 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
371
372#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
383
384#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
385 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
386 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
387 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
397
398#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
401
402#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
403 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
404 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
405 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
406 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
408 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
409
410#define ARM_MS_PRE \
411 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
412 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
413
414#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
415
416#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
417 DEFINE_INSTRUCTION_ARM(NAME, \
418 int rn = (opcode >> 16) & 0xF; \
419 int rs = opcode & 0x0000FFFF; \
420 uint32_t address = cpu->gprs[rn]; \
421 S_PRE; \
422 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
423 S_POST; \
424 POST_BODY; \
425 WRITEBACK;)
426
427
428#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
429 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
430 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
431 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
432 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
433 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
434 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
435 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
436 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
437 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
438 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
439 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
440 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
441 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
442 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
443 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
444 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
445
446// Begin ALU definitions
447
448DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
449 int32_t n = cpu->gprs[rn];
450 cpu->gprs[rd] = n + cpu->shifterOperand;)
451
452DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
453 int32_t n = cpu->gprs[rn];
454 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
455
456DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
457 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
458
459DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
460 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
461
462DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
463 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
464
465DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
466 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
467
468DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
469 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
470
471DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
472 cpu->gprs[rd] = cpu->shifterOperand;)
473
474DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
475 cpu->gprs[rd] = ~cpu->shifterOperand;)
476
477DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
478 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
479
480DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
481 int32_t n = cpu->gprs[rn];
482 cpu->gprs[rd] = cpu->shifterOperand - n;)
483
484DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
485 int32_t n = cpu->gprs[rn];
486 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
487
488DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
489 int32_t n = cpu->gprs[rn];
490 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
491
492DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
493 int32_t n = cpu->gprs[rn];
494 cpu->gprs[rd] = n - cpu->shifterOperand;)
495
496DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
497 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
498
499DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
500 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
501
502// End ALU definitions
503
504// Begin multiply definitions
505
506DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
507DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
508
509DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
510 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
511 int32_t dm = cpu->gprs[rd];
512 int32_t dn = d;
513 cpu->gprs[rd] = dm + dn;
514 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
515 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
516
517DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
518 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
519 cpu->gprs[rd] = d;
520 cpu->gprs[rdHi] = d >> 32;,
521 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
522
523DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
524 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
525 int32_t dm = cpu->gprs[rd];
526 int32_t dn = d;
527 cpu->gprs[rd] = dm + dn;
528 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
529 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
530
531DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
532 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
533 cpu->gprs[rd] = d;
534 cpu->gprs[rdHi] = d >> 32;,
535 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
536
537// End multiply definitions
538
539// Begin load/store definitions
540
541DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
542DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
543DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
544DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
545DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
546DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
547DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
548DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
549
550DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
551 enum PrivilegeMode priv = cpu->privilegeMode;
552 ARMSetPrivilegeMode(cpu, MODE_USER);
553 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
554 ARMSetPrivilegeMode(cpu, priv);
555 cpu->gprs[rd] = r;
556 ARM_LOAD_POST_BODY;)
557
558DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
559 enum PrivilegeMode priv = cpu->privilegeMode;
560 ARMSetPrivilegeMode(cpu, MODE_USER);
561 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
562 ARMSetPrivilegeMode(cpu, priv);
563 cpu->gprs[rd] = r;
564 ARM_LOAD_POST_BODY;)
565
566DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
567 enum PrivilegeMode priv = cpu->privilegeMode;
568 int32_t r = cpu->gprs[rd];
569 ARMSetPrivilegeMode(cpu, MODE_USER);
570 cpu->memory.store8(cpu, address, r, ¤tCycles);
571 ARMSetPrivilegeMode(cpu, priv);
572 ARM_STORE_POST_BODY;)
573
574DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
575 enum PrivilegeMode priv = cpu->privilegeMode;
576 int32_t r = cpu->gprs[rd];
577 ARMSetPrivilegeMode(cpu, MODE_USER);
578 cpu->memory.store32(cpu, address, r, ¤tCycles);
579 ARMSetPrivilegeMode(cpu, priv);
580 ARM_STORE_POST_BODY;)
581
582DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
583 load,
584 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
585 if (rs & 0x8000) {
586 ARM_WRITE_PC;
587 })
588
589DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
590 store,
591 ARM_STORE_POST_BODY;)
592
593DEFINE_INSTRUCTION_ARM(SWP,
594 int rm = opcode & 0xF;
595 int rd = (opcode >> 12) & 0xF;
596 int rn = (opcode >> 16) & 0xF;
597 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
598 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
599 cpu->gprs[rd] = d;)
600
601DEFINE_INSTRUCTION_ARM(SWPB,
602 int rm = opcode & 0xF;
603 int rd = (opcode >> 12) & 0xF;
604 int rn = (opcode >> 16) & 0xF;
605 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
606 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
607 cpu->gprs[rd] = d;)
608
609// End load/store definitions
610
611// Begin branch definitions
612
613DEFINE_INSTRUCTION_ARM(B,
614 int32_t offset = opcode << 8;
615 offset >>= 6;
616 cpu->gprs[ARM_PC] += offset;
617 ARM_WRITE_PC;)
618
619DEFINE_INSTRUCTION_ARM(BL,
620 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
621 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
622 cpu->gprs[ARM_PC] += immediate >> 6;
623 ARM_WRITE_PC;)
624
625DEFINE_INSTRUCTION_ARM(BX,
626 int rm = opcode & 0x0000000F;
627 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
628 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
629 if (cpu->executionMode == MODE_THUMB) {
630 THUMB_WRITE_PC;
631 } else {
632 ARM_WRITE_PC;
633
634 })
635DEFINE_INSTRUCTION_ARM(BLX2,
636 int rm = opcode & 0x0000000F;
637 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
638 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
639 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
640 if (cpu->executionMode == MODE_THUMB) {
641 THUMB_WRITE_PC;
642 } else {
643 ARM_WRITE_PC;
644 })
645
646// End branch definitions
647
648// Begin coprocessor definitions
649
650#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
651 DEFINE_INSTRUCTION_ARM(NAME, \
652 int op1 = (opcode >> 21) & 7; \
653 int op2 = (opcode >> 5) & 7; \
654 int rd = (opcode >> 12) & 0xF; \
655 int cp = (opcode >> 8) & 0xF; \
656 int crn = (opcode >> 16) & 0xF; \
657 int crm = opcode & 0xF; \
658 UNUSED(op1); \
659 UNUSED(op2); \
660 UNUSED(rd); \
661 UNUSED(crn); \
662 UNUSED(crm); \
663 BODY;)
664
665DEFINE_COPROCESSOR_INSTRUCTION(MRC, ARM_STUB)
666
667DEFINE_COPROCESSOR_INSTRUCTION(MCR,
668 if (cp == 15 && cpu->irqh.writeCP15) {
669 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
670 } else {
671 ARM_STUB;
672 })
673
674DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
675DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
676DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
677
678// Begin miscellaneous definitions
679
680DEFINE_INSTRUCTION_ARM(CLZ,
681 int rm = opcode & 0xF;
682 int rd = (opcode >> 12) & 0xF;
683 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
684
685DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
686DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
687
688DEFINE_INSTRUCTION_ARM(MSR,
689 int c = opcode & 0x00010000;
690 int f = opcode & 0x00080000;
691 int32_t operand = cpu->gprs[opcode & 0x0000000F];
692 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
693 if (mask & PSR_USER_MASK) {
694 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
695 }
696 if (mask & PSR_STATE_MASK) {
697 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
698 }
699 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
700 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
701 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
702 }
703 _ARMReadCPSR(cpu);
704 if (cpu->executionMode == MODE_THUMB) {
705 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
706 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
707 } else {
708 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
709 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
710 })
711
712DEFINE_INSTRUCTION_ARM(MSRR,
713 int c = opcode & 0x00010000;
714 int f = opcode & 0x00080000;
715 int32_t operand = cpu->gprs[opcode & 0x0000000F];
716 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
717 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
718 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
719
720DEFINE_INSTRUCTION_ARM(MRS, \
721 int rd = (opcode >> 12) & 0xF; \
722 cpu->gprs[rd] = cpu->cpsr.packed;)
723
724DEFINE_INSTRUCTION_ARM(MRSR, \
725 int rd = (opcode >> 12) & 0xF; \
726 cpu->gprs[rd] = cpu->spsr.packed;)
727
728DEFINE_INSTRUCTION_ARM(MSRI,
729 int c = opcode & 0x00010000;
730 int f = opcode & 0x00080000;
731 int rotate = (opcode & 0x00000F00) >> 7;
732 int32_t operand = ROR(opcode & 0x000000FF, rotate);
733 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
734 if (mask & PSR_USER_MASK) {
735 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
736 }
737 if (mask & PSR_STATE_MASK) {
738 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
739 }
740 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
741 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
742 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
743 }
744 _ARMReadCPSR(cpu);
745 if (cpu->executionMode == MODE_THUMB) {
746 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
747 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
748 } else {
749 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
750 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
751 })
752
753DEFINE_INSTRUCTION_ARM(MSRRI,
754 int c = opcode & 0x00010000;
755 int f = opcode & 0x00080000;
756 int rotate = (opcode & 0x00000F00) >> 7;
757 int32_t operand = ROR(opcode & 0x000000FF, rotate);
758 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
759 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
760 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
761
762DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
763
764const ARMInstruction _armv4Table[0x1000] = {
765 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
766};
767
768const ARMInstruction _armv5Table[0x1000] = {
769 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
770};