src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count);
14
15static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
16static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 4, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
17static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
18static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
19static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
20static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
21static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
22
23void GBAMemoryInit(struct GBAMemory* memory) {
24 memory->d.load32 = GBALoad32;
25 memory->d.load16 = GBALoad16;
26 memory->d.loadU16 = GBALoadU16;
27 memory->d.load8 = GBALoad8;
28 memory->d.loadU8 = GBALoadU8;
29 memory->d.store32 = GBAStore32;
30 memory->d.store16 = GBAStore16;
31 memory->d.store8 = GBAStore8;
32
33 memory->bios = (uint32_t*) hleBios;
34 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
35 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
36 memory->rom = 0;
37 memset(memory->io, 0, sizeof(memory->io));
38 memset(memory->dma, 0, sizeof(memory->dma));
39
40 if (!memory->wram || !memory->iwram) {
41 GBAMemoryDeinit(memory);
42 memory->p->errno = GBA_OUT_OF_MEMORY;
43 memory->p->errstr = GBA_CANNOT_MMAP;
44 }
45
46 GBASavedataInit(&memory->savedata, "test.sav");
47
48 int i;
49 for (i = 0; i < 16; ++i) {
50 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
51 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
52 memory->waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
53 memory->waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
54 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
55 memory->waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
56 }
57 for (; i < 256; ++i) {
58 memory->waitstates16[i] = 0;
59 memory->waitstatesSeq16[i] = 0;
60 memory->waitstatesPrefetch16[i] = 0;
61 memory->waitstates32[i] = 0;
62 memory->waitstatesSeq32[i] = 0;
63 memory->waitstatesPrefetch32[i] = 0;
64 }
65
66 memory->activeRegion = 0;
67 memory->d.activeRegion = 0;
68 memory->d.activeMask = 0;
69 memory->d.setActiveRegion = GBASetActiveRegion;
70 memory->d.activePrefetchCycles32 = 0;
71 memory->d.activePrefetchCycles16 = 0;
72 memory->d.waitMultiple = GBAWaitMultiple;
73}
74
75void GBAMemoryDeinit(struct GBAMemory* memory) {
76 munmap(memory->wram, SIZE_WORKING_RAM);
77 munmap(memory->iwram, SIZE_WORKING_IRAM);
78 GBASavedataDeinit(&memory->savedata);
79}
80
81static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
82 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
83
84 gbaMemory->activeRegion = address >> BASE_OFFSET;
85 memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[gbaMemory->activeRegion];
86 memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[gbaMemory->activeRegion];
87 memory->activeNonseqCycles32 = gbaMemory->waitstates32[gbaMemory->activeRegion];
88 memory->activeNonseqCycles16 = gbaMemory->waitstates16[gbaMemory->activeRegion];
89 switch (address & ~OFFSET_MASK) {
90 case BASE_BIOS:
91 memory->activeRegion = gbaMemory->bios;
92 memory->activeMask = SIZE_BIOS - 1;
93 break;
94 case BASE_WORKING_RAM:
95 memory->activeRegion = gbaMemory->wram;
96 memory->activeMask = SIZE_WORKING_RAM - 1;
97 break;
98 case BASE_WORKING_IRAM:
99 memory->activeRegion = gbaMemory->iwram;
100 memory->activeMask = SIZE_WORKING_IRAM - 1;
101 break;
102 case BASE_CART0:
103 case BASE_CART0_EX:
104 case BASE_CART1:
105 case BASE_CART1_EX:
106 case BASE_CART2:
107 case BASE_CART2_EX:
108 memory->activeRegion = gbaMemory->rom;
109 memory->activeMask = SIZE_CART0 - 1;
110 break;
111 default:
112 memory->activeRegion = 0;
113 memory->activeMask = 0;
114 break;
115 }
116 gbaMemory->p->cpu.cycles += 1 + (gbaMemory->p->cpu.executionMode == MODE_ARM ? gbaMemory->waitstates32[address >> BASE_OFFSET] : gbaMemory->waitstates16[address >> BASE_OFFSET]);
117}
118
119int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
120 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
121 uint32_t value = 0;
122 int wait = 0;
123
124 switch (address & ~OFFSET_MASK) {
125 case BASE_BIOS:
126 break;
127 case BASE_WORKING_RAM:
128 value = gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
129 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
130 break;
131 case BASE_WORKING_IRAM:
132 value = gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
133 break;
134 case BASE_IO:
135 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1)) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
136 break;
137 case BASE_PALETTE_RAM:
138 value = ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2];
139 break;
140 case BASE_VRAM:
141 value = ((int32_t*) gbaMemory->p->video.renderer->vram)[(address & 0x0001FFFF) >> 2];
142 break;
143 case BASE_OAM:
144 value = ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2];
145 break;
146 case BASE_CART0:
147 case BASE_CART0_EX:
148 case BASE_CART1:
149 case BASE_CART1_EX:
150 case BASE_CART2:
151 case BASE_CART2_EX:
152 wait = gbaMemory->waitstates32[address >> BASE_OFFSET];
153 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
154 value = gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
155 }
156 break;
157 case BASE_CART_SRAM:
158 break;
159 default:
160 break;
161 }
162
163
164 if (cycleCounter) {
165 *cycleCounter += 2 + wait;
166 }
167 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
168 int rotate = (address & 3) << 3;
169 return (value >> rotate) | (value << (32 - rotate));
170}
171
172uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
173 return GBALoad16(memory, address, cycleCounter);
174}
175
176int16_t GBALoad16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
177 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
178 int16_t value = 0;
179 int wait = 0;
180
181 switch (address & ~OFFSET_MASK) {
182 case BASE_BIOS:
183 break;
184 case BASE_WORKING_RAM:
185 value = ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
186 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
187 break;
188 case BASE_WORKING_IRAM:
189 value = ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
190 break;
191 case BASE_IO:
192 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
193 break;
194 case BASE_PALETTE_RAM:
195 value = gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
196 break;
197 case BASE_VRAM:
198 value = gbaMemory->p->video.renderer->vram[(address & 0x0001FFFF) >> 1];
199 break;
200 case BASE_OAM:
201 value = gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1];
202 break;
203 case BASE_CART0:
204 case BASE_CART0_EX:
205 case BASE_CART1:
206 case BASE_CART1_EX:
207 case BASE_CART2:
208 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
209 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
210 value = ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
211 }
212 break;
213 case BASE_CART2_EX:
214 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
215 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
216 value = GBASavedataReadEEPROM(&gbaMemory->savedata);
217 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
218 value = ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
219 }
220 break;
221 case BASE_CART_SRAM:
222 break;
223 default:
224 break;
225 }
226
227 if (cycleCounter) {
228 *cycleCounter += 2 + wait;
229 }
230 return value;
231}
232
233uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
234 return GBALoad8(memory, address, cycleCounter);
235}
236
237int8_t GBALoad8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
238 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
239 int8_t value = 0;
240 int wait = 0;
241
242 switch (address & ~OFFSET_MASK) {
243 case BASE_BIOS:
244 break;
245 case BASE_WORKING_RAM:
246 value = ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
247 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
248 break;
249 case BASE_WORKING_IRAM:
250 value = ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
251 break;
252 case BASE_IO:
253 value = (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
254 break;
255 case BASE_PALETTE_RAM:
256 break;
257 case BASE_VRAM:
258 break;
259 case BASE_OAM:
260 break;
261 case BASE_CART0:
262 case BASE_CART0_EX:
263 case BASE_CART1:
264 case BASE_CART1_EX:
265 case BASE_CART2:
266 case BASE_CART2_EX:
267 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
268 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
269 value = ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
270 }
271 break;
272 case BASE_CART_SRAM:
273 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
274 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
275 GBASavedataInitSRAM(&gbaMemory->savedata);
276 }
277 value = gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
278 default:
279 break;
280 }
281
282 if (cycleCounter) {
283 *cycleCounter += 2 + wait;
284 }
285 return value;
286}
287
288void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value, int* cycleCounter) {
289 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
290 int wait = 0;
291
292 switch (address & ~OFFSET_MASK) {
293 case BASE_WORKING_RAM:
294 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
295 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
296 break;
297 case BASE_WORKING_IRAM:
298 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
299 break;
300 case BASE_IO:
301 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
302 break;
303 case BASE_PALETTE_RAM:
304 ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2] = value;
305 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
306 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
307 break;
308 case BASE_VRAM:
309 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
310 ((int32_t*) gbaMemory->p->video.renderer->vram)[(address & 0x0001FFFF) >> 2] = value;
311 }
312 break;
313 case BASE_OAM:
314 ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2] = value;
315 break;
316 case BASE_CART0:
317 break;
318 case BASE_CART_SRAM:
319 break;
320 default:
321 break;
322 }
323
324 if (cycleCounter) {
325 *cycleCounter += 1 + wait;
326 }
327}
328
329void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value, int* cycleCounter) {
330 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
331 int wait = 0;
332
333 switch (address & ~OFFSET_MASK) {
334 case BASE_WORKING_RAM:
335 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
336 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
337 break;
338 case BASE_WORKING_IRAM:
339 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
340 break;
341 case BASE_IO:
342 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
343 break;
344 case BASE_PALETTE_RAM:
345 gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1] = value;
346 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
347 break;
348 case BASE_VRAM:
349 if ((address & OFFSET_MASK) < SIZE_VRAM) {
350 gbaMemory->p->video.renderer->vram[(address & 0x0001FFFF) >> 1] = value;
351 }
352 break;
353 case BASE_OAM:
354 gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1] = value;
355 break;
356 case BASE_CART0:
357 break;
358 case BASE_CART2_EX:
359 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
360 GBASavedataInitEEPROM(&gbaMemory->savedata);
361 }
362 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
363 break;
364 case BASE_CART_SRAM:
365 break;
366 default:
367 break;
368 }
369
370 if (cycleCounter) {
371 *cycleCounter += 1 + wait;
372 }
373}
374
375void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value, int* cycleCounter) {
376 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
377 int wait = 0;
378
379 switch (address & ~OFFSET_MASK) {
380 case BASE_WORKING_RAM:
381 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
382 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
383 break;
384 case BASE_WORKING_IRAM:
385 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
386 break;
387 case BASE_IO:
388 break;
389 case BASE_PALETTE_RAM:
390 break;
391 case BASE_VRAM:
392 break;
393 case BASE_OAM:
394 break;
395 case BASE_CART0:
396 break;
397 case BASE_CART_SRAM:
398 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
399 if (address == SAVEDATA_FLASH_BASE) {
400 GBASavedataInitFlash(&gbaMemory->savedata);
401 } else {
402 GBASavedataInitSRAM(&gbaMemory->savedata);
403 }
404 }
405 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
406 GBASavedataWriteFlash(&gbaMemory->savedata, value);
407 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
408 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
409 }
410 wait = gbaMemory->waitstates16[REGION_CART_SRAM];
411 break;
412 default:
413 break;
414 }
415
416 if (cycleCounter) {
417 *cycleCounter += 1 + wait;
418 }
419}
420
421static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count) {
422 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
423 int wait = 1 + gbaMemory->waitstates32[startAddress >> BASE_OFFSET];
424 wait += (1 + gbaMemory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
425 return wait;
426}
427
428void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
429 int sram = parameters & 0x0003;
430 int ws0 = (parameters & 0x000C) >> 2;
431 int ws0seq = (parameters & 0x0010) >> 4;
432 int ws1 = (parameters & 0x0060) >> 5;
433 int ws1seq = (parameters & 0x0080) >> 7;
434 int ws2 = (parameters & 0x0300) >> 8;
435 int ws2seq = (parameters & 0x0400) >> 10;
436 int prefetch = parameters & 0x4000;
437
438 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
439 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
440 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
441 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
442
443 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
444 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
445 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
446
447 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
448 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
449 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
450
451 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
452 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
453 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
454
455 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
456 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
457 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
458
459 if (!prefetch) {
460 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
461 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
462 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
463
464 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
465 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
466 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
467 } else {
468 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
469 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
470 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
471
472 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
473 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
474 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
475 }
476
477 memory->d.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
478 memory->d.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
479 memory->d.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
480 memory->d.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
481}
482
483int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
484 struct GBADMA* dma;
485 int32_t test = INT_MAX;
486
487 dma = &memory->dma[0];
488 dma->nextIRQ -= cycles;
489 if (dma->enable && dma->doIrq && dma->nextIRQ) {
490 if (dma->nextIRQ <= 0) {
491 dma->nextIRQ = INT_MAX;
492 GBARaiseIRQ(memory->p, IRQ_DMA0);
493 } else if (dma->nextIRQ < test) {
494 test = dma->nextIRQ;
495 }
496 }
497
498 dma = &memory->dma[1];
499 dma->nextIRQ -= cycles;
500 if (dma->enable && dma->doIrq && dma->nextIRQ) {
501 if (dma->nextIRQ <= 0) {
502 dma->nextIRQ = INT_MAX;
503 GBARaiseIRQ(memory->p, IRQ_DMA1);
504 } else if (dma->nextIRQ < test) {
505 test = dma->nextIRQ;
506 }
507 }
508
509 dma = &memory->dma[2];
510 dma->nextIRQ -= cycles;
511 if (dma->enable && dma->doIrq && dma->nextIRQ) {
512 if (dma->nextIRQ <= 0) {
513 dma->nextIRQ = INT_MAX;
514 GBARaiseIRQ(memory->p, IRQ_DMA2);
515 } else if (dma->nextIRQ < test) {
516 test = dma->nextIRQ;
517 }
518 }
519
520 dma = &memory->dma[3];
521 dma->nextIRQ -= cycles;
522 if (dma->enable && dma->doIrq && dma->nextIRQ) {
523 if (dma->nextIRQ <= 0) {
524 dma->nextIRQ = INT_MAX;
525 GBARaiseIRQ(memory->p, IRQ_DMA3);
526 } else if (dma->nextIRQ < test) {
527 test = dma->nextIRQ;
528 }
529 }
530
531 return test;
532}
533
534void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
535 memory->dma[dma].source = address & 0xFFFFFFFE;
536}
537
538void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
539 memory->dma[dma].dest = address & 0xFFFFFFFE;
540}
541
542void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
543 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
544}
545
546uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
547 struct GBADMA* currentDma = &memory->dma[dma];
548 int wasEnabled = currentDma->enable;
549 currentDma->packed = control;
550 currentDma->nextIRQ = 0;
551
552 if (currentDma->drq) {
553 GBALog(GBA_LOG_STUB, "DRQ not implemented");
554 }
555
556 if (!wasEnabled && currentDma->enable) {
557 currentDma->nextSource = currentDma->source;
558 currentDma->nextDest = currentDma->dest;
559 currentDma->nextCount = currentDma->count;
560 GBAMemoryScheduleDMA(memory, dma, currentDma);
561 }
562 // If the DMA has already occurred, this value might have changed since the function started
563 return currentDma->packed;
564};
565
566void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
567 switch (info->timing) {
568 case DMA_TIMING_NOW:
569 GBAMemoryServiceDMA(memory, number, info);
570 break;
571 case DMA_TIMING_HBLANK:
572 // Handled implicitly
573 break;
574 case DMA_TIMING_VBLANK:
575 // Handled implicitly
576 break;
577 case DMA_TIMING_CUSTOM:
578 switch (number) {
579 case 0:
580 GBALog(GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
581 break;
582 case 1:
583 case 2:
584 //this.cpu.irq.audio.scheduleFIFODma(number, info);
585 break;
586 case 3:
587 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
588 break;
589 }
590 }
591}
592
593void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
594 struct GBADMA* dma;
595 int i;
596 for (i = 0; i < 4; ++i) {
597 dma = &memory->dma[i];
598 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
599 GBAMemoryServiceDMA(memory, i, dma);
600 }
601 }
602}
603
604void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
605 struct GBADMA* dma;
606 int i;
607 for (i = 0; i < 4; ++i) {
608 dma = &memory->dma[i];
609 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
610 GBAMemoryServiceDMA(memory, i, dma);
611 }
612 }
613}
614
615void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
616 if (!info->enable) {
617 // There was a DMA scheduled that got canceled
618 return;
619 }
620
621 uint32_t width = info->width ? 4 : 2;
622 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
623 int destOffset = DMA_OFFSET[info->dstControl] * width;
624 int32_t wordsRemaining = info->nextCount;
625 uint32_t source = info->nextSource;
626 uint32_t dest = info->nextDest;
627 uint32_t sourceRegion = source >> BASE_OFFSET;
628 uint32_t destRegion = dest >> BASE_OFFSET;
629
630 if (width == 4) {
631 int32_t word;
632 source &= 0xFFFFFFFC;
633 dest &= 0xFFFFFFFC;
634 while (wordsRemaining--) {
635 word = GBALoad32(&memory->d, source, 0);
636 GBAStore32(&memory->d, dest, word, 0);
637 source += sourceOffset;
638 dest += destOffset;
639 }
640 } else {
641 uint16_t word;
642 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
643 while (wordsRemaining--) {
644 word = GBASavedataReadEEPROM(&memory->savedata);
645 GBAStore16(&memory->d, dest, word, 0);
646 source += sourceOffset;
647 dest += destOffset;
648 }
649 } else if (destRegion == REGION_CART2_EX) {
650 if (memory->savedata.type != SAVEDATA_EEPROM) {
651 GBASavedataInitEEPROM(&memory->savedata);
652 }
653 while (wordsRemaining) {
654 word = GBALoadU16(&memory->d, source, 0);
655 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
656 source += sourceOffset;
657 dest += destOffset;
658 --wordsRemaining;
659 }
660 } else {
661 while (wordsRemaining--) {
662 word = GBALoadU16(&memory->d, source, 0);
663 GBAStore16(&memory->d, dest, word, 0);
664 source += sourceOffset;
665 dest += destOffset;
666 }
667 }
668 }
669
670 if (info->doIrq) {
671 info->nextIRQ = memory->p->cpu.cycles + 2;
672 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
673 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
674 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
675 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
676 }
677
678 info->nextSource = source;
679 info->nextDest = dest;
680 info->nextCount = wordsRemaining;
681
682 if (!info->repeat) {
683 info->enable = 0;
684
685 // Clear the enable bit in memory
686 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
687 } else {
688 info->nextCount = info->count;
689 if (info->dstControl == DMA_INCREMENT_RELOAD) {
690 info->nextDest = info->dest;
691 }
692 GBAMemoryScheduleDMA(memory, number, info);
693 }
694}