src/ds/slot1.c (view raw)
1/* Copyright (c) 2013-2017 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/slot1.h>
7
8#include <mgba/internal/arm/macros.h>
9#include <mgba/internal/ds/ds.h>
10#include <mgba/internal/ds/dma.h>
11#include <mgba-util/math.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(DS_SLOT1, "DS Slot-1", "ds.slot1");
15
16static void _slot1SPI(struct mTiming*, void* context, uint32_t cyclesLate);
17static void _transferEvent(struct mTiming* timing, void* context, uint32_t cyclesLate);
18static bool _slot1GuaranteeSize(struct DSSlot1*);
19
20void DSSlot1SPIInit(struct DS* ds, struct VFile* vf) {
21 ds->memory.slot1.spiEvent.name = "DS Slot-1 SPI";
22 ds->memory.slot1.spiEvent.priority = 0x70;
23 ds->memory.slot1.spiEvent.context = NULL;
24 ds->memory.slot1.spiEvent.callback = _slot1SPI;
25 ds->memory.slot1.transferEvent.name = "DS Slot-1 Transfer";
26 ds->memory.slot1.transferEvent.priority = 0x71;
27 ds->memory.slot1.transferEvent.context = ds;
28 ds->memory.slot1.transferEvent.callback = _transferEvent;
29 ds->memory.slot1.savedataType = DS_SAVEDATA_AUTODETECT;
30 ds->memory.slot1.spiVf = vf;
31 ds->memory.slot1.spiRealVf = vf;
32 ds->memory.slot1.spiData = NULL;
33}
34
35void DSSlot1Reset(struct DS* ds) {
36 ds->memory.slot1.statusReg = 0;
37 ds->memory.slot1.spiCommand = 0;
38 ds->memory.slot1.spiHoldEnabled = 0;
39 ds->memory.slot1.dmaSource = -1;
40}
41
42static void _scheduleTransfer(struct DS* ds, struct mTiming* timing, uint32_t cyclesLate) {
43 DSSlot1ROMCNT romcnt = ds->memory.io7[DS_REG_ROMCNT_HI >> 1] << 16;
44 uint32_t cycles;
45 if (DSSlot1ROMCNTIsTransferRate(romcnt)) {
46 cycles = 8;
47 } else {
48 cycles = 5;
49 }
50 if (!ds->ds7.memory.slot1Access) {
51 cycles <<= 1;
52 }
53 cycles -= cyclesLate;
54 mTimingDeschedule(timing, &ds->memory.slot1.transferEvent);
55 mTimingSchedule(timing, &ds->memory.slot1.transferEvent, cycles);
56}
57
58static void _transferEvent(struct mTiming* timing, void* context, uint32_t cyclesLate) {
59 struct DS* ds = context;
60 DSSlot1ROMCNT romcnt;
61 // TODO: Big endian
62 LOAD_32(romcnt, DS_REG_ROMCNT_LO, ds->memory.io7);
63
64 struct DSCommon* dscore;
65 if (ds->ds7.memory.slot1Access) {
66 dscore = &ds->ds7;
67 } else {
68 dscore = &ds->ds9;
69 }
70
71 struct GBADMA* dma = NULL;
72 if (ds->memory.slot1.dmaSource >= 0) {
73 dma = &dscore->memory.dma[ds->memory.slot1.dmaSource];
74 }
75 bool hasDMA = false;
76 if (dma) {
77 if (ds->ds7.memory.slot1Access && GBADMARegisterGetTiming(dma->reg) == DS7_DMA_TIMING_SLOT1) {
78 hasDMA = true;
79 }
80 if (ds->ds9.memory.slot1Access && GBADMARegisterGetTiming9(dma->reg) == DS9_DMA_TIMING_SLOT1) {
81 hasDMA = true;
82 }
83 if (!GBADMARegisterIsEnable(dma->reg)) {
84 hasDMA = false;
85 }
86 }
87 if (!hasDMA) {
88 ds->memory.slot1.dmaSource = -1;
89 }
90
91 if (ds->memory.slot1.transferRemaining) {
92 ds->romVf->read(ds->romVf, ds->memory.slot1.readBuffer, 4);
93 // TODO: Error check
94 ds->memory.slot1.address += 4;
95 ds->memory.slot1.transferRemaining -= 4;
96 romcnt = DSSlot1ROMCNTFillWordReady(romcnt);
97
98 if (hasDMA) {
99 dma->when = mTimingCurrentTime(timing);
100 dma->nextCount = 1;
101 DSDMAUpdate(dscore);
102 }
103 } else {
104 DSSlot1AUXSPICNT config = ds->memory.io7[DS_REG_AUXSPICNT >> 1];
105 memset(ds->memory.slot1.readBuffer, 0, 4);
106 romcnt = DSSlot1ROMCNTClearWordReady(romcnt);
107 romcnt = DSSlot1ROMCNTClearBlockBusy(romcnt);
108 if (DSSlot1AUXSPICNTIsDoIRQ(config)) {
109 DSRaiseIRQ(dscore->cpu, dscore->memory.io, DS_IRQ_SLOT1_TRANS);
110 }
111 if (hasDMA) {
112 dma->reg = GBADMARegisterClearEnable(dma->reg);
113 dma->reg = GBADMARegisterClearRepeat(dma->reg);
114 dscore->memory.io[(DS_REG_DMA0CNT_HI + ds->memory.slot1.dmaSource * (DS_REG_DMA1CNT_HI - DS_REG_DMA0CNT_HI)) >> 1] = dma->reg;
115 }
116 }
117 STORE_32(romcnt, DS_REG_ROMCNT_LO, ds->memory.io7);
118 STORE_32(romcnt, DS_REG_ROMCNT_LO, ds->memory.io9);
119}
120
121static void DSSlot1StartTransfer(struct DS* ds) {
122 size_t i;
123 for (i = 0; i < 8; i += 2) {
124 uint16_t bytes;
125 LOAD_16(bytes, DS_REG_ROMCMD_0 + i, ds->memory.io7);
126 ds->memory.slot1.command[i] = bytes & 0xFF;
127 ds->memory.slot1.command[i + 1] = bytes >> 8;
128 }
129 switch (ds->memory.slot1.command[0]) {
130 case 0xB7:
131 ds->memory.slot1.address = ds->memory.slot1.command[1] << 24;
132 ds->memory.slot1.address |= ds->memory.slot1.command[2] << 16;
133 ds->memory.slot1.address |= ds->memory.slot1.command[3] << 8;
134 ds->memory.slot1.address |= ds->memory.slot1.command[4];
135 if (ds->memory.slot1.address < 0x8000) {
136 mLOG(DS_SLOT1, GAME_ERROR, "Invalid read from secure area: %04X", ds->memory.slot1.address);
137 ds->memory.slot1.address = 0x8000 + (ds->memory.slot1.address & 0x1FF);
138 }
139 if (ds->romVf) {
140 ds->romVf->seek(ds->romVf, ds->memory.slot1.address, SEEK_SET);
141 }
142 ds->memory.slot1.transferRemaining = ds->memory.slot1.transferSize;
143 if (ds->ds7.memory.slot1Access) {
144 _scheduleTransfer(ds, &ds->ds7.timing, 0);
145 } else {
146 _scheduleTransfer(ds, &ds->ds9.timing, 0);
147 }
148 break;
149 case 0xB8:
150 memcpy(ds->memory.slot1.readBuffer, DS_CHIP_ID, 4);
151 ds->memory.slot1.transferRemaining = 0;
152 break;
153 default:
154 mLOG(DS_SLOT1, STUB, "Unimplemented card command: %02X%02X%02X%02X%02X%02X%02X%02X",
155 ds->memory.slot1.command[0], ds->memory.slot1.command[1],
156 ds->memory.slot1.command[2], ds->memory.slot1.command[3],
157 ds->memory.slot1.command[4], ds->memory.slot1.command[5],
158 ds->memory.slot1.command[6], ds->memory.slot1.command[7]);
159 break;
160 }
161}
162
163DSSlot1AUXSPICNT DSSlot1Configure(struct DS* ds, DSSlot1AUXSPICNT config) {
164 if (DSSlot1AUXSPICNTIsSPIMode(config)) {
165 if (!ds->memory.slot1.spiHoldEnabled) {
166 ds->memory.slot1.spiCommand = 0;
167 }
168 ds->memory.slot1.spiHoldEnabled = DSSlot1AUXSPICNTIsCSHold(config);
169 }
170 return config;
171}
172
173DSSlot1ROMCNT DSSlot1Control(struct DS* ds, DSSlot1ROMCNT control) {
174 ds->memory.slot1.transferSize = DSSlot1ROMCNTGetBlockSize(control);
175 if (ds->memory.slot1.transferSize != 0 && ds->memory.slot1.transferSize != 7) {
176 ds->memory.slot1.transferSize = 0x100 << ds->memory.slot1.transferSize;
177 }
178
179 DSSlot1AUXSPICNT config = ds->memory.io7[DS_REG_AUXSPICNT >> 1];
180 if (DSSlot1AUXSPICNTIsSPIMode(config)) {
181 mLOG(DS_SLOT1, STUB, "Bad ROMCNT?");
182 return control;
183 }
184 if (DSSlot1ROMCNTIsBlockBusy(control)) {
185 DSSlot1StartTransfer(ds);
186 // TODO: timing
187 control = DSSlot1ROMCNTFillWordReady(control);
188 }
189 return control;
190}
191
192uint32_t DSSlot1Read(struct DS* ds) {
193 uint32_t result;
194 LOAD_32(result, 0, ds->memory.slot1.readBuffer);
195 if (ds->ds7.memory.slot1Access) {
196 _scheduleTransfer(ds, &ds->ds7.timing, 0);
197 } else {
198 _scheduleTransfer(ds, &ds->ds9.timing, 0);
199 }
200 return result;
201}
202
203void DSSlot1WriteSPI(struct DSCommon* dscore, uint8_t datum) {
204 UNUSED(datum);
205 DSSlot1AUXSPICNT control = dscore->memory.io[DS_REG_AUXSPICNT >> 1];
206 if (!DSSlot1AUXSPICNTIsSPIMode(control) || !DSSlot1AUXSPICNTIsEnable(control)) {
207 return;
208 }
209 uint32_t baud = 19 - DSSlot1AUXSPICNTGetBaud(control);
210 baud = DS_ARM7TDMI_FREQUENCY >> baud; // TODO: Right frequency for ARM9
211 control = DSSlot1AUXSPICNTFillBusy(control);
212 mTimingDeschedule(&dscore->timing, &dscore->p->memory.slot1.spiEvent);
213 mTimingSchedule(&dscore->timing, &dscore->p->memory.slot1.spiEvent, baud);
214 dscore->p->memory.slot1.spiEvent.context = dscore;
215 dscore->memory.io[DS_REG_AUXSPICNT >> 1] = control;
216 dscore->ipc->memory.io[DS_REG_AUXSPICNT >> 1] = control;
217}
218
219static uint8_t _slot1SPIAutodetect(struct DSCommon* dscore, uint8_t datum) {
220 DSSlot1AUXSPICNT control = dscore->memory.io[DS_REG_AUXSPICNT >> 1];
221 mLOG(DS_SLOT1, STUB, "Unimplemented SPI write: %04X:%02X:%02X", control, dscore->p->memory.slot1.spiCommand, datum);
222
223 if (dscore->p->memory.slot1.spiAddressingRemaining) {
224 dscore->p->memory.slot1.spiAddress <<= 8;
225 dscore->p->memory.slot1.spiAddress |= datum;
226 dscore->p->memory.slot1.spiAddressingRemaining -= 8;
227 if (dscore->p->memory.slot1.spiAddressingPc >= 0) {
228 dscore->p->memory.slot1.spiAddressingPc = dscore->cpu->gprs[ARM_PC];
229 }
230 return 0xFF;
231 } else if (dscore->cpu->gprs[ARM_PC] == dscore->p->memory.slot1.spiAddressingPc) {
232 dscore->p->memory.slot1.spiAddress <<= 8;
233 dscore->p->memory.slot1.spiAddress |= datum;
234 dscore->p->memory.slot1.savedataType = DS_SAVEDATA_FLASH;
235 return 0xFF;
236 } else {
237 if (dscore->p->memory.slot1.spiAddress) {
238 // Cease autodetection
239 dscore->p->memory.slot1.spiAddressingPc = -1;
240 }
241 if (!_slot1GuaranteeSize(&dscore->p->memory.slot1)) {
242 return 0xFF;
243 }
244 }
245
246 switch (dscore->p->memory.slot1.spiCommand) {
247 case 0x03: // RD
248 return dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress++];
249 case 0x02: // WR
250 dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress] = datum;
251 ++dscore->p->memory.slot1.spiAddress;
252 break;
253 }
254 return 0xFF;
255}
256
257static uint8_t _slot1SPIFlash(struct DSCommon* dscore, uint8_t datum) {
258 DSSlot1AUXSPICNT control = dscore->memory.io[DS_REG_AUXSPICNT >> 1];
259
260 if (dscore->p->memory.slot1.spiAddressingRemaining) {
261 dscore->p->memory.slot1.spiAddress <<= 8;
262 dscore->p->memory.slot1.spiAddress |= datum;
263 dscore->p->memory.slot1.spiAddressingRemaining -= 8;
264 return 0xFF;
265 } else {
266 if (!_slot1GuaranteeSize(&dscore->p->memory.slot1)) {
267 return 0xFF;
268 }
269 }
270
271 uint8_t oldValue;
272 switch (dscore->p->memory.slot1.spiCommand) {
273 case 0x03: // RD
274 oldValue = dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress];
275 ++dscore->p->memory.slot1.spiAddress;
276 return oldValue;
277 case 0x02: // PP
278 dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress] = datum;
279 ++dscore->p->memory.slot1.spiAddress;
280 break;
281 case 0x0A: // PW
282 oldValue = dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress];
283 dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress] = datum;
284 ++dscore->p->memory.slot1.spiAddress;
285 return oldValue;
286 default:
287 mLOG(DS_SLOT1, STUB, "Unimplemented SPI Flash write: %04X:%02X:%02X", control, dscore->p->memory.slot1.spiCommand, datum);
288 break;
289 }
290 return 0xFF;
291}
292
293static void _slot1SPI(struct mTiming* timing, void* context, uint32_t cyclesLate) {
294 UNUSED(timing);
295 UNUSED(cyclesLate);
296 struct DSCommon* dscore = context;
297 DSSlot1AUXSPICNT control = dscore->memory.io[DS_REG_AUXSPICNT >> 1];
298 uint8_t oldValue = dscore->memory.io[DS_REG_AUXSPIDATA >> 1];
299 uint8_t newValue = 0xFF;
300
301 if (!dscore->p->memory.slot1.spiCommand) {
302 dscore->p->memory.slot1.spiCommand = oldValue;
303 // Probably RDHI
304 if (oldValue == 0x0B && dscore->p->memory.slot1.savedataType == DS_SAVEDATA_AUTODETECT) {
305 dscore->p->memory.slot1.savedataType = DS_SAVEDATA_EEPROM512;
306 }
307 dscore->p->memory.slot1.spiAddress = 0;
308 switch (dscore->p->memory.slot1.savedataType) {
309 case DS_SAVEDATA_FLASH:
310 dscore->p->memory.slot1.spiAddressingRemaining = 24;
311 break;
312 default:
313 dscore->p->memory.slot1.spiAddressingRemaining = 16;
314 break;
315 }
316 } else {
317 switch (dscore->p->memory.slot1.spiCommand) {
318 case 0x04: // WRDI
319 dscore->p->memory.slot1.statusReg &= ~2;
320 break;
321 case 0x05: // RDSR
322 newValue = dscore->p->memory.slot1.statusReg;
323 break;
324 case 0x06: // WREN
325 dscore->p->memory.slot1.statusReg |= 2;
326 break;
327 default:
328 switch (dscore->p->memory.slot1.savedataType) {
329 case DS_SAVEDATA_AUTODETECT:
330 newValue = _slot1SPIAutodetect(dscore, oldValue);
331 break;
332 case DS_SAVEDATA_FLASH:
333 newValue = _slot1SPIFlash(dscore, oldValue);
334 break;
335 default:
336 mLOG(DS_SLOT1, STUB, "Unimplemented SPI write: %04X:%02X", control, oldValue);
337 break;
338 }
339 }
340 }
341
342 control = DSSlot1AUXSPICNTClearBusy(control);
343 dscore->memory.io[DS_REG_AUXSPIDATA >> 1] = newValue;
344 dscore->ipc->memory.io[DS_REG_AUXSPIDATA >> 1] = newValue;
345 dscore->memory.io[DS_REG_AUXSPICNT >> 1] = control;
346 dscore->ipc->memory.io[DS_REG_AUXSPICNT >> 1] = control;
347}
348
349static bool _slot1GuaranteeSize(struct DSSlot1* slot1) {
350 if (!slot1->spiVf) {
351 return false;
352 }
353 if (slot1->spiAddress >= slot1->spiVf->size(slot1->spiVf)) {
354 size_t size = toPow2(slot1->spiAddress + 1);
355 size_t oldSize = slot1->spiVf->size(slot1->spiVf);
356 if (slot1->spiData) {
357 slot1->spiVf->unmap(slot1->spiVf, slot1->spiData, oldSize);
358 slot1->spiData = NULL;
359 }
360 slot1->spiVf->truncate(slot1->spiVf, size);
361 slot1->spiVf->seek(slot1->spiVf, oldSize, SEEK_SET);
362 while (oldSize < size) {
363 static char buffer[1024];
364 memset(buffer, 0xFF, sizeof(buffer));
365 ssize_t written;
366 if (oldSize + sizeof(buffer) <= size) {
367 written = slot1->spiVf->write(slot1->spiVf, buffer, sizeof(buffer));
368 } else {
369 written = slot1->spiVf->write(slot1->spiVf, buffer, size - oldSize);
370 }
371 if (written >= 0) {
372 oldSize += written;
373 } else {
374 break;
375 }
376 }
377 }
378 if (!slot1->spiData) {
379 slot1->spiData = slot1->spiVf->map(slot1->spiVf, slot1->spiVf->size(slot1->spiVf), MAP_WRITE);
380 }
381 return slot1->spiData;
382}
383
384void DSSlot1ScheduleDMA(struct DSCommon* dscore, int number, struct GBADMA* info) {
385 UNUSED(info);
386 dscore->p->memory.slot1.dmaSource = number;
387}