src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/io.h>
7
8#include <mgba/internal/gb/gb.h>
9#include <mgba/internal/gb/sio.h>
10#include <mgba/internal/gb/serialize.h>
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
13
14const char* const GBIORegisterNames[] = {
15 [REG_JOYP] = "JOYP",
16 [REG_SB] = "SB",
17 [REG_SC] = "SC",
18 [REG_DIV] = "DIV",
19 [REG_TIMA] = "TIMA",
20 [REG_TMA] = "TMA",
21 [REG_TAC] = "TAC",
22 [REG_IF] = "IF",
23 [REG_NR10] = "NR10",
24 [REG_NR11] = "NR11",
25 [REG_NR12] = "NR12",
26 [REG_NR13] = "NR13",
27 [REG_NR14] = "NR14",
28 [REG_NR21] = "NR21",
29 [REG_NR22] = "NR22",
30 [REG_NR23] = "NR23",
31 [REG_NR24] = "NR24",
32 [REG_NR30] = "NR30",
33 [REG_NR31] = "NR31",
34 [REG_NR32] = "NR32",
35 [REG_NR33] = "NR33",
36 [REG_NR34] = "NR34",
37 [REG_NR41] = "NR41",
38 [REG_NR42] = "NR42",
39 [REG_NR43] = "NR43",
40 [REG_NR44] = "NR44",
41 [REG_NR50] = "NR50",
42 [REG_NR51] = "NR51",
43 [REG_NR52] = "NR52",
44 [REG_LCDC] = "LCDC",
45 [REG_STAT] = "STAT",
46 [REG_SCY] = "SCY",
47 [REG_SCX] = "SCX",
48 [REG_LY] = "LY",
49 [REG_LYC] = "LYC",
50 [REG_DMA] = "DMA",
51 [REG_BGP] = "BGP",
52 [REG_OBP0] = "OBP0",
53 [REG_OBP1] = "OBP1",
54 [REG_WY] = "WY",
55 [REG_WX] = "WX",
56 [REG_KEY1] = "KEY1",
57 [REG_VBK] = "VBK",
58 [REG_HDMA1] = "HDMA1",
59 [REG_HDMA2] = "HDMA2",
60 [REG_HDMA3] = "HDMA3",
61 [REG_HDMA4] = "HDMA4",
62 [REG_HDMA5] = "HDMA5",
63 [REG_RP] = "RP",
64 [REG_BCPS] = "BCPS",
65 [REG_BCPD] = "BCPD",
66 [REG_OCPS] = "OCPS",
67 [REG_OCPD] = "OCPD",
68 [REG_SVBK] = "SVBK",
69 [REG_IE] = "IE",
70};
71
72static const uint8_t _registerMask[] = {
73 [REG_SC] = 0x7E, // TODO: GBC differences
74 [REG_IF] = 0xE0,
75 [REG_TAC] = 0xF8,
76 [REG_NR10] = 0x80,
77 [REG_NR11] = 0x3F,
78 [REG_NR12] = 0x00,
79 [REG_NR13] = 0xFF,
80 [REG_NR14] = 0xBF,
81 [REG_NR21] = 0x3F,
82 [REG_NR22] = 0x00,
83 [REG_NR23] = 0xFF,
84 [REG_NR24] = 0xBF,
85 [REG_NR30] = 0x7F,
86 [REG_NR31] = 0xFF,
87 [REG_NR32] = 0x9F,
88 [REG_NR33] = 0xFF,
89 [REG_NR34] = 0xBF,
90 [REG_NR41] = 0xFF,
91 [REG_NR42] = 0x00,
92 [REG_NR43] = 0x00,
93 [REG_NR44] = 0xBF,
94 [REG_NR50] = 0x00,
95 [REG_NR51] = 0x00,
96 [REG_NR52] = 0x70,
97 [REG_STAT] = 0x80,
98 [REG_KEY1] = 0x7E,
99 [REG_VBK] = 0xFE,
100 [REG_OCPS] = 0x40,
101 [REG_BCPS] = 0x40,
102 [REG_UNK6C] = 0xFE,
103 [REG_SVBK] = 0xF8,
104 [REG_UNK75] = 0x8F,
105 [REG_IE] = 0xE0,
106};
107
108void GBIOInit(struct GB* gb) {
109 memset(gb->memory.io, 0, sizeof(gb->memory.io));
110}
111
112void GBIOReset(struct GB* gb) {
113 memset(gb->memory.io, 0, sizeof(gb->memory.io));
114
115 GBIOWrite(gb, REG_TIMA, 0);
116 GBIOWrite(gb, REG_TMA, 0);
117 GBIOWrite(gb, REG_TAC, 0);
118 GBIOWrite(gb, REG_IF, 1);
119 GBIOWrite(gb, REG_NR52, 0xF1);
120 GBIOWrite(gb, REG_NR14, 0xBF);
121 GBIOWrite(gb, REG_NR10, 0x80);
122 GBIOWrite(gb, REG_NR11, 0xBF);
123 GBIOWrite(gb, REG_NR12, 0xF3);
124 GBIOWrite(gb, REG_NR13, 0xF3);
125 GBIOWrite(gb, REG_NR24, 0xBF);
126 GBIOWrite(gb, REG_NR21, 0x3F);
127 GBIOWrite(gb, REG_NR22, 0x00);
128 GBIOWrite(gb, REG_NR34, 0xBF);
129 GBIOWrite(gb, REG_NR30, 0x7F);
130 GBIOWrite(gb, REG_NR31, 0xFF);
131 GBIOWrite(gb, REG_NR32, 0x9F);
132 GBIOWrite(gb, REG_NR44, 0xBF);
133 GBIOWrite(gb, REG_NR41, 0xFF);
134 GBIOWrite(gb, REG_NR42, 0x00);
135 GBIOWrite(gb, REG_NR43, 0x00);
136 GBIOWrite(gb, REG_NR50, 0x77);
137 GBIOWrite(gb, REG_NR51, 0xF3);
138 GBIOWrite(gb, REG_LCDC, 0x91);
139 GBIOWrite(gb, REG_SCY, 0x00);
140 GBIOWrite(gb, REG_SCX, 0x00);
141 GBIOWrite(gb, REG_LYC, 0x00);
142 GBIOWrite(gb, REG_BGP, 0xFC);
143 GBIOWrite(gb, REG_OBP0, 0xFF);
144 GBIOWrite(gb, REG_OBP1, 0xFF);
145 GBIOWrite(gb, REG_WY, 0x00);
146 GBIOWrite(gb, REG_WX, 0x00);
147 GBIOWrite(gb, REG_VBK, 0);
148 GBIOWrite(gb, REG_BCPS, 0);
149 GBIOWrite(gb, REG_OCPS, 0);
150 GBIOWrite(gb, REG_SVBK, 1);
151 GBIOWrite(gb, REG_HDMA1, 0xFF);
152 GBIOWrite(gb, REG_HDMA2, 0xFF);
153 GBIOWrite(gb, REG_HDMA3, 0xFF);
154 GBIOWrite(gb, REG_HDMA4, 0xFF);
155 gb->memory.io[REG_HDMA5] = 0xFF;
156 GBIOWrite(gb, REG_IE, 0x00);
157}
158
159void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
160 switch (address) {
161 case REG_SB:
162 GBSIOWriteSB(&gb->sio, value);
163 break;
164 case REG_SC:
165 GBSIOWriteSC(&gb->sio, value);
166 break;
167 case REG_DIV:
168 GBTimerDivReset(&gb->timer);
169 return;
170 case REG_NR10:
171 if (gb->audio.enable) {
172 GBAudioWriteNR10(&gb->audio, value);
173 } else {
174 value = 0;
175 }
176 break;
177 case REG_NR11:
178 if (gb->audio.enable) {
179 GBAudioWriteNR11(&gb->audio, value);
180 } else {
181 if (gb->audio.style == GB_AUDIO_DMG) {
182 GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
183 }
184 value = 0;
185 }
186 break;
187 case REG_NR12:
188 if (gb->audio.enable) {
189 GBAudioWriteNR12(&gb->audio, value);
190 } else {
191 value = 0;
192 }
193 break;
194 case REG_NR13:
195 if (gb->audio.enable) {
196 GBAudioWriteNR13(&gb->audio, value);
197 } else {
198 value = 0;
199 }
200 break;
201 case REG_NR14:
202 if (gb->audio.enable) {
203 GBAudioWriteNR14(&gb->audio, value);
204 } else {
205 value = 0;
206 }
207 break;
208 case REG_NR21:
209 if (gb->audio.enable) {
210 GBAudioWriteNR21(&gb->audio, value);
211 } else {
212 if (gb->audio.style == GB_AUDIO_DMG) {
213 GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
214 }
215 value = 0;
216 }
217 break;
218 case REG_NR22:
219 if (gb->audio.enable) {
220 GBAudioWriteNR22(&gb->audio, value);
221 } else {
222 value = 0;
223 }
224 break;
225 case REG_NR23:
226 if (gb->audio.enable) {
227 GBAudioWriteNR23(&gb->audio, value);
228 } else {
229 value = 0;
230 }
231 break;
232 case REG_NR24:
233 if (gb->audio.enable) {
234 GBAudioWriteNR24(&gb->audio, value);
235 } else {
236 value = 0;
237 }
238 break;
239 case REG_NR30:
240 if (gb->audio.enable) {
241 GBAudioWriteNR30(&gb->audio, value);
242 } else {
243 value = 0;
244 }
245 break;
246 case REG_NR31:
247 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
248 GBAudioWriteNR31(&gb->audio, value);
249 } else {
250 value = 0;
251 }
252 break;
253 case REG_NR32:
254 if (gb->audio.enable) {
255 GBAudioWriteNR32(&gb->audio, value);
256 } else {
257 value = 0;
258 }
259 break;
260 case REG_NR33:
261 if (gb->audio.enable) {
262 GBAudioWriteNR33(&gb->audio, value);
263 } else {
264 value = 0;
265 }
266 break;
267 case REG_NR34:
268 if (gb->audio.enable) {
269 GBAudioWriteNR34(&gb->audio, value);
270 } else {
271 value = 0;
272 }
273 break;
274 case REG_NR41:
275 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
276 GBAudioWriteNR41(&gb->audio, value);
277 } else {
278 value = 0;
279 }
280 break;
281 case REG_NR42:
282 if (gb->audio.enable) {
283 GBAudioWriteNR42(&gb->audio, value);
284 } else {
285 value = 0;
286 }
287 break;
288 case REG_NR43:
289 if (gb->audio.enable) {
290 GBAudioWriteNR43(&gb->audio, value);
291 } else {
292 value = 0;
293 }
294 break;
295 case REG_NR44:
296 if (gb->audio.enable) {
297 GBAudioWriteNR44(&gb->audio, value);
298 } else {
299 value = 0;
300 }
301 break;
302 case REG_NR50:
303 if (gb->audio.enable) {
304 GBAudioWriteNR50(&gb->audio, value);
305 } else {
306 value = 0;
307 }
308 break;
309 case REG_NR51:
310 if (gb->audio.enable) {
311 GBAudioWriteNR51(&gb->audio, value);
312 } else {
313 value = 0;
314 }
315 break;
316 case REG_NR52:
317 GBAudioWriteNR52(&gb->audio, value);
318 value &= 0x80;
319 value |= gb->memory.io[REG_NR52] & 0x0F;
320 break;
321 case REG_WAVE_0:
322 case REG_WAVE_1:
323 case REG_WAVE_2:
324 case REG_WAVE_3:
325 case REG_WAVE_4:
326 case REG_WAVE_5:
327 case REG_WAVE_6:
328 case REG_WAVE_7:
329 case REG_WAVE_8:
330 case REG_WAVE_9:
331 case REG_WAVE_A:
332 case REG_WAVE_B:
333 case REG_WAVE_C:
334 case REG_WAVE_D:
335 case REG_WAVE_E:
336 case REG_WAVE_F:
337 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
338 gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
339 } else if(gb->audio.ch3.readable) {
340 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
341 }
342 break;
343 case REG_JOYP:
344 case REG_TIMA:
345 case REG_TMA:
346 // Handled transparently by the registers
347 break;
348 case REG_TAC:
349 value = GBTimerUpdateTAC(&gb->timer, value);
350 break;
351 case REG_IF:
352 gb->memory.io[REG_IF] = value | 0xE0;
353 GBUpdateIRQs(gb);
354 return;
355 case REG_LCDC:
356 // TODO: handle GBC differences
357 GBVideoProcessDots(&gb->video);
358 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
359 GBVideoWriteLCDC(&gb->video, value);
360 break;
361 case REG_LYC:
362 GBVideoWriteLYC(&gb->video, value);
363 break;
364 case REG_DMA:
365 GBMemoryDMA(gb, value << 8);
366 break;
367 case REG_SCY:
368 case REG_SCX:
369 case REG_WY:
370 case REG_WX:
371 GBVideoProcessDots(&gb->video);
372 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
373 break;
374 case REG_BGP:
375 case REG_OBP0:
376 case REG_OBP1:
377 GBVideoProcessDots(&gb->video);
378 GBVideoWritePalette(&gb->video, address, value);
379 break;
380 case REG_STAT:
381 GBVideoWriteSTAT(&gb->video, value);
382 value = gb->video.stat;
383 break;
384 case 0x50:
385 if (gb->memory.romBase < gb->memory.rom && gb->memory.romBase > &gb->memory.rom[gb->memory.romSize - 1]) {
386 free(gb->memory.romBase);
387 gb->memory.romBase = gb->memory.rom;
388 }
389 break;
390 case REG_IE:
391 gb->memory.ie = value;
392 GBUpdateIRQs(gb);
393 return;
394 default:
395 if (gb->model >= GB_MODEL_CGB) {
396 switch (address) {
397 case REG_KEY1:
398 value &= 0x1;
399 value |= gb->memory.io[address] & 0x80;
400 break;
401 case REG_VBK:
402 GBVideoSwitchBank(&gb->video, value);
403 break;
404 case REG_HDMA1:
405 case REG_HDMA2:
406 case REG_HDMA3:
407 case REG_HDMA4:
408 // Handled transparently by the registers
409 break;
410 case REG_HDMA5:
411 GBMemoryWriteHDMA5(gb, value);
412 value &= 0x7F;
413 break;
414 case REG_BCPS:
415 gb->video.bcpIndex = value & 0x3F;
416 gb->video.bcpIncrement = value & 0x80;
417 gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
418 break;
419 case REG_BCPD:
420 GBVideoProcessDots(&gb->video);
421 GBVideoWritePalette(&gb->video, address, value);
422 return;
423 case REG_OCPS:
424 gb->video.ocpIndex = value & 0x3F;
425 gb->video.ocpIncrement = value & 0x80;
426 gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
427 break;
428 case REG_OCPD:
429 GBVideoProcessDots(&gb->video);
430 GBVideoWritePalette(&gb->video, address, value);
431 return;
432 case REG_SVBK:
433 GBMemorySwitchWramBank(&gb->memory, value);
434 value = gb->memory.wramCurrentBank;
435 break;
436 default:
437 goto failed;
438 }
439 goto success;
440 }
441 failed:
442 mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
443 if (address >= GB_SIZE_IO) {
444 return;
445 }
446 break;
447 }
448 success:
449 gb->memory.io[address] = value;
450}
451
452static uint8_t _readKeys(struct GB* gb) {
453 uint8_t keys = *gb->keySource;
454 switch (gb->memory.io[REG_JOYP] & 0x30) {
455 case 0x30:
456 keys = 0;
457 break;
458 case 0x20:
459 keys >>= 4;
460 break;
461 case 0x10:
462 break;
463 case 0x00:
464 keys |= keys >> 4;
465 break;
466 }
467 return (0xC0 | (gb->memory.io[REG_JOYP] | 0xF)) ^ (keys & 0xF);
468}
469
470uint8_t GBIORead(struct GB* gb, unsigned address) {
471 switch (address) {
472 case REG_JOYP:
473 return _readKeys(gb);
474 case REG_IE:
475 return gb->memory.ie;
476 case REG_WAVE_0:
477 case REG_WAVE_1:
478 case REG_WAVE_2:
479 case REG_WAVE_3:
480 case REG_WAVE_4:
481 case REG_WAVE_5:
482 case REG_WAVE_6:
483 case REG_WAVE_7:
484 case REG_WAVE_8:
485 case REG_WAVE_9:
486 case REG_WAVE_A:
487 case REG_WAVE_B:
488 case REG_WAVE_C:
489 case REG_WAVE_D:
490 case REG_WAVE_E:
491 case REG_WAVE_F:
492 if (gb->audio.playingCh3) {
493 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
494 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
495 } else {
496 return 0xFF;
497 }
498 } else {
499 return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
500 }
501 break;
502 case REG_SB:
503 case REG_SC:
504 case REG_IF:
505 case REG_NR10:
506 case REG_NR11:
507 case REG_NR12:
508 case REG_NR14:
509 case REG_NR21:
510 case REG_NR22:
511 case REG_NR24:
512 case REG_NR30:
513 case REG_NR32:
514 case REG_NR34:
515 case REG_NR41:
516 case REG_NR42:
517 case REG_NR43:
518 case REG_NR44:
519 case REG_NR50:
520 case REG_NR51:
521 case REG_NR52:
522 case REG_DIV:
523 case REG_TIMA:
524 case REG_TMA:
525 case REG_TAC:
526 case REG_STAT:
527 case REG_LCDC:
528 case REG_SCY:
529 case REG_SCX:
530 case REG_LY:
531 case REG_LYC:
532 case REG_BGP:
533 case REG_OBP0:
534 case REG_OBP1:
535 case REG_WY:
536 case REG_WX:
537 // Handled transparently by the registers
538 break;
539 default:
540 if (gb->model >= GB_MODEL_CGB) {
541 switch (address) {
542 case REG_KEY1:
543 case REG_VBK:
544 case REG_HDMA1:
545 case REG_HDMA2:
546 case REG_HDMA3:
547 case REG_HDMA4:
548 case REG_HDMA5:
549 case REG_BCPS:
550 case REG_BCPD:
551 case REG_OCPS:
552 case REG_OCPD:
553 case REG_SVBK:
554 // Handled transparently by the registers
555 goto success;
556 default:
557 break;
558 }
559 }
560 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
561 return 0xFF;
562 }
563 success:
564 return gb->memory.io[address] | _registerMask[address];
565}
566
567struct GBSerializedState;
568void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
569 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
570 state->ie = gb->memory.ie;
571}
572
573void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
574 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
575 gb->memory.ie = state->ie;
576 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
577 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
578 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
579 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
580 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
581}