1#ifndef ISA_INLINES_H
 2#define ISA_INLINES_H
 3
 4#include "macros.h"
 5
 6#include "arm.h"
 7
 8#define ARM_COND_EQ (cpu->cpsr.z)
 9#define ARM_COND_NE (!cpu->cpsr.z)
10#define ARM_COND_CS (cpu->cpsr.c)
11#define ARM_COND_CC (!cpu->cpsr.c)
12#define ARM_COND_MI (cpu->cpsr.n)
13#define ARM_COND_PL (!cpu->cpsr.n)
14#define ARM_COND_VS (cpu->cpsr.v)
15#define ARM_COND_VC (!cpu->cpsr.v)
16#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
17#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
18#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
19#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
20#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
21#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
22#define ARM_COND_AL 1
23
24#define ARM_SIGN(I) ((I) >> 31)
25#define ARM_ROR(I, ROTATE) ((((uint32_t) (I)) >> ROTATE) | ((I) << (32 - ROTATE)))
26
27#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
28#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
29#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
30#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
31
32#define ARM_WAIT_MUL(R) \
33	if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
34		cpu->cycles += 1; \
35	} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
36		cpu->cycles += 2; \
37	} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
38		cpu->cycles += 3; \
39	} else { \
40		cpu->cycles += 4; \
41	}
42
43#define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
44#define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
45
46#define ARM_WRITE_PC \
47	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM); \
48	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]); \
49	LOAD_32(cpu->prefetch, cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
50	cpu->gprs[ARM_PC] += WORD_SIZE_ARM; \
51	currentCycles += 2 + cpu->memory.activeUncachedCycles32 + cpu->memory.activeSeqCycles32;
52
53#define THUMB_WRITE_PC \
54	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB); \
55	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]); \
56	LOAD_16(cpu->prefetch, cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
57	cpu->gprs[ARM_PC] += WORD_SIZE_THUMB; \
58	currentCycles += 2 + cpu->memory.activeUncachedCycles16 + cpu->memory.activeSeqCycles16;
59
60static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
61	return mode != MODE_SYSTEM && mode != MODE_USER;
62}
63
64static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
65	if (executionMode == cpu->executionMode) {
66		return;
67	}
68
69	cpu->executionMode = executionMode;
70	switch (executionMode) {
71	case MODE_ARM:
72		cpu->cpsr.t = 0;
73		break;
74	case MODE_THUMB:
75		cpu->cpsr.t = 1;
76	}
77	cpu->nextEvent = 0;
78}
79
80static inline void _ARMReadCPSR(struct ARMCore* cpu) {
81	_ARMSetMode(cpu, cpu->cpsr.t);
82	ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
83	cpu->irqh.readCPSR(cpu);
84}
85
86#endif