src/arm/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4#include "emitter-thumb.h"
5
6// Instruction definitions
7// Beware pre-processor insanity
8
9#define THUMB_ADDITION_S(M, N, D) \
10 cpu->cpsr.n = ARM_SIGN(D); \
11 cpu->cpsr.z = !(D); \
12 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
13 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
14
15#define THUMB_SUBTRACTION_S(M, N, D) \
16 cpu->cpsr.n = ARM_SIGN(D); \
17 cpu->cpsr.z = !(D); \
18 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
19 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
20
21#define THUMB_NEUTRAL_S(M, N, D) \
22 cpu->cpsr.n = ARM_SIGN(D); \
23 cpu->cpsr.z = !(D);
24
25#define THUMB_ADDITION(D, M, N) \
26 int n = N; \
27 int m = M; \
28 D = M + N; \
29 THUMB_ADDITION_S(m, n, D)
30
31#define THUMB_SUBTRACTION(D, M, N) \
32 int n = N; \
33 int m = M; \
34 D = M - N; \
35 THUMB_SUBTRACTION_S(m, n, D)
36
37#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activeSeqCycles16)
38
39#define THUMB_LOAD_POST_BODY ++currentCycles;
40
41#define THUMB_STORE_POST_BODY \
42 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
43
44#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
45 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
46 int currentCycles = THUMB_PREFETCH_CYCLES; \
47 BODY; \
48 cpu->cycles += currentCycles; \
49 }
50
51#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
52 DEFINE_INSTRUCTION_THUMB(NAME, \
53 int immediate = IMMEDIATE; \
54 int rd = opcode & 0x0007; \
55 int rm = (opcode >> 3) & 0x0007; \
56 BODY;)
57
58#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
59 COUNT_CALL_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
60
61DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
62 if (!immediate) {
63 cpu->gprs[rd] = cpu->gprs[rm];
64 } else {
65 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
66 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
67 }
68 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
69
70DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
71 if (!immediate) {
72 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
73 cpu->gprs[rd] = 0;
74 } else {
75 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
76 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
77 }
78 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
79
80DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
81 if (!immediate) {
82 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
83 if (cpu->cpsr.c) {
84 cpu->gprs[rd] = 0xFFFFFFFF;
85 } else {
86 cpu->gprs[rd] = 0;
87 }
88 } else {
89 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
90 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
91 }
92 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
93
94DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, ¤tCycles); THUMB_LOAD_POST_BODY;)
95DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.loadU8(cpu, cpu->gprs[rm] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
96DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.loadU16(cpu, cpu->gprs[rm] + immediate * 2, ¤tCycles); THUMB_LOAD_POST_BODY;)
97DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
98DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
99DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
100
101#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
102 DEFINE_INSTRUCTION_THUMB(NAME, \
103 int rm = RM; \
104 int rd = opcode & 0x0007; \
105 int rn = (opcode >> 3) & 0x0007; \
106 BODY;)
107
108#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
109 COUNT_CALL_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
110
111DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
112DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
113
114#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
115 DEFINE_INSTRUCTION_THUMB(NAME, \
116 int immediate = IMMEDIATE; \
117 int rd = opcode & 0x0007; \
118 int rn = (opcode >> 3) & 0x0007; \
119 BODY;)
120
121#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
122 COUNT_CALL_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
123
124DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
125DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
126
127#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
128 DEFINE_INSTRUCTION_THUMB(NAME, \
129 int rd = RD; \
130 int immediate = opcode & 0x00FF; \
131 BODY;)
132
133#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
134 COUNT_CALL_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
135
136DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
137DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
138DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
139DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
140
141#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
142 DEFINE_INSTRUCTION_THUMB(NAME, \
143 int rd = opcode & 0x0007; \
144 int rn = (opcode >> 3) & 0x0007; \
145 BODY;)
146
147DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
148DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
149DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
150 int rs = cpu->gprs[rn] & 0xFF;
151 if (rs) {
152 if (rs < 32) {
153 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
154 cpu->gprs[rd] <<= rs;
155 } else {
156 if (rs > 32) {
157 cpu->cpsr.c = 0;
158 } else {
159 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
160 }
161 cpu->gprs[rd] = 0;
162 }
163 }
164 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
165
166DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
167 int rs = cpu->gprs[rn] & 0xFF;
168 if (rs) {
169 if (rs < 32) {
170 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
171 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
172 } else {
173 if (rs > 32) {
174 cpu->cpsr.c = 0;
175 } else {
176 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
177 }
178 cpu->gprs[rd] = 0;
179 }
180 }
181 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
182
183DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
184 int rs = cpu->gprs[rn] & 0xFF;
185 if (rs) {
186 if (rs < 32) {
187 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
188 cpu->gprs[rd] >>= rs;
189 } else {
190 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
191 if (cpu->cpsr.c) {
192 cpu->gprs[rd] = 0xFFFFFFFF;
193 } else {
194 cpu->gprs[rd] = 0;
195 }
196 }
197 }
198 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
199
200DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
201 int n = cpu->gprs[rn];
202 int d = cpu->gprs[rd];
203 cpu->gprs[rd] = d + n + cpu->cpsr.c;
204 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
205
206DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
207 int n = cpu->gprs[rn] + !cpu->cpsr.c;
208 int d = cpu->gprs[rd];
209 cpu->gprs[rd] = d - n;
210 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
211DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
212 int rs = cpu->gprs[rn] & 0xFF;
213 if (rs) {
214 int r4 = rs & 0x1F;
215 if (r4 > 0) {
216 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
217 cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4);
218 } else {
219 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
220 }
221 }
222 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
223DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
224DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
225DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
226DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
227DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
228DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rn]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
229DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
230DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
231
232#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
233 DEFINE_INSTRUCTION_THUMB(NAME, \
234 int rd = (opcode & 0x0007) | H1; \
235 int rm = ((opcode >> 3) & 0x0007) | H2; \
236 BODY;)
237
238#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
239 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
240 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
241 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
242 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
243
244DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
245 cpu->gprs[rd] += cpu->gprs[rm];
246 if (rd == ARM_PC) {
247 THUMB_WRITE_PC;
248 })
249
250DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
251DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
252 cpu->gprs[rd] = cpu->gprs[rm];
253 if (rd == ARM_PC) {
254 THUMB_WRITE_PC;
255 })
256
257#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
258 DEFINE_INSTRUCTION_THUMB(NAME, \
259 int rd = RD; \
260 int immediate = (opcode & 0x00FF) << 2; \
261 BODY;)
262
263#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
264 COUNT_CALL_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
265
266DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
267DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
268DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
269
270DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
271DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
272
273#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
274 DEFINE_INSTRUCTION_THUMB(NAME, \
275 int rm = RM; \
276 int rd = opcode & 0x0007; \
277 int rn = (opcode >> 3) & 0x0007; \
278 BODY;)
279
280#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
281 COUNT_CALL_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
282
283DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
284DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.loadU8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
285DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.loadU16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
286DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
287DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
288DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
289DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
290DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
291
292#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
293 DEFINE_INSTRUCTION_THUMB(NAME, \
294 int rn = RN; \
295 UNUSED(rn); \
296 int rs = opcode & 0xFF; \
297 int32_t address = cpu->gprs[RN]; \
298 PRE_BODY; \
299 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
300 WRITEBACK;)
301
302#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, LS, DIRECTION, WRITEBACK) \
303 COUNT_CALL_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, LS, DIRECTION, , WRITEBACK)
304
305DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
306 load,
307 IA,
308 THUMB_LOAD_POST_BODY;
309 if (!((1 << rn) & rs)) {
310 cpu->gprs[rn] = address;
311 })
312
313DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
314 store,
315 IA,
316 THUMB_STORE_POST_BODY;
317 cpu->gprs[rn] = address;)
318
319#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
320 DEFINE_INSTRUCTION_THUMB(B ## COND, \
321 if (ARM_COND_ ## COND) { \
322 int8_t immediate = opcode; \
323 cpu->gprs[ARM_PC] += immediate << 1; \
324 THUMB_WRITE_PC; \
325 })
326
327DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
328DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
329DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
330DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
331DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
332DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
333DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
334DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
335DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
336DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
337DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
338DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
339DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
340DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
341
342DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
343DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
344
345DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
346 ARM_SP,
347 load,
348 IA,
349 ,
350 THUMB_LOAD_POST_BODY;
351 cpu->gprs[ARM_SP] = address)
352
353DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
354 ARM_SP,
355 load,
356 IA,
357 rs |= 1 << ARM_PC,
358 THUMB_LOAD_POST_BODY;
359 cpu->gprs[ARM_SP] = address;
360 THUMB_WRITE_PC;)
361
362DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
363 ARM_SP,
364 store,
365 DB,
366 ,
367 THUMB_STORE_POST_BODY;
368 cpu->gprs[ARM_SP] = address)
369
370DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
371 ARM_SP,
372 store,
373 DB,
374 rs |= 1 << ARM_LR,
375 THUMB_STORE_POST_BODY;
376 cpu->gprs[ARM_SP] = address)
377
378DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
379DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
380DEFINE_INSTRUCTION_THUMB(B,
381 int16_t immediate = (opcode & 0x07FF) << 5;
382 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
383 THUMB_WRITE_PC;)
384
385DEFINE_INSTRUCTION_THUMB(BL1,
386 int16_t immediate = (opcode & 0x07FF) << 5;
387 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
388
389DEFINE_INSTRUCTION_THUMB(BL2,
390 uint16_t immediate = (opcode & 0x07FF) << 1;
391 uint32_t pc = cpu->gprs[ARM_PC];
392 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
393 cpu->gprs[ARM_LR] = pc - 1;
394 THUMB_WRITE_PC;)
395
396DEFINE_INSTRUCTION_THUMB(BX,
397 int rm = (opcode >> 3) & 0xF;
398 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
399 int misalign = 0;
400 if (rm == ARM_PC) {
401 misalign = cpu->gprs[rm] & 0x00000002;
402 }
403 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
404 if (cpu->executionMode == MODE_THUMB) {
405 THUMB_WRITE_PC;
406 } else {
407 ARM_WRITE_PC;
408 })
409
410DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
411
412const ThumbInstruction _thumbTable[0x400] = {
413 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
414};