src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "core/interface.h"
9#include "gb/gb.h"
10#include "gb/io.h"
11
12#include "util/memory.h"
13
14#include <time.h>
15
16mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC");
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory");
18
19static void _GBMBCNone(struct GBMemory* memory, uint16_t address, uint8_t value) {
20 UNUSED(memory);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GBMemory*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GBMemory*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GBMemory*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GBMemory*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GBMemory*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GBMemory*, uint16_t address, uint8_t value);
33
34static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
35 // TODO
36}
37
38static void _GBMemoryDMAService(struct GB* gb);
39static void _GBMemoryHDMAService(struct GB* gb);
40
41void GBMemoryInit(struct GB* gb) {
42 struct LR35902Core* cpu = gb->cpu;
43 cpu->memory.cpuLoad8 = GBLoad8;
44 cpu->memory.load8 = GBLoad8;
45 cpu->memory.store8 = GBStore8;
46 cpu->memory.setActiveRegion = GBSetActiveRegion;
47
48 gb->memory.wram = 0;
49 gb->memory.wramBank = 0;
50 gb->memory.rom = 0;
51 gb->memory.romBank = 0;
52 gb->memory.romSize = 0;
53 gb->memory.sram = 0;
54 gb->memory.mbcType = GB_MBC_NONE;
55 gb->memory.mbc = 0;
56
57 gb->memory.dmaNext = INT_MAX;
58 gb->memory.dmaRemaining = 0;
59 gb->memory.hdmaNext = INT_MAX;
60 gb->memory.hdmaRemaining = 0;
61
62 memset(gb->memory.hram, 0, sizeof(gb->memory.hram));
63
64 gb->memory.sramAccess = false;
65 gb->memory.rtcAccess = false;
66 gb->memory.rtcLatched = 0;
67 gb->memory.rtc = NULL;
68
69 GBIOInit(gb);
70}
71
72void GBMemoryDeinit(struct GB* gb) {
73 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
74 if (gb->memory.rom) {
75 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
76 }
77}
78
79void GBMemoryReset(struct GB* gb) {
80 if (gb->memory.wram) {
81 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
82 }
83 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
84 GBMemorySwitchWramBank(&gb->memory, 1);
85 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
86 gb->memory.currentBank = 1;
87 gb->memory.sramCurrentBank = 0;
88 gb->memory.sramBank = gb->memory.sram;
89
90 memset(&gb->video.oam, 0, sizeof(gb->video.oam));
91
92 const struct GBCartridge* cart = &gb->memory.rom[0x100];
93 switch (cart->type) {
94 case 0:
95 case 8:
96 case 9:
97 gb->memory.mbc = _GBMBCNone;
98 gb->memory.mbcType = GB_MBC_NONE;
99 break;
100 case 1:
101 case 2:
102 case 3:
103 gb->memory.mbc = _GBMBC1;
104 gb->memory.mbcType = GB_MBC1;
105 break;
106 case 5:
107 case 6:
108 gb->memory.mbc = _GBMBC2;
109 gb->memory.mbcType = GB_MBC2;
110 break;
111 case 0x0F:
112 case 0x10:
113 case 0x11:
114 case 0x12:
115 case 0x13:
116 gb->memory.mbc = _GBMBC3;
117 gb->memory.mbcType = GB_MBC3;
118 break;
119 default:
120 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
121 case 0x19:
122 case 0x1A:
123 case 0x1B:
124 case 0x1C:
125 case 0x1D:
126 case 0x1E:
127 gb->memory.mbc = _GBMBC5;
128 gb->memory.mbcType = GB_MBC5;
129 break;
130 case 0x20:
131 gb->memory.mbc = _GBMBC6;
132 gb->memory.mbcType = GB_MBC6;
133 break;
134 case 0x22:
135 gb->memory.mbc = _GBMBC7;
136 gb->memory.mbcType = GB_MBC7;
137 break;
138 }
139
140 if (!gb->memory.wram) {
141 GBMemoryDeinit(gb);
142 }
143}
144
145void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
146 bank &= 7;
147 if (!bank) {
148 bank = 1;
149 }
150 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
151 memory->wramCurrentBank = bank;
152}
153
154uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
155 struct GB* gb = (struct GB*) cpu->master;
156 struct GBMemory* memory = &gb->memory;
157 switch (address >> 12) {
158 case GB_REGION_CART_BANK0:
159 case GB_REGION_CART_BANK0 + 1:
160 case GB_REGION_CART_BANK0 + 2:
161 case GB_REGION_CART_BANK0 + 3:
162 return memory->rom[address & (GB_SIZE_CART_BANK0 - 1)];
163 case GB_REGION_CART_BANK1:
164 case GB_REGION_CART_BANK1 + 1:
165 case GB_REGION_CART_BANK1 + 2:
166 case GB_REGION_CART_BANK1 + 3:
167 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
168 case GB_REGION_VRAM:
169 case GB_REGION_VRAM + 1:
170 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
171 case GB_REGION_EXTERNAL_RAM:
172 case GB_REGION_EXTERNAL_RAM + 1:
173 if (memory->rtcAccess) {
174 return gb->memory.rtcRegs[memory->activeRtcReg];
175 } else if (memory->sramAccess) {
176 return gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
177 }
178 return 0xFF;
179 case GB_REGION_WORKING_RAM_BANK0:
180 case GB_REGION_WORKING_RAM_BANK0 + 2:
181 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
182 case GB_REGION_WORKING_RAM_BANK1:
183 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
184 default:
185 if (address < GB_BASE_OAM) {
186 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
187 }
188 if (address < GB_BASE_UNUSABLE) {
189 if (gb->video.mode < 2) {
190 return gb->video.oam.raw[address & 0xFF];
191 }
192 return 0xFF;
193 }
194 if (address < GB_BASE_IO) {
195 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
196 return 0xFF;
197 }
198 if (address < GB_BASE_HRAM) {
199 return GBIORead(gb, address & (GB_SIZE_IO - 1));
200 }
201 if (address < GB_BASE_IE) {
202 return memory->hram[address & GB_SIZE_HRAM];
203 }
204 return GBIORead(gb, REG_IE);
205 }
206}
207
208void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
209 struct GB* gb = (struct GB*) cpu->master;
210 struct GBMemory* memory = &gb->memory;
211 switch (address >> 12) {
212 case GB_REGION_CART_BANK0:
213 case GB_REGION_CART_BANK0 + 1:
214 case GB_REGION_CART_BANK0 + 2:
215 case GB_REGION_CART_BANK0 + 3:
216 case GB_REGION_CART_BANK1:
217 case GB_REGION_CART_BANK1 + 1:
218 case GB_REGION_CART_BANK1 + 2:
219 case GB_REGION_CART_BANK1 + 3:
220 memory->mbc(memory, address, value);
221 return;
222 case GB_REGION_VRAM:
223 case GB_REGION_VRAM + 1:
224 // TODO: Block access in wrong modes
225 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
226 return;
227 case GB_REGION_EXTERNAL_RAM:
228 case GB_REGION_EXTERNAL_RAM + 1:
229 if (memory->rtcAccess) {
230 gb->memory.rtcRegs[memory->activeRtcReg] = value;
231 } else if (memory->sramAccess) {
232 gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
233 }
234 return;
235 case GB_REGION_WORKING_RAM_BANK0:
236 case GB_REGION_WORKING_RAM_BANK0 + 2:
237 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
238 return;
239 case GB_REGION_WORKING_RAM_BANK1:
240 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
241 return;
242 default:
243 if (address < GB_BASE_OAM) {
244 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
245 } else if (address < GB_BASE_UNUSABLE) {
246 if (gb->video.mode < 2) {
247 gb->video.oam.raw[address & 0xFF] = value;
248 }
249 } else if (address < GB_BASE_IO) {
250 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
251 } else if (address < GB_BASE_HRAM) {
252 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
253 } else if (address < GB_BASE_IE) {
254 memory->hram[address & GB_SIZE_HRAM] = value;
255 } else {
256 GBIOWrite(gb, REG_IE, value);
257 }
258 }
259}
260
261int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles) {
262 int nextEvent = INT_MAX;
263 if (gb->memory.dmaRemaining) {
264 gb->memory.dmaNext -= cycles;
265 if (gb->memory.dmaNext <= 0) {
266 _GBMemoryDMAService(gb);
267 }
268 nextEvent = gb->memory.dmaNext;
269 }
270 if (gb->memory.hdmaRemaining) {
271 gb->memory.hdmaNext -= cycles;
272 if (gb->memory.hdmaNext <= 0) {
273 _GBMemoryHDMAService(gb);
274 }
275 if (gb->memory.hdmaNext < nextEvent) {
276 nextEvent = gb->memory.hdmaNext;
277 }
278 }
279 return nextEvent;
280}
281
282void GBMemoryDMA(struct GB* gb, uint16_t base) {
283 if (base > 0xF100) {
284 return;
285 }
286 gb->cpu->memory.store8 = GBDMAStore8;
287 gb->cpu->memory.load8 = GBDMALoad8;
288 gb->memory.dmaNext = gb->cpu->cycles + 8;
289 if (gb->memory.dmaNext < gb->cpu->nextEvent) {
290 gb->cpu->nextEvent = gb->memory.dmaNext;
291 }
292 gb->memory.dmaSource = base;
293 gb->memory.dmaDest = 0;
294 gb->memory.dmaRemaining = 0xA0;
295}
296
297void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
298 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
299 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
300 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
301 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
302 gb->memory.hdmaSource &= 0xFFF0;
303 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
304 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
305 return;
306 }
307 gb->memory.hdmaDest &= 0x1FF0;
308 gb->memory.hdmaDest |= 0x8000;
309 gb->memory.isHdma = value & 0x80;
310 if (!gb->memory.isHdma) {
311 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
312 gb->memory.hdmaNext = gb->cpu->cycles;
313 gb->cpu->nextEvent = gb->cpu->cycles;
314 }
315}
316
317void _GBMemoryDMAService(struct GB* gb) {
318 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
319 // TODO: Can DMA write OAM during modes 2-3?
320 gb->video.oam.raw[gb->memory.dmaDest] = b;
321 ++gb->memory.dmaSource;
322 ++gb->memory.dmaDest;
323 --gb->memory.dmaRemaining;
324 if (gb->memory.dmaRemaining) {
325 gb->memory.dmaNext += 4;
326 } else {
327 gb->memory.dmaNext = INT_MAX;
328 gb->cpu->memory.store8 = GBStore8;
329 gb->cpu->memory.load8 = GBLoad8;
330 }
331}
332
333void _GBMemoryHDMAService(struct GB* gb) {
334 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
335 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
336 ++gb->memory.hdmaSource;
337 ++gb->memory.hdmaDest;
338 --gb->memory.hdmaRemaining;
339 gb->cpu->cycles += 2;
340 if (gb->memory.hdmaRemaining) {
341 gb->memory.hdmaNext += 2;
342 } else {
343 gb->memory.io[REG_HDMA5] |= 0x80;
344 }
345}
346
347uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address) {
348 struct GB* gb = (struct GB*) cpu->master;
349 struct GBMemory* memory = &gb->memory;
350 if (address < 0xFF80 || address == 0xFFFF) {
351 return 0xFF;
352 }
353 return memory->hram[address & GB_SIZE_HRAM];
354}
355
356void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
357 struct GB* gb = (struct GB*) cpu->master;
358 struct GBMemory* memory = &gb->memory;
359 if (address < 0xFF80 || address == 0xFFFF) {
360 return;
361 }
362 memory->hram[address & GB_SIZE_HRAM] = value;
363}
364
365uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
366
367void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
368
369static void _switchBank(struct GBMemory* memory, int bank) {
370 size_t bankStart = bank * GB_SIZE_CART_BANK0;
371 if (bankStart + GB_SIZE_CART_BANK0 > memory->romSize) {
372 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
373 bankStart &= (GB_SIZE_CART_BANK0 - 1);
374 bank /= GB_SIZE_CART_BANK0;
375 }
376 memory->romBank = &memory->rom[bankStart];
377 memory->currentBank = bank;
378}
379
380static void _switchSramBank(struct GBMemory* memory, int bank) {
381 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
382 memory->sramBank = &memory->sram[bankStart];
383 memory->sramCurrentBank = bank;
384}
385
386static void _latchRtc(struct GBMemory* memory) {
387 time_t t;
388 struct mRTCSource* rtc = memory->rtc;
389 if (rtc) {
390 if (rtc->sample) {
391 rtc->sample(rtc);
392 }
393 t = rtc->unixTime(rtc);
394 } else {
395 t = time(0);
396 }
397 struct tm date;
398 localtime_r(&t, &date);
399 memory->rtcRegs[0] = date.tm_sec;
400 memory->rtcRegs[1] = date.tm_min;
401 memory->rtcRegs[2] = date.tm_hour;
402 memory->rtcRegs[3] = date.tm_yday; // TODO: Persist day counter
403 memory->rtcRegs[4] &= 0xF0;
404 memory->rtcRegs[4] |= date.tm_yday >> 8;
405}
406
407void _GBMBC1(struct GBMemory* memory, uint16_t address, uint8_t value) {
408 int bank = value & 0x1F;
409 switch (address >> 13) {
410 case 0x0:
411 switch (value) {
412 case 0:
413 memory->sramAccess = false;
414 break;
415 case 0xA:
416 memory->sramAccess = true;
417 _switchSramBank(memory, memory->sramCurrentBank);
418 break;
419 default:
420 // TODO
421 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
422 break;
423 }
424 break;
425 case 0x1:
426 if (!bank) {
427 ++bank;
428 }
429 _switchBank(memory, bank | (memory->currentBank & 0x60));
430 break;
431 default:
432 // TODO
433 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
434 break;
435 }
436}
437
438void _GBMBC2(struct GBMemory* memory, uint16_t address, uint8_t value) {
439 mLOG(GB_MBC, STUB, "MBC2 unimplemented");
440}
441
442void _GBMBC3(struct GBMemory* memory, uint16_t address, uint8_t value) {
443 int bank = value & 0x7F;
444 switch (address >> 13) {
445 case 0x0:
446 switch (value) {
447 case 0:
448 memory->sramAccess = false;
449 break;
450 case 0xA:
451 memory->sramAccess = true;
452 _switchSramBank(memory, memory->sramCurrentBank);
453 break;
454 default:
455 // TODO
456 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
457 break;
458 }
459 break;
460 case 0x1:
461 if (!bank) {
462 ++bank;
463 }
464 _switchBank(memory, bank);
465 break;
466 case 0x2:
467 if (value < 4) {
468 _switchSramBank(memory, value);
469 memory->rtcAccess = false;
470 } else if (value >= 8 && value <= 0xC) {
471 memory->activeRtcReg = value - 8;
472 memory->rtcAccess = true;
473 }
474 break;
475 case 0x3:
476 if (memory->rtcLatched && value == 0) {
477 memory->rtcLatched = value;
478 } else if (!memory->rtcLatched && value == 1) {
479 _latchRtc(memory);
480 }
481 break;
482 }
483}
484
485void _GBMBC5(struct GBMemory* memory, uint16_t address, uint8_t value) {
486 int bank = value & 0x7F;
487 switch (address >> 13) {
488 case 0x0:
489 switch (value) {
490 case 0:
491 memory->sramAccess = false;
492 break;
493 case 0xA:
494 memory->sramAccess = true;
495 _switchSramBank(memory, memory->sramCurrentBank);
496 break;
497 default:
498 // TODO
499 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
500 break;
501 }
502 break;
503 case 0x1:
504 _switchBank(memory, bank);
505 break;
506 case 0x2:
507 if (value < 0x10) {
508 _switchSramBank(memory, value);
509 }
510 break;
511 default:
512 // TODO
513 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
514 break;
515 }
516}
517
518void _GBMBC6(struct GBMemory* memory, uint16_t address, uint8_t value) {
519 // TODO
520 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
521}
522
523void _GBMBC7(struct GBMemory* memory, uint16_t address, uint8_t value) {
524 // TODO
525 mLOG(GB_MBC, STUB, "MBC7 unimplemented");
526}