src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "core/interface.h"
9#include "gb/gb.h"
10#include "gb/io.h"
11
12#include "util/memory.h"
13
14#include <time.h>
15
16mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC");
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory");
18
19static void _GBMBCNone(struct GBMemory* memory, uint16_t address, uint8_t value) {
20 UNUSED(memory);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GBMemory*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GBMemory*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GBMemory*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GBMemory*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GBMemory*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GBMemory*, uint16_t address, uint8_t value);
33static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
34static void _GBMBC7Write(struct GBMemory*, uint16_t address, uint8_t value);
35
36static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
37 if (UNLIKELY(address > cpu->memory.activeRegionEnd)) {
38 cpu->memory.setActiveRegion(cpu, address);
39 return cpu->memory.cpuLoad8(cpu, address);
40 }
41 return cpu->memory.activeRegion[address & cpu->memory.activeMask];
42}
43
44static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
45 struct GB* gb = (struct GB*) cpu->master;
46 struct GBMemory* memory = &gb->memory;
47 switch (address >> 12) {
48 case GB_REGION_CART_BANK0:
49 case GB_REGION_CART_BANK0 + 1:
50 case GB_REGION_CART_BANK0 + 2:
51 case GB_REGION_CART_BANK0 + 3:
52 cpu->memory.cpuLoad8 = GBFastLoad8;
53 cpu->memory.activeRegion = memory->rom;
54 cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
55 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
56 break;
57 case GB_REGION_CART_BANK1:
58 case GB_REGION_CART_BANK1 + 1:
59 case GB_REGION_CART_BANK1 + 2:
60 case GB_REGION_CART_BANK1 + 3:
61 cpu->memory.cpuLoad8 = GBFastLoad8;
62 cpu->memory.activeRegion = memory->romBank;
63 cpu->memory.activeRegionEnd = GB_BASE_VRAM;
64 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
65 break;
66 default:
67 cpu->memory.cpuLoad8 = GBLoad8;
68 break;
69 }
70}
71
72static void _GBMemoryDMAService(struct GB* gb);
73static void _GBMemoryHDMAService(struct GB* gb);
74
75void GBMemoryInit(struct GB* gb) {
76 struct LR35902Core* cpu = gb->cpu;
77 cpu->memory.cpuLoad8 = GBLoad8;
78 cpu->memory.load8 = GBLoad8;
79 cpu->memory.store8 = GBStore8;
80 cpu->memory.setActiveRegion = GBSetActiveRegion;
81
82 gb->memory.wram = 0;
83 gb->memory.wramBank = 0;
84 gb->memory.rom = 0;
85 gb->memory.romBank = 0;
86 gb->memory.romSize = 0;
87 gb->memory.sram = 0;
88 gb->memory.mbcType = GB_MBC_NONE;
89 gb->memory.mbc = 0;
90
91 gb->memory.rtc = NULL;
92
93 GBIOInit(gb);
94}
95
96void GBMemoryDeinit(struct GB* gb) {
97 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
98 if (gb->memory.rom) {
99 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
100 }
101}
102
103void GBMemoryReset(struct GB* gb) {
104 if (gb->memory.wram) {
105 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
106 }
107 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
108 GBMemorySwitchWramBank(&gb->memory, 1);
109 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
110 gb->memory.currentBank = 1;
111 if (!gb->memory.sram) {
112 gb->memory.sram = anonymousMemoryMap(0x20000);
113 }
114 gb->memory.sramCurrentBank = 0;
115 gb->memory.sramBank = gb->memory.sram;
116
117 gb->memory.ime = false;
118 gb->memory.ie = 0;
119
120 gb->memory.dmaNext = INT_MAX;
121 gb->memory.dmaRemaining = 0;
122 gb->memory.dmaSource = 0;
123 gb->memory.dmaDest = 0;
124 gb->memory.hdmaNext = INT_MAX;
125 gb->memory.hdmaRemaining = 0;
126 gb->memory.hdmaSource = 0;
127 gb->memory.hdmaDest = 0;
128 gb->memory.isHdma = false;
129
130 gb->memory.sramAccess = false;
131 gb->memory.rtcAccess = false;
132 gb->memory.activeRtcReg = 0;
133 gb->memory.rtcLatched = 0;
134 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
135
136 memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
137 memset(&gb->memory.mbcState, 0, sizeof(gb->memory.mbcState));
138
139 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
140 switch (cart->type) {
141 case 0:
142 case 8:
143 case 9:
144 gb->memory.mbc = _GBMBCNone;
145 gb->memory.mbcType = GB_MBC_NONE;
146 break;
147 case 1:
148 case 2:
149 case 3:
150 gb->memory.mbc = _GBMBC1;
151 gb->memory.mbcType = GB_MBC1;
152 break;
153 case 5:
154 case 6:
155 gb->memory.mbc = _GBMBC2;
156 gb->memory.mbcType = GB_MBC2;
157 break;
158 case 0x0F:
159 case 0x10:
160 case 0x11:
161 case 0x12:
162 case 0x13:
163 gb->memory.mbc = _GBMBC3;
164 gb->memory.mbcType = GB_MBC3;
165 break;
166 default:
167 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
168 case 0x19:
169 case 0x1A:
170 case 0x1B:
171 gb->memory.mbc = _GBMBC5;
172 gb->memory.mbcType = GB_MBC5;
173 break;
174 case 0x1C:
175 case 0x1D:
176 case 0x1E:
177 gb->memory.mbc = _GBMBC5;
178 gb->memory.mbcType = GB_MBC5_RUMBLE;
179 break;
180 case 0x20:
181 gb->memory.mbc = _GBMBC6;
182 gb->memory.mbcType = GB_MBC6;
183 break;
184 case 0x22:
185 gb->memory.mbc = _GBMBC7;
186 gb->memory.mbcType = GB_MBC7;
187 break;
188 }
189
190 if (!gb->memory.wram) {
191 GBMemoryDeinit(gb);
192 }
193}
194
195void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
196 bank &= 7;
197 if (!bank) {
198 bank = 1;
199 }
200 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
201 memory->wramCurrentBank = bank;
202}
203
204uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
205 struct GB* gb = (struct GB*) cpu->master;
206 struct GBMemory* memory = &gb->memory;
207 switch (address >> 12) {
208 case GB_REGION_CART_BANK0:
209 case GB_REGION_CART_BANK0 + 1:
210 case GB_REGION_CART_BANK0 + 2:
211 case GB_REGION_CART_BANK0 + 3:
212 return memory->rom[address & (GB_SIZE_CART_BANK0 - 1)];
213 case GB_REGION_CART_BANK1:
214 case GB_REGION_CART_BANK1 + 1:
215 case GB_REGION_CART_BANK1 + 2:
216 case GB_REGION_CART_BANK1 + 3:
217 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
218 case GB_REGION_VRAM:
219 case GB_REGION_VRAM + 1:
220 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
221 case GB_REGION_EXTERNAL_RAM:
222 case GB_REGION_EXTERNAL_RAM + 1:
223 if (memory->rtcAccess) {
224 return gb->memory.rtcRegs[memory->activeRtcReg];
225 } else if (memory->sramAccess) {
226 return gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
227 } else if (memory->mbcType == GB_MBC7) {
228 return _GBMBC7Read(memory, address);
229 }
230 return 0xFF;
231 case GB_REGION_WORKING_RAM_BANK0:
232 case GB_REGION_WORKING_RAM_BANK0 + 2:
233 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
234 case GB_REGION_WORKING_RAM_BANK1:
235 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
236 default:
237 if (address < GB_BASE_OAM) {
238 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
239 }
240 if (address < GB_BASE_UNUSABLE) {
241 if (gb->video.mode < 2) {
242 return gb->video.oam.raw[address & 0xFF];
243 }
244 return 0xFF;
245 }
246 if (address < GB_BASE_IO) {
247 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
248 return 0xFF;
249 }
250 if (address < GB_BASE_HRAM) {
251 return GBIORead(gb, address & (GB_SIZE_IO - 1));
252 }
253 if (address < GB_BASE_IE) {
254 return memory->hram[address & GB_SIZE_HRAM];
255 }
256 return GBIORead(gb, REG_IE);
257 }
258}
259
260void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
261 struct GB* gb = (struct GB*) cpu->master;
262 struct GBMemory* memory = &gb->memory;
263 switch (address >> 12) {
264 case GB_REGION_CART_BANK0:
265 case GB_REGION_CART_BANK0 + 1:
266 case GB_REGION_CART_BANK0 + 2:
267 case GB_REGION_CART_BANK0 + 3:
268 case GB_REGION_CART_BANK1:
269 case GB_REGION_CART_BANK1 + 1:
270 case GB_REGION_CART_BANK1 + 2:
271 case GB_REGION_CART_BANK1 + 3:
272 memory->mbc(memory, address, value);
273 cpu->memory.setActiveRegion(cpu, cpu->pc);
274 return;
275 case GB_REGION_VRAM:
276 case GB_REGION_VRAM + 1:
277 // TODO: Block access in wrong modes
278 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
279 return;
280 case GB_REGION_EXTERNAL_RAM:
281 case GB_REGION_EXTERNAL_RAM + 1:
282 if (memory->rtcAccess) {
283 gb->memory.rtcRegs[memory->activeRtcReg] = value;
284 } else if (memory->sramAccess) {
285 gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
286 } else if (gb->memory.mbcType == GB_MBC7) {
287 _GBMBC7Write(&gb->memory, address, value);
288 }
289 return;
290 case GB_REGION_WORKING_RAM_BANK0:
291 case GB_REGION_WORKING_RAM_BANK0 + 2:
292 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
293 return;
294 case GB_REGION_WORKING_RAM_BANK1:
295 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
296 return;
297 default:
298 if (address < GB_BASE_OAM) {
299 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
300 } else if (address < GB_BASE_UNUSABLE) {
301 if (gb->video.mode < 2) {
302 gb->video.oam.raw[address & 0xFF] = value;
303 }
304 } else if (address < GB_BASE_IO) {
305 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
306 } else if (address < GB_BASE_HRAM) {
307 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
308 } else if (address < GB_BASE_IE) {
309 memory->hram[address & GB_SIZE_HRAM] = value;
310 } else {
311 GBIOWrite(gb, REG_IE, value);
312 }
313 }
314}
315
316int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles) {
317 int nextEvent = INT_MAX;
318 if (gb->memory.dmaRemaining) {
319 gb->memory.dmaNext -= cycles;
320 if (gb->memory.dmaNext <= 0) {
321 _GBMemoryDMAService(gb);
322 }
323 nextEvent = gb->memory.dmaNext;
324 }
325 if (gb->memory.hdmaRemaining) {
326 gb->memory.hdmaNext -= cycles;
327 if (gb->memory.hdmaNext <= 0) {
328 _GBMemoryHDMAService(gb);
329 }
330 if (gb->memory.hdmaNext < nextEvent) {
331 nextEvent = gb->memory.hdmaNext;
332 }
333 }
334 return nextEvent;
335}
336
337void GBMemoryDMA(struct GB* gb, uint16_t base) {
338 if (base > 0xF100) {
339 return;
340 }
341 gb->cpu->memory.store8 = GBDMAStore8;
342 gb->cpu->memory.load8 = GBDMALoad8;
343 gb->cpu->memory.cpuLoad8 = GBDMALoad8;
344 gb->memory.dmaNext = gb->cpu->cycles + 8;
345 if (gb->memory.dmaNext < gb->cpu->nextEvent) {
346 gb->cpu->nextEvent = gb->memory.dmaNext;
347 }
348 gb->memory.dmaSource = base;
349 gb->memory.dmaDest = 0;
350 gb->memory.dmaRemaining = 0xA0;
351}
352
353void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
354 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
355 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
356 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
357 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
358 gb->memory.hdmaSource &= 0xFFF0;
359 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
360 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
361 return;
362 }
363 gb->memory.hdmaDest &= 0x1FF0;
364 gb->memory.hdmaDest |= 0x8000;
365 bool wasHdma = gb->memory.isHdma;
366 gb->memory.isHdma = value & 0x80;
367 if (!wasHdma && !gb->memory.isHdma) {
368 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
369 gb->memory.hdmaNext = gb->cpu->cycles;
370 gb->cpu->nextEvent = gb->cpu->cycles;
371 }
372}
373
374void _GBMemoryDMAService(struct GB* gb) {
375 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
376 // TODO: Can DMA write OAM during modes 2-3?
377 gb->video.oam.raw[gb->memory.dmaDest] = b;
378 ++gb->memory.dmaSource;
379 ++gb->memory.dmaDest;
380 --gb->memory.dmaRemaining;
381 if (gb->memory.dmaRemaining) {
382 gb->memory.dmaNext += 4;
383 } else {
384 gb->memory.dmaNext = INT_MAX;
385 gb->cpu->memory.store8 = GBStore8;
386 gb->cpu->memory.load8 = GBLoad8;
387 }
388}
389
390void _GBMemoryHDMAService(struct GB* gb) {
391 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
392 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
393 ++gb->memory.hdmaSource;
394 ++gb->memory.hdmaDest;
395 --gb->memory.hdmaRemaining;
396 gb->cpu->cycles += 2;
397 if (gb->memory.hdmaRemaining) {
398 gb->memory.hdmaNext += 2;
399 } else {
400 gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
401 gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
402 gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
403 gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
404 if (gb->memory.isHdma) {
405 --gb->memory.io[REG_HDMA5];
406 if (gb->memory.io[REG_HDMA5] == 0xFF) {
407 gb->memory.isHdma = false;
408 }
409 } else {
410 gb->memory.io[REG_HDMA5] |= 0x80;
411 }
412 }
413}
414
415struct OAMBlock {
416 uint16_t low;
417 uint16_t high;
418};
419
420static const struct OAMBlock _oamBlockDMG[] = {
421 { 0xA000, 0xFE00 },
422 { 0xA000, 0xFE00 },
423 { 0xA000, 0xFE00 },
424 { 0xA000, 0xFE00 },
425 { 0x8000, 0xA000 },
426 { 0xA000, 0xFE00 },
427 { 0xA000, 0xFE00 },
428 { 0xA000, 0xFE00 },
429};
430
431static const struct OAMBlock _oamBlockCGB[] = {
432 { 0xA000, 0xC000 },
433 { 0xA000, 0xC000 },
434 { 0xA000, 0xC000 },
435 { 0xA000, 0xC000 },
436 { 0x8000, 0xA000 },
437 { 0xA000, 0xC000 },
438 { 0xC000, 0xFE00 },
439 { 0xA000, 0xC000 },
440};
441
442uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address) {
443 struct GB* gb = (struct GB*) cpu->master;
444 struct GBMemory* memory = &gb->memory;
445 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
446 block = &block[memory->dmaSource >> 13];
447 if (address >= block->low && address < block->high) {
448 return 0xFF;
449 }
450 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
451 return 0xFF;
452 }
453 return GBLoad8(cpu, address);
454}
455
456void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
457 struct GB* gb = (struct GB*) cpu->master;
458 struct GBMemory* memory = &gb->memory;
459 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
460 block = &block[memory->dmaSource >> 13];
461 if (address >= block->low && address < block->high) {
462 return;
463 }
464 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
465 return;
466 }
467 GBStore8(cpu, address, value);
468}
469
470void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
471
472static void _switchBank(struct GBMemory* memory, int bank) {
473 size_t bankStart = bank * GB_SIZE_CART_BANK0;
474 if (bankStart + GB_SIZE_CART_BANK0 > memory->romSize) {
475 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
476 bankStart &= (memory->romSize - 1);
477 bank = bankStart / GB_SIZE_CART_BANK0;
478 }
479 memory->romBank = &memory->rom[bankStart];
480 memory->currentBank = bank;
481}
482
483static void _switchSramBank(struct GBMemory* memory, int bank) {
484 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
485 memory->sramBank = &memory->sram[bankStart];
486 memory->sramCurrentBank = bank;
487}
488
489static void _latchRtc(struct GBMemory* memory) {
490 time_t t;
491 struct mRTCSource* rtc = memory->rtc;
492 if (rtc) {
493 if (rtc->sample) {
494 rtc->sample(rtc);
495 }
496 t = rtc->unixTime(rtc);
497 } else {
498 t = time(0);
499 }
500 struct tm date;
501 localtime_r(&t, &date);
502 memory->rtcRegs[0] = date.tm_sec;
503 memory->rtcRegs[1] = date.tm_min;
504 memory->rtcRegs[2] = date.tm_hour;
505 memory->rtcRegs[3] = date.tm_yday; // TODO: Persist day counter
506 memory->rtcRegs[4] &= 0xF0;
507 memory->rtcRegs[4] |= date.tm_yday >> 8;
508}
509
510void _GBMBC1(struct GBMemory* memory, uint16_t address, uint8_t value) {
511 int bank = value & 0x1F;
512 switch (address >> 13) {
513 case 0x0:
514 switch (value) {
515 case 0:
516 memory->sramAccess = false;
517 break;
518 case 0xA:
519 memory->sramAccess = true;
520 _switchSramBank(memory, memory->sramCurrentBank);
521 break;
522 default:
523 // TODO
524 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
525 break;
526 }
527 break;
528 case 0x1:
529 if (!bank) {
530 ++bank;
531 }
532 _switchBank(memory, bank | (memory->currentBank & 0x60));
533 break;
534 case 0x2:
535 bank &= 3;
536 if (!memory->mbcState.mbc1.mode) {
537 _switchBank(memory, (bank << 5) | (memory->currentBank & 0x1F));
538 } else {
539 _switchSramBank(memory, bank);
540 }
541 break;
542 case 0x3:
543 memory->mbcState.mbc1.mode = value & 1;
544 if (memory->mbcState.mbc1.mode) {
545 _switchBank(memory, memory->currentBank & 0x1F);
546 } else {
547 _switchSramBank(memory, 0);
548 }
549 break;
550 default:
551 // TODO
552 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
553 break;
554 }
555}
556
557void _GBMBC2(struct GBMemory* memory, uint16_t address, uint8_t value) {
558 int bank = value & 0xF;
559 switch (address >> 13) {
560 case 0x0:
561 switch (value) {
562 case 0:
563 memory->sramAccess = false;
564 break;
565 case 0xA:
566 memory->sramAccess = true;
567 _switchSramBank(memory, memory->sramCurrentBank);
568 break;
569 default:
570 // TODO
571 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
572 break;
573 }
574 break;
575 case 0x1:
576 if (!bank) {
577 ++bank;
578 }
579 _switchBank(memory, bank);
580 break;
581 default:
582 // TODO
583 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
584 break;
585 }}
586
587void _GBMBC3(struct GBMemory* memory, uint16_t address, uint8_t value) {
588 int bank = value & 0x7F;
589 switch (address >> 13) {
590 case 0x0:
591 switch (value) {
592 case 0:
593 memory->sramAccess = false;
594 break;
595 case 0xA:
596 memory->sramAccess = true;
597 _switchSramBank(memory, memory->sramCurrentBank);
598 break;
599 default:
600 // TODO
601 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
602 break;
603 }
604 break;
605 case 0x1:
606 if (!bank) {
607 ++bank;
608 }
609 _switchBank(memory, bank);
610 break;
611 case 0x2:
612 if (value < 4) {
613 _switchSramBank(memory, value);
614 memory->rtcAccess = false;
615 } else if (value >= 8 && value <= 0xC) {
616 memory->activeRtcReg = value - 8;
617 memory->rtcAccess = true;
618 }
619 break;
620 case 0x3:
621 if (memory->rtcLatched && value == 0) {
622 memory->rtcLatched = value;
623 } else if (!memory->rtcLatched && value == 1) {
624 _latchRtc(memory);
625 }
626 break;
627 }
628}
629
630void _GBMBC5(struct GBMemory* memory, uint16_t address, uint8_t value) {
631 int bank;
632 switch (address >> 12) {
633 case 0x0:
634 case 0x1:
635 switch (value) {
636 case 0:
637 memory->sramAccess = false;
638 break;
639 case 0xA:
640 memory->sramAccess = true;
641 _switchSramBank(memory, memory->sramCurrentBank);
642 break;
643 default:
644 // TODO
645 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
646 break;
647 }
648 break;
649 case 0x2:
650 bank = (memory->currentBank & 0x100) | value;
651 _switchBank(memory, bank);
652 break;
653 case 0x3:
654 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
655 _switchBank(memory, bank);
656 break;
657 case 0x4:
658 case 0x5:
659 if (memory->mbcType == GB_MBC5_RUMBLE) {
660 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
661 value &= ~8;
662 }
663 _switchSramBank(memory, value & 0xF);
664 break;
665 default:
666 // TODO
667 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
668 break;
669 }
670}
671
672void _GBMBC6(struct GBMemory* memory, uint16_t address, uint8_t value) {
673 // TODO
674 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
675}
676
677void _GBMBC7(struct GBMemory* memory, uint16_t address, uint8_t value) {
678 int bank = value & 0x7F;
679 switch (address >> 13) {
680 case 0x1:
681 _switchBank(memory, bank);
682 break;
683 case 0x2:
684 if (value < 0x10) {
685 _switchSramBank(memory, value);
686 }
687 break;
688 default:
689 // TODO
690 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
691 break;
692 }
693}
694
695uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
696 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
697 switch (address & 0xF0) {
698 case 0x00:
699 case 0x10:
700 case 0x60:
701 case 0x70:
702 return 0;
703 case 0x20:
704 if (memory->rotation && memory->rotation->readTiltX) {
705 int32_t x = -memory->rotation->readTiltX(memory->rotation);
706 x >>= 21;
707 x += 2047;
708 return x;
709 }
710 return 0xFF;
711 case 0x30:
712 if (memory->rotation && memory->rotation->readTiltX) {
713 int32_t x = -memory->rotation->readTiltX(memory->rotation);
714 x >>= 21;
715 x += 2047;
716 return x >> 8;
717 }
718 return 7;
719 case 0x40:
720 if (memory->rotation && memory->rotation->readTiltY) {
721 int32_t y = -memory->rotation->readTiltY(memory->rotation);
722 y >>= 21;
723 y += 2047;
724 return y;
725 }
726 return 0xFF;
727 case 0x50:
728 if (memory->rotation && memory->rotation->readTiltY) {
729 int32_t y = -memory->rotation->readTiltY(memory->rotation);
730 y >>= 21;
731 y += 2047;
732 return y >> 8;
733 }
734 return 7;
735 case 0x80:
736 return (mbc7->sr >> 16) & 1;
737 default:
738 return 0xFF;
739 }
740}
741
742void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
743 if ((address & 0xF0) != 0x80) {
744 return;
745 }
746 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
747 GBMBC7Field old = memory->mbcState.mbc7.field;
748 mbc7->field = GBMBC7FieldClearIO(value);
749 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
750 if (mbc7->state == GBMBC7_STATE_WRITE) {
751 if (mbc7->writable) {
752 memory->sramBank[mbc7->address * 2] = mbc7->sr >> 8;
753 memory->sramBank[mbc7->address * 2 + 1] = mbc7->sr;
754 }
755 mbc7->sr = 0x1FFFF;
756 mbc7->state = GBMBC7_STATE_NULL;
757 } else {
758 mbc7->state = GBMBC7_STATE_IDLE;
759 }
760 }
761 if (!GBMBC7FieldIsSK(old) && GBMBC7FieldIsSK(value)) {
762 if (mbc7->state > GBMBC7_STATE_IDLE && mbc7->state != GBMBC7_STATE_READ) {
763 mbc7->sr <<= 1;
764 mbc7->sr |= GBMBC7FieldGetIO(value);
765 ++mbc7->srBits;
766 }
767 switch (mbc7->state) {
768 case GBMBC7_STATE_IDLE:
769 if (GBMBC7FieldIsIO(value)) {
770 mbc7->state = GBMBC7_STATE_READ_COMMAND;
771 mbc7->srBits = 0;
772 mbc7->sr = 0;
773 }
774 break;
775 case GBMBC7_STATE_READ_COMMAND:
776 if (mbc7->srBits == 2) {
777 mbc7->state = GBMBC7_STATE_READ_ADDRESS;
778 mbc7->srBits = 0;
779 mbc7->command = mbc7->sr;
780 }
781 break;
782 case GBMBC7_STATE_READ_ADDRESS:
783 if (mbc7->srBits == 8) {
784 mbc7->state = GBMBC7_STATE_COMMAND_0 + mbc7->command;
785 mbc7->srBits = 0;
786 mbc7->address = mbc7->sr;
787 if (mbc7->state == GBMBC7_STATE_COMMAND_0) {
788 switch (mbc7->address >> 6) {
789 case 0:
790 mbc7->writable = false;
791 mbc7->state = GBMBC7_STATE_NULL;
792 break;
793 case 3:
794 mbc7->writable = true;
795 mbc7->state = GBMBC7_STATE_NULL;
796 break;
797 }
798 }
799 }
800 break;
801 case GBMBC7_STATE_COMMAND_0:
802 if (mbc7->srBits == 16) {
803 switch (mbc7->address >> 6) {
804 case 0:
805 mbc7->writable = false;
806 mbc7->state = GBMBC7_STATE_NULL;
807 break;
808 case 1:
809 mbc7->state = GBMBC7_STATE_WRITE;
810 if (mbc7->writable) {
811 int i;
812 for (i = 0; i < 256; ++i) {
813 memory->sramBank[i * 2] = mbc7->sr >> 8;
814 memory->sramBank[i * 2 + 1] = mbc7->sr;
815 }
816 }
817 break;
818 case 2:
819 mbc7->state = GBMBC7_STATE_WRITE;
820 if (mbc7->writable) {
821 int i;
822 for (i = 0; i < 256; ++i) {
823 memory->sramBank[i * 2] = 0xFF;
824 memory->sramBank[i * 2 + 1] = 0xFF;
825 }
826 }
827 break;
828 case 3:
829 mbc7->writable = true;
830 mbc7->state = GBMBC7_STATE_NULL;
831 break;
832 }
833 }
834 break;
835 case GBMBC7_STATE_COMMAND_SR_WRITE:
836 if (mbc7->srBits == 16) {
837 mbc7->srBits = 0;
838 mbc7->state = GBMBC7_STATE_WRITE;
839 }
840 break;
841 case GBMBC7_STATE_COMMAND_SR_READ:
842 if (mbc7->srBits == 1) {
843 mbc7->sr = memory->sramBank[mbc7->address * 2] << 8;
844 mbc7->sr |= memory->sramBank[mbc7->address * 2 + 1];
845 mbc7->srBits = 0;
846 mbc7->state = GBMBC7_STATE_READ;
847 }
848 break;
849 case GBMBC7_STATE_COMMAND_SR_FILL:
850 if (mbc7->srBits == 16) {
851 mbc7->sr = 0xFFFF;
852 mbc7->srBits = 0;
853 mbc7->state = GBMBC7_STATE_WRITE;
854 }
855 break;
856 default:
857 break;
858 }
859 } else if (GBMBC7FieldIsSK(old) && !GBMBC7FieldIsSK(value)) {
860 if (mbc7->state == GBMBC7_STATE_READ) {
861 mbc7->sr <<= 1;
862 ++mbc7->srBits;
863 if (mbc7->srBits == 16) {
864 mbc7->srBits = 0;
865 mbc7->state = GBMBC7_STATE_NULL;
866 }
867 }
868 }
869}