src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-arm.h"
7
8#include "arm.h"
9#include "emitter-arm.h"
10#include "isa-inlines.h"
11#include "util/math.h"
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 cpu->cpsr.n = ARM_SIGN(D); \
194 cpu->cpsr.z = !(D); \
195 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
196 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
197 }
198
199#define ARM_SUBTRACTION_S(M, N, D) \
200 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
201 cpu->cpsr = cpu->spsr; \
202 _ARMReadCPSR(cpu); \
203 } else { \
204 cpu->cpsr.n = ARM_SIGN(D); \
205 cpu->cpsr.z = !(D); \
206 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
207 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
208 }
209
210#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 cpu->cpsr.n = ARM_SIGN(D); \
216 cpu->cpsr.z = !(D); \
217 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
218 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
219 }
220
221#define ARM_NEUTRAL_S(M, N, D) \
222 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
223 cpu->cpsr = cpu->spsr; \
224 _ARMReadCPSR(cpu); \
225 } else { \
226 cpu->cpsr.n = ARM_SIGN(D); \
227 cpu->cpsr.z = !(D); \
228 cpu->cpsr.c = cpu->shifterCarryOut; \
229 }
230
231#define ARM_NEUTRAL_HI_S(DLO, DHI) \
232 cpu->cpsr.n = ARM_SIGN(DHI); \
233 cpu->cpsr.z = !((DHI) | (DLO));
234
235#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
236#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
237#define ADDR_MODE_2_ADDRESS (address)
238#define ADDR_MODE_2_RN (cpu->gprs[rn])
239#define ADDR_MODE_2_RM (cpu->gprs[rm])
240#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
241#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
242#define ADDR_MODE_2_WRITEBACK(ADDR) \
243 cpu->gprs[rn] = ADDR; \
244 if (UNLIKELY(rn == ARM_PC)) { \
245 ARM_WRITE_PC; \
246 }
247
248#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
249#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
250#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
251#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
252
253#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
254#define ADDR_MODE_3_RN ADDR_MODE_2_RN
255#define ADDR_MODE_3_RM ADDR_MODE_2_RM
256#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
257#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
258#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
259
260#define ADDR_MODE_4_WRITEBACK_LDM \
261 if (!((1 << rn) & rs)) { \
262 cpu->gprs[rn] = address; \
263 }
264
265#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
266
267#define ARM_LOAD_POST_BODY \
268 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
269 if (rd == ARM_PC) { \
270 ARM_WRITE_PC; \
271 }
272
273#define ARM_STORE_POST_BODY \
274 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
275
276#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
277 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
278 int currentCycles = ARM_PREFETCH_CYCLES; \
279 BODY; \
280 cpu->cycles += currentCycles; \
281 }
282
283#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
284 DEFINE_INSTRUCTION_ARM(NAME, \
285 int rd = (opcode >> 12) & 0xF; \
286 int rn = (opcode >> 16) & 0xF; \
287 UNUSED(rn); \
288 SHIFTER(cpu, opcode); \
289 BODY; \
290 S_BODY; \
291 if (rd == ARM_PC) { \
292 if (cpu->executionMode == MODE_ARM) { \
293 ARM_WRITE_PC; \
294 } else { \
295 THUMB_WRITE_PC; \
296 } \
297 })
298
299#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
310
311#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
317
318#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
319 DEFINE_INSTRUCTION_ARM(NAME, \
320 int rd = (opcode >> 12) & 0xF; \
321 int rdHi = (opcode >> 16) & 0xF; \
322 int rs = (opcode >> 8) & 0xF; \
323 int rm = opcode & 0xF; \
324 if (rdHi == ARM_PC || rd == ARM_PC) { \
325 return; \
326 } \
327 ARM_WAIT_MUL(cpu->gprs[rs]); \
328 BODY; \
329 S_BODY; \
330 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
331
332#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
333 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
334 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
335
336#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
337 DEFINE_INSTRUCTION_ARM(NAME, \
338 uint32_t address; \
339 int rn = (opcode >> 16) & 0xF; \
340 int rd = (opcode >> 12) & 0xF; \
341 int rm = opcode & 0xF; \
342 UNUSED(rm); \
343 address = ADDRESS; \
344 WRITEBACK; \
345 BODY;)
346
347#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
350 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
351 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
354
355#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
356 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
357 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
358 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
366
367#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
370 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
371 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
380
381#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
383 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
384
385#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
386 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
387 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
388 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
389 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
392
393#define ARM_MS_PRE \
394 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
395 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
396
397#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
398
399#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
400 DEFINE_INSTRUCTION_ARM(NAME, \
401 int rn = (opcode >> 16) & 0xF; \
402 int rs = opcode & 0x0000FFFF; \
403 uint32_t address = cpu->gprs[rn]; \
404 S_PRE; \
405 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
406 S_POST; \
407 POST_BODY; \
408 WRITEBACK;)
409
410
411#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
412 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
413 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
414 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
415 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
416 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
417 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
418 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
419 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
420 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
421 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
422 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
423 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
424 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
425 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
426 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
427 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
428
429// Begin ALU definitions
430
431DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
432 int32_t n = cpu->gprs[rn];
433 cpu->gprs[rd] = n + cpu->shifterOperand;)
434
435DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
436 int32_t n = cpu->gprs[rn];
437 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
438
439DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
440 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
441
442DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
443 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
444
445DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
446 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
447
448DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
449 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
450
451DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
452 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
453
454DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
455 cpu->gprs[rd] = cpu->shifterOperand;)
456
457DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
458 cpu->gprs[rd] = ~cpu->shifterOperand;)
459
460DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
461 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
462
463DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
464 int32_t n = cpu->gprs[rn];
465 cpu->gprs[rd] = cpu->shifterOperand - n;)
466
467DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
468 int32_t n = cpu->gprs[rn];
469 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
470
471DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
472 int32_t n = cpu->gprs[rn];
473 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
474
475DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
476 int32_t n = cpu->gprs[rn];
477 cpu->gprs[rd] = n - cpu->shifterOperand;)
478
479DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
480 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
481
482DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
483 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
484
485// End ALU definitions
486
487// Begin multiply definitions
488
489DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
490DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
491
492DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
493 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
494 int32_t dm = cpu->gprs[rd];
495 int32_t dn = d;
496 cpu->gprs[rd] = dm + dn;
497 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
498 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
499
500DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
501 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
502 cpu->gprs[rd] = d;
503 cpu->gprs[rdHi] = d >> 32;,
504 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
505
506DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
507 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
508 int32_t dm = cpu->gprs[rd];
509 int32_t dn = d;
510 cpu->gprs[rd] = dm + dn;
511 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
512 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
513
514DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
515 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
516 cpu->gprs[rd] = d;
517 cpu->gprs[rdHi] = d >> 32;,
518 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
519
520// End multiply definitions
521
522// Begin load/store definitions
523
524DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
525DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
526DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
527DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
528DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
529DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
530DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
531DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
532
533DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
534 enum PrivilegeMode priv = cpu->privilegeMode;
535 ARMSetPrivilegeMode(cpu, MODE_USER);
536 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
537 ARMSetPrivilegeMode(cpu, priv);
538 cpu->gprs[rd] = r;
539 ARM_LOAD_POST_BODY;)
540
541DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
542 enum PrivilegeMode priv = cpu->privilegeMode;
543 ARMSetPrivilegeMode(cpu, MODE_USER);
544 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
545 ARMSetPrivilegeMode(cpu, priv);
546 cpu->gprs[rd] = r;
547 ARM_LOAD_POST_BODY;)
548
549DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
550 enum PrivilegeMode priv = cpu->privilegeMode;
551 int32_t r = cpu->gprs[rd];
552 ARMSetPrivilegeMode(cpu, MODE_USER);
553 cpu->memory.store8(cpu, address, r, ¤tCycles);
554 ARMSetPrivilegeMode(cpu, priv);
555 ARM_STORE_POST_BODY;)
556
557DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
558 enum PrivilegeMode priv = cpu->privilegeMode;
559 int32_t r = cpu->gprs[rd];
560 ARMSetPrivilegeMode(cpu, MODE_USER);
561 cpu->memory.store32(cpu, address, r, ¤tCycles);
562 ARMSetPrivilegeMode(cpu, priv);
563 ARM_STORE_POST_BODY;)
564
565DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
566 load,
567 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
568 if (rs & 0x8000) {
569 ARM_WRITE_PC;
570 })
571
572DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
573 store,
574 ARM_STORE_POST_BODY;)
575
576DEFINE_INSTRUCTION_ARM(SWP,
577 int rm = opcode & 0xF;
578 int rd = (opcode >> 12) & 0xF;
579 int rn = (opcode >> 16) & 0xF;
580 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
581 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
582 cpu->gprs[rd] = d;)
583
584DEFINE_INSTRUCTION_ARM(SWPB,
585 int rm = opcode & 0xF;
586 int rd = (opcode >> 12) & 0xF;
587 int rn = (opcode >> 16) & 0xF;
588 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
589 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
590 cpu->gprs[rd] = d;)
591
592// End load/store definitions
593
594// Begin branch definitions
595
596DEFINE_INSTRUCTION_ARM(B,
597 int32_t offset = opcode << 8;
598 offset >>= 6;
599 cpu->gprs[ARM_PC] += offset;
600 ARM_WRITE_PC;)
601
602DEFINE_INSTRUCTION_ARM(BL,
603 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
604 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
605 cpu->gprs[ARM_PC] += immediate >> 6;
606 ARM_WRITE_PC;)
607
608DEFINE_INSTRUCTION_ARM(BX,
609 int rm = opcode & 0x0000000F;
610 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
611 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
612 if (cpu->executionMode == MODE_THUMB) {
613 THUMB_WRITE_PC;
614 } else {
615 ARM_WRITE_PC;
616
617 })
618DEFINE_INSTRUCTION_ARM(BLX2,
619 int rm = opcode & 0x0000000F;
620 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
621 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
622 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
623 if (cpu->executionMode == MODE_THUMB) {
624 THUMB_WRITE_PC;
625 } else {
626 ARM_WRITE_PC;
627 })
628
629// End branch definitions
630
631// Begin coprocessor definitions
632
633#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
634 DEFINE_INSTRUCTION_ARM(NAME, \
635 int op1 = (opcode >> 21) & 7; \
636 int op2 = (opcode >> 5) & 7; \
637 int rd = (opcode >> 12) & 0xF; \
638 int cp = (opcode >> 8) & 0xF; \
639 int crn = (opcode >> 16) & 0xF; \
640 int crm = opcode & 0xF; \
641 UNUSED(op1); \
642 UNUSED(op2); \
643 UNUSED(rd); \
644 UNUSED(crn); \
645 UNUSED(crm); \
646 BODY;)
647
648DEFINE_COPROCESSOR_INSTRUCTION(MRC, ARM_STUB)
649
650DEFINE_COPROCESSOR_INSTRUCTION(MCR,
651 if (cp == 15 && cpu->irqh.writeCP15) {
652 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
653 } else {
654 ARM_STUB;
655 })
656
657DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
658DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
659DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
660
661// Begin miscellaneous definitions
662
663DEFINE_INSTRUCTION_ARM(CLZ,
664 int rm = opcode & 0xF;
665 int rd = (opcode >> 12) & 0xF;
666 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
667
668DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
669DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
670
671DEFINE_INSTRUCTION_ARM(MSR,
672 int c = opcode & 0x00010000;
673 int f = opcode & 0x00080000;
674 int32_t operand = cpu->gprs[opcode & 0x0000000F];
675 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
676 if (mask & PSR_USER_MASK) {
677 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
678 }
679 if (mask & PSR_STATE_MASK) {
680 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
681 }
682 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
683 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
684 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
685 }
686 _ARMReadCPSR(cpu);
687 if (cpu->executionMode == MODE_THUMB) {
688 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
689 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
690 } else {
691 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
692 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
693 })
694
695DEFINE_INSTRUCTION_ARM(MSRR,
696 int c = opcode & 0x00010000;
697 int f = opcode & 0x00080000;
698 int32_t operand = cpu->gprs[opcode & 0x0000000F];
699 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
700 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
701 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
702
703DEFINE_INSTRUCTION_ARM(MRS, \
704 int rd = (opcode >> 12) & 0xF; \
705 cpu->gprs[rd] = cpu->cpsr.packed;)
706
707DEFINE_INSTRUCTION_ARM(MRSR, \
708 int rd = (opcode >> 12) & 0xF; \
709 cpu->gprs[rd] = cpu->spsr.packed;)
710
711DEFINE_INSTRUCTION_ARM(MSRI,
712 int c = opcode & 0x00010000;
713 int f = opcode & 0x00080000;
714 int rotate = (opcode & 0x00000F00) >> 7;
715 int32_t operand = ROR(opcode & 0x000000FF, rotate);
716 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
717 if (mask & PSR_USER_MASK) {
718 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
719 }
720 if (mask & PSR_STATE_MASK) {
721 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
722 }
723 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
724 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
725 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
726 }
727 _ARMReadCPSR(cpu);
728 if (cpu->executionMode == MODE_THUMB) {
729 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
730 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
731 } else {
732 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
733 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
734 })
735
736DEFINE_INSTRUCTION_ARM(MSRRI,
737 int c = opcode & 0x00010000;
738 int f = opcode & 0x00080000;
739 int rotate = (opcode & 0x00000F00) >> 7;
740 int32_t operand = ROR(opcode & 0x000000FF, rotate);
741 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
742 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
743 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
744
745DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
746
747const ARMInstruction _armv4Table[0x1000] = {
748 DECLARE_ARMV4_EMITTER_BLOCK(_ARMInstruction)
749};
750
751const ARMInstruction _armv5Table[0x1000] = {
752 DECLARE_ARMV5_EMITTER_BLOCK(_ARMInstruction)
753};