1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "core/log.h"
 12#include "core/timing.h"
 13#include "gb/interface.h"
 14#include "lr35902/lr35902.h"
 15
 16#include <time.h>
 17
 18mLOG_DECLARE_CATEGORY(GB_MBC);
 19mLOG_DECLARE_CATEGORY(GB_MEM);
 20
 21struct GB;
 22
 23enum {
 24	GB_BASE_CART_BANK0 = 0x0000,
 25	GB_BASE_CART_BANK1 = 0x4000,
 26	GB_BASE_VRAM = 0x8000,
 27	GB_BASE_EXTERNAL_RAM = 0xA000,
 28	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 29	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 30	GB_BASE_OAM = 0xFE00,
 31	GB_BASE_UNUSABLE = 0xFEA0,
 32	GB_BASE_IO = 0xFF00,
 33	GB_BASE_HRAM = 0xFF80,
 34	GB_BASE_IE = 0xFFFF
 35};
 36
 37enum {
 38	GB_REGION_CART_BANK0 = 0x0,
 39	GB_REGION_CART_BANK1 = 0x4,
 40	GB_REGION_VRAM = 0x8,
 41	GB_REGION_EXTERNAL_RAM = 0xA,
 42	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 43	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 44	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 45	GB_REGION_OTHER = 0xF,
 46};
 47
 48enum {
 49	GB_SIZE_CART_BANK0 = 0x4000,
 50	GB_SIZE_CART_MAX = 0x800000,
 51	GB_SIZE_VRAM = 0x4000,
 52	GB_SIZE_VRAM_BANK0 = 0x2000,
 53	GB_SIZE_EXTERNAL_RAM = 0x2000,
 54	GB_SIZE_WORKING_RAM = 0x8000,
 55	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 56	GB_SIZE_OAM = 0xA0,
 57	GB_SIZE_IO = 0x80,
 58	GB_SIZE_HRAM = 0x7F,
 59};
 60
 61enum {
 62	GB_SRAM_DIRT_NEW = 1,
 63	GB_SRAM_DIRT_SEEN = 2
 64};
 65
 66struct GBMemory;
 67typedef void (*GBMemoryBankController)(struct GB*, uint16_t address, uint8_t value);
 68
 69DECL_BITFIELD(GBMBC7Field, uint8_t);
 70DECL_BIT(GBMBC7Field, SK, 6);
 71DECL_BIT(GBMBC7Field, CS, 7);
 72DECL_BIT(GBMBC7Field, IO, 1);
 73
 74enum GBMBC7MachineState {
 75	GBMBC7_STATE_NULL = -1,
 76	GBMBC7_STATE_IDLE = 0,
 77	GBMBC7_STATE_READ_COMMAND = 1,
 78	GBMBC7_STATE_READ_ADDRESS = 2,
 79	GBMBC7_STATE_COMMAND_0 = 3,
 80	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 81	GBMBC7_STATE_COMMAND_SR_READ = 5,
 82	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 83	GBMBC7_STATE_READ = 7,
 84	GBMBC7_STATE_WRITE = 8,
 85};
 86
 87struct GBMBC1State {
 88	int mode;
 89};
 90
 91struct GBMBC7State {
 92	enum GBMBC7MachineState state;
 93	uint32_t sr;
 94	uint8_t address;
 95	bool writable;
 96	int srBits;
 97	int command;
 98	GBMBC7Field field;
 99};
100
101union GBMBCState {
102	struct GBMBC1State mbc1;
103	struct GBMBC7State mbc7;
104};
105
106struct mRotationSource;
107struct GBMemory {
108	uint8_t* rom;
109	uint8_t* romBase;
110	uint8_t* romBank;
111	enum GBMemoryBankControllerType mbcType;
112	GBMemoryBankController mbc;
113	union GBMBCState mbcState;
114	int currentBank;
115
116	uint8_t* wram;
117	uint8_t* wramBank;
118	int wramCurrentBank;
119
120	bool sramAccess;
121	uint8_t* sram;
122	uint8_t* sramBank;
123	int sramCurrentBank;
124
125	uint8_t io[GB_SIZE_IO];
126	bool ime;
127	uint8_t ie;
128
129	uint8_t hram[GB_SIZE_HRAM];
130
131	uint16_t dmaSource;
132	uint16_t dmaDest;
133	int dmaRemaining;
134
135	uint16_t hdmaSource;
136	uint16_t hdmaDest;
137	int hdmaRemaining;
138	bool isHdma;
139
140	struct mTimingEvent dmaEvent;
141	struct mTimingEvent hdmaEvent;
142
143	size_t romSize;
144
145	bool rtcAccess;
146	int activeRtcReg;
147	bool rtcLatched;
148	uint8_t rtcRegs[5];
149	time_t rtcLastLatch;
150	struct mRTCSource* rtc;
151	struct mRotationSource* rotation;
152	struct mRumble* rumble;
153};
154
155void GBMemoryInit(struct GB* gb);
156void GBMemoryDeinit(struct GB* gb);
157
158void GBMemoryReset(struct GB* gb);
159void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
160
161uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
162void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
163
164uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
165
166int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles);
167void GBMemoryDMA(struct GB* gb, uint16_t base);
168void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
169
170uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
171void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
172
173void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
174
175struct GBSerializedState;
176void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
177void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
178
179#endif