src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "core/interface.h"
9#include "gb/gb.h"
10#include "gb/io.h"
11
12#include "util/memory.h"
13
14#include <time.h>
15
16mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC");
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory");
18
19static void _GBMBCNone(struct GBMemory* memory, uint16_t address, uint8_t value) {
20 UNUSED(memory);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GBMemory*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GBMemory*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GBMemory*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GBMemory*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GBMemory*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GBMemory*, uint16_t address, uint8_t value);
33static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
34static void _GBMBC7Write(struct GBMemory*, uint16_t address, uint8_t value);
35
36static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
37 if (UNLIKELY(address > cpu->memory.activeRegionEnd)) {
38 cpu->memory.setActiveRegion(cpu, address);
39 return cpu->memory.cpuLoad8(cpu, address);
40 }
41 return cpu->memory.activeRegion[address & cpu->memory.activeMask];
42}
43
44static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
45 struct GB* gb = (struct GB*) cpu->master;
46 struct GBMemory* memory = &gb->memory;
47 switch (address >> 12) {
48 case GB_REGION_CART_BANK0:
49 case GB_REGION_CART_BANK0 + 1:
50 case GB_REGION_CART_BANK0 + 2:
51 case GB_REGION_CART_BANK0 + 3:
52 cpu->memory.cpuLoad8 = GBFastLoad8;
53 cpu->memory.activeRegion = memory->rom;
54 cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
55 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
56 break;
57 case GB_REGION_CART_BANK1:
58 case GB_REGION_CART_BANK1 + 1:
59 case GB_REGION_CART_BANK1 + 2:
60 case GB_REGION_CART_BANK1 + 3:
61 cpu->memory.cpuLoad8 = GBFastLoad8;
62 cpu->memory.activeRegion = memory->romBank;
63 cpu->memory.activeRegionEnd = GB_BASE_VRAM;
64 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
65 break;
66 default:
67 cpu->memory.cpuLoad8 = GBLoad8;
68 break;
69 }
70}
71
72static void _GBMemoryDMAService(struct GB* gb);
73static void _GBMemoryHDMAService(struct GB* gb);
74
75void GBMemoryInit(struct GB* gb) {
76 struct LR35902Core* cpu = gb->cpu;
77 cpu->memory.cpuLoad8 = GBLoad8;
78 cpu->memory.load8 = GBLoad8;
79 cpu->memory.store8 = GBStore8;
80 cpu->memory.setActiveRegion = GBSetActiveRegion;
81
82 gb->memory.wram = 0;
83 gb->memory.wramBank = 0;
84 gb->memory.rom = 0;
85 gb->memory.romBank = 0;
86 gb->memory.romSize = 0;
87 gb->memory.sram = 0;
88 gb->memory.mbcType = GB_MBC_NONE;
89 gb->memory.mbc = 0;
90
91 gb->memory.rtc = NULL;
92
93 GBIOInit(gb);
94}
95
96void GBMemoryDeinit(struct GB* gb) {
97 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
98 if (gb->memory.rom) {
99 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
100 }
101}
102
103void GBMemoryReset(struct GB* gb) {
104 if (gb->memory.wram) {
105 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
106 }
107 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
108 GBMemorySwitchWramBank(&gb->memory, 1);
109 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
110 gb->memory.currentBank = 1;
111 if (!gb->memory.sram) {
112 gb->memory.sram = anonymousMemoryMap(0x20000);
113 }
114 gb->memory.sramCurrentBank = 0;
115 gb->memory.sramBank = gb->memory.sram;
116
117 gb->memory.ime = false;
118 gb->memory.ie = 0;
119
120 gb->memory.dmaNext = INT_MAX;
121 gb->memory.dmaRemaining = 0;
122 gb->memory.dmaSource = 0;
123 gb->memory.dmaDest = 0;
124 gb->memory.hdmaNext = INT_MAX;
125 gb->memory.hdmaRemaining = 0;
126 gb->memory.hdmaSource = 0;
127 gb->memory.hdmaDest = 0;
128 gb->memory.isHdma = false;
129
130 gb->memory.sramAccess = false;
131 gb->memory.rtcAccess = false;
132 gb->memory.activeRtcReg = 0;
133 gb->memory.rtcLatched = 0;
134 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
135
136 memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
137
138 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
139 switch (cart->type) {
140 case 0:
141 case 8:
142 case 9:
143 gb->memory.mbc = _GBMBCNone;
144 gb->memory.mbcType = GB_MBC_NONE;
145 break;
146 case 1:
147 case 2:
148 case 3:
149 gb->memory.mbc = _GBMBC1;
150 gb->memory.mbcType = GB_MBC1;
151 break;
152 case 5:
153 case 6:
154 gb->memory.mbc = _GBMBC2;
155 gb->memory.mbcType = GB_MBC2;
156 break;
157 case 0x0F:
158 case 0x10:
159 case 0x11:
160 case 0x12:
161 case 0x13:
162 gb->memory.mbc = _GBMBC3;
163 gb->memory.mbcType = GB_MBC3;
164 break;
165 default:
166 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
167 case 0x19:
168 case 0x1A:
169 case 0x1B:
170 gb->memory.mbc = _GBMBC5;
171 gb->memory.mbcType = GB_MBC5;
172 break;
173 case 0x1C:
174 case 0x1D:
175 case 0x1E:
176 gb->memory.mbc = _GBMBC5;
177 gb->memory.mbcType = GB_MBC5_RUMBLE;
178 break;
179 case 0x20:
180 gb->memory.mbc = _GBMBC6;
181 gb->memory.mbcType = GB_MBC6;
182 break;
183 case 0x22:
184 gb->memory.mbc = _GBMBC7;
185 gb->memory.mbcType = GB_MBC7;
186 memset(&gb->memory.mbcState.mbc7, 0, sizeof(gb->memory.mbcState.mbc7));
187 break;
188 }
189
190 if (!gb->memory.wram) {
191 GBMemoryDeinit(gb);
192 }
193}
194
195void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
196 bank &= 7;
197 if (!bank) {
198 bank = 1;
199 }
200 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
201 memory->wramCurrentBank = bank;
202}
203
204uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
205 struct GB* gb = (struct GB*) cpu->master;
206 struct GBMemory* memory = &gb->memory;
207 switch (address >> 12) {
208 case GB_REGION_CART_BANK0:
209 case GB_REGION_CART_BANK0 + 1:
210 case GB_REGION_CART_BANK0 + 2:
211 case GB_REGION_CART_BANK0 + 3:
212 return memory->rom[address & (GB_SIZE_CART_BANK0 - 1)];
213 case GB_REGION_CART_BANK1:
214 case GB_REGION_CART_BANK1 + 1:
215 case GB_REGION_CART_BANK1 + 2:
216 case GB_REGION_CART_BANK1 + 3:
217 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
218 case GB_REGION_VRAM:
219 case GB_REGION_VRAM + 1:
220 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
221 case GB_REGION_EXTERNAL_RAM:
222 case GB_REGION_EXTERNAL_RAM + 1:
223 if (memory->rtcAccess) {
224 return gb->memory.rtcRegs[memory->activeRtcReg];
225 } else if (memory->sramAccess) {
226 return gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
227 } else if (memory->mbcType == GB_MBC7) {
228 return _GBMBC7Read(memory, address);
229 }
230 return 0xFF;
231 case GB_REGION_WORKING_RAM_BANK0:
232 case GB_REGION_WORKING_RAM_BANK0 + 2:
233 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
234 case GB_REGION_WORKING_RAM_BANK1:
235 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
236 default:
237 if (address < GB_BASE_OAM) {
238 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
239 }
240 if (address < GB_BASE_UNUSABLE) {
241 if (gb->video.mode < 2) {
242 return gb->video.oam.raw[address & 0xFF];
243 }
244 return 0xFF;
245 }
246 if (address < GB_BASE_IO) {
247 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
248 return 0xFF;
249 }
250 if (address < GB_BASE_HRAM) {
251 return GBIORead(gb, address & (GB_SIZE_IO - 1));
252 }
253 if (address < GB_BASE_IE) {
254 return memory->hram[address & GB_SIZE_HRAM];
255 }
256 return GBIORead(gb, REG_IE);
257 }
258}
259
260void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
261 struct GB* gb = (struct GB*) cpu->master;
262 struct GBMemory* memory = &gb->memory;
263 switch (address >> 12) {
264 case GB_REGION_CART_BANK0:
265 case GB_REGION_CART_BANK0 + 1:
266 case GB_REGION_CART_BANK0 + 2:
267 case GB_REGION_CART_BANK0 + 3:
268 case GB_REGION_CART_BANK1:
269 case GB_REGION_CART_BANK1 + 1:
270 case GB_REGION_CART_BANK1 + 2:
271 case GB_REGION_CART_BANK1 + 3:
272 memory->mbc(memory, address, value);
273 cpu->memory.setActiveRegion(cpu, cpu->pc);
274 return;
275 case GB_REGION_VRAM:
276 case GB_REGION_VRAM + 1:
277 // TODO: Block access in wrong modes
278 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
279 return;
280 case GB_REGION_EXTERNAL_RAM:
281 case GB_REGION_EXTERNAL_RAM + 1:
282 if (memory->rtcAccess) {
283 gb->memory.rtcRegs[memory->activeRtcReg] = value;
284 } else if (memory->sramAccess) {
285 gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
286 } else if (gb->memory.mbcType == GB_MBC7) {
287 _GBMBC7Write(&gb->memory, address, value);
288 }
289 return;
290 case GB_REGION_WORKING_RAM_BANK0:
291 case GB_REGION_WORKING_RAM_BANK0 + 2:
292 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
293 return;
294 case GB_REGION_WORKING_RAM_BANK1:
295 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
296 return;
297 default:
298 if (address < GB_BASE_OAM) {
299 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
300 } else if (address < GB_BASE_UNUSABLE) {
301 if (gb->video.mode < 2) {
302 gb->video.oam.raw[address & 0xFF] = value;
303 }
304 } else if (address < GB_BASE_IO) {
305 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
306 } else if (address < GB_BASE_HRAM) {
307 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
308 } else if (address < GB_BASE_IE) {
309 memory->hram[address & GB_SIZE_HRAM] = value;
310 } else {
311 GBIOWrite(gb, REG_IE, value);
312 }
313 }
314}
315
316int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles) {
317 int nextEvent = INT_MAX;
318 if (gb->memory.dmaRemaining) {
319 gb->memory.dmaNext -= cycles;
320 if (gb->memory.dmaNext <= 0) {
321 _GBMemoryDMAService(gb);
322 }
323 nextEvent = gb->memory.dmaNext;
324 }
325 if (gb->memory.hdmaRemaining) {
326 gb->memory.hdmaNext -= cycles;
327 if (gb->memory.hdmaNext <= 0) {
328 _GBMemoryHDMAService(gb);
329 }
330 if (gb->memory.hdmaNext < nextEvent) {
331 nextEvent = gb->memory.hdmaNext;
332 }
333 }
334 return nextEvent;
335}
336
337void GBMemoryDMA(struct GB* gb, uint16_t base) {
338 if (base > 0xF100) {
339 return;
340 }
341 gb->cpu->memory.store8 = GBDMAStore8;
342 gb->cpu->memory.load8 = GBDMALoad8;
343 gb->cpu->memory.cpuLoad8 = GBDMALoad8;
344 gb->memory.dmaNext = gb->cpu->cycles + 8;
345 if (gb->memory.dmaNext < gb->cpu->nextEvent) {
346 gb->cpu->nextEvent = gb->memory.dmaNext;
347 }
348 gb->memory.dmaSource = base;
349 gb->memory.dmaDest = 0;
350 gb->memory.dmaRemaining = 0xA0;
351}
352
353void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
354 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
355 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
356 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
357 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
358 gb->memory.hdmaSource &= 0xFFF0;
359 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
360 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
361 return;
362 }
363 gb->memory.hdmaDest &= 0x1FF0;
364 gb->memory.hdmaDest |= 0x8000;
365 bool wasHdma = gb->memory.isHdma;
366 gb->memory.isHdma = value & 0x80;
367 if (!wasHdma && !gb->memory.isHdma) {
368 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
369 gb->memory.hdmaNext = gb->cpu->cycles;
370 gb->cpu->nextEvent = gb->cpu->cycles;
371 }
372}
373
374void _GBMemoryDMAService(struct GB* gb) {
375 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
376 // TODO: Can DMA write OAM during modes 2-3?
377 gb->video.oam.raw[gb->memory.dmaDest] = b;
378 ++gb->memory.dmaSource;
379 ++gb->memory.dmaDest;
380 --gb->memory.dmaRemaining;
381 if (gb->memory.dmaRemaining) {
382 gb->memory.dmaNext += 4;
383 } else {
384 gb->memory.dmaNext = INT_MAX;
385 gb->cpu->memory.store8 = GBStore8;
386 gb->cpu->memory.load8 = GBLoad8;
387 }
388}
389
390void _GBMemoryHDMAService(struct GB* gb) {
391 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
392 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
393 ++gb->memory.hdmaSource;
394 ++gb->memory.hdmaDest;
395 --gb->memory.hdmaRemaining;
396 gb->cpu->cycles += 2;
397 if (gb->memory.hdmaRemaining) {
398 gb->memory.hdmaNext += 2;
399 } else {
400 gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
401 gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
402 gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
403 gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
404 if (gb->memory.isHdma) {
405 --gb->memory.io[REG_HDMA5];
406 if (gb->memory.io[REG_HDMA5] == 0xFF) {
407 gb->memory.isHdma = false;
408 }
409 } else {
410 gb->memory.io[REG_HDMA5] |= 0x80;
411 }
412 }
413}
414
415uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address) {
416 struct GB* gb = (struct GB*) cpu->master;
417 struct GBMemory* memory = &gb->memory;
418 if (address < 0xFF80 || address == 0xFFFF) {
419 return 0xFF;
420 }
421 return memory->hram[address & GB_SIZE_HRAM];
422}
423
424void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
425 struct GB* gb = (struct GB*) cpu->master;
426 struct GBMemory* memory = &gb->memory;
427 if (address < 0xFF80 || address == 0xFFFF) {
428 return;
429 }
430 memory->hram[address & GB_SIZE_HRAM] = value;
431}
432
433uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
434
435void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
436
437static void _switchBank(struct GBMemory* memory, int bank) {
438 size_t bankStart = bank * GB_SIZE_CART_BANK0;
439 if (bankStart + GB_SIZE_CART_BANK0 > memory->romSize) {
440 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
441 bankStart &= (GB_SIZE_CART_BANK0 - 1);
442 bank /= GB_SIZE_CART_BANK0;
443 }
444 memory->romBank = &memory->rom[bankStart];
445 memory->currentBank = bank;
446}
447
448static void _switchSramBank(struct GBMemory* memory, int bank) {
449 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
450 memory->sramBank = &memory->sram[bankStart];
451 memory->sramCurrentBank = bank;
452}
453
454static void _latchRtc(struct GBMemory* memory) {
455 time_t t;
456 struct mRTCSource* rtc = memory->rtc;
457 if (rtc) {
458 if (rtc->sample) {
459 rtc->sample(rtc);
460 }
461 t = rtc->unixTime(rtc);
462 } else {
463 t = time(0);
464 }
465 struct tm date;
466 localtime_r(&t, &date);
467 memory->rtcRegs[0] = date.tm_sec;
468 memory->rtcRegs[1] = date.tm_min;
469 memory->rtcRegs[2] = date.tm_hour;
470 memory->rtcRegs[3] = date.tm_yday; // TODO: Persist day counter
471 memory->rtcRegs[4] &= 0xF0;
472 memory->rtcRegs[4] |= date.tm_yday >> 8;
473}
474
475void _GBMBC1(struct GBMemory* memory, uint16_t address, uint8_t value) {
476 int bank = value & 0x1F;
477 switch (address >> 13) {
478 case 0x0:
479 switch (value) {
480 case 0:
481 memory->sramAccess = false;
482 break;
483 case 0xA:
484 memory->sramAccess = true;
485 _switchSramBank(memory, memory->sramCurrentBank);
486 break;
487 default:
488 // TODO
489 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
490 break;
491 }
492 break;
493 case 0x1:
494 if (!bank) {
495 ++bank;
496 }
497 _switchBank(memory, bank | (memory->currentBank & 0x60));
498 break;
499 default:
500 // TODO
501 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
502 break;
503 }
504}
505
506void _GBMBC2(struct GBMemory* memory, uint16_t address, uint8_t value) {
507 mLOG(GB_MBC, STUB, "MBC2 unimplemented");
508}
509
510void _GBMBC3(struct GBMemory* memory, uint16_t address, uint8_t value) {
511 int bank = value & 0x7F;
512 switch (address >> 13) {
513 case 0x0:
514 switch (value) {
515 case 0:
516 memory->sramAccess = false;
517 break;
518 case 0xA:
519 memory->sramAccess = true;
520 _switchSramBank(memory, memory->sramCurrentBank);
521 break;
522 default:
523 // TODO
524 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
525 break;
526 }
527 break;
528 case 0x1:
529 if (!bank) {
530 ++bank;
531 }
532 _switchBank(memory, bank);
533 break;
534 case 0x2:
535 if (value < 4) {
536 _switchSramBank(memory, value);
537 memory->rtcAccess = false;
538 } else if (value >= 8 && value <= 0xC) {
539 memory->activeRtcReg = value - 8;
540 memory->rtcAccess = true;
541 }
542 break;
543 case 0x3:
544 if (memory->rtcLatched && value == 0) {
545 memory->rtcLatched = value;
546 } else if (!memory->rtcLatched && value == 1) {
547 _latchRtc(memory);
548 }
549 break;
550 }
551}
552
553void _GBMBC5(struct GBMemory* memory, uint16_t address, uint8_t value) {
554 int bank;
555 switch (address >> 12) {
556 case 0x0:
557 case 0x1:
558 switch (value) {
559 case 0:
560 memory->sramAccess = false;
561 break;
562 case 0xA:
563 memory->sramAccess = true;
564 _switchSramBank(memory, memory->sramCurrentBank);
565 break;
566 default:
567 // TODO
568 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
569 break;
570 }
571 break;
572 case 0x2:
573 bank = (memory->currentBank & 0x100) | value;
574 _switchBank(memory, bank);
575 break;
576 case 0x3:
577 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
578 _switchBank(memory, bank);
579 break;
580 case 0x4:
581 case 0x5:
582 if (memory->mbcType == GB_MBC5_RUMBLE) {
583 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
584 value &= ~8;
585 }
586 _switchSramBank(memory, value & 0xF);
587 break;
588 default:
589 // TODO
590 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
591 break;
592 }
593}
594
595void _GBMBC6(struct GBMemory* memory, uint16_t address, uint8_t value) {
596 // TODO
597 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
598}
599
600void _GBMBC7(struct GBMemory* memory, uint16_t address, uint8_t value) {
601 int bank = value & 0x7F;
602 switch (address >> 13) {
603 case 0x1:
604 _switchBank(memory, bank);
605 break;
606 case 0x2:
607 if (value < 0x10) {
608 _switchSramBank(memory, value);
609 }
610 break;
611 default:
612 // TODO
613 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
614 break;
615 }
616}
617
618uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
619 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
620 switch (address & 0xF0) {
621 case 0x00:
622 case 0x10:
623 case 0x60:
624 case 0x70:
625 return 0;
626 case 0x20:
627 if (memory->rotation && memory->rotation->readTiltX) {
628 int32_t x = -memory->rotation->readTiltX(memory->rotation);
629 x >>= 21;
630 x += 2047;
631 return x;
632 }
633 return 0xFF;
634 case 0x30:
635 if (memory->rotation && memory->rotation->readTiltX) {
636 int32_t x = -memory->rotation->readTiltX(memory->rotation);
637 x >>= 21;
638 x += 2047;
639 return x >> 8;
640 }
641 return 7;
642 case 0x40:
643 if (memory->rotation && memory->rotation->readTiltY) {
644 int32_t y = -memory->rotation->readTiltY(memory->rotation);
645 y >>= 21;
646 y += 2047;
647 return y;
648 }
649 return 0xFF;
650 case 0x50:
651 if (memory->rotation && memory->rotation->readTiltY) {
652 int32_t y = -memory->rotation->readTiltY(memory->rotation);
653 y >>= 21;
654 y += 2047;
655 return y >> 8;
656 }
657 return 7;
658 case 0x80:
659 return (mbc7->sr >> 16) & 1;
660 default:
661 return 0xFF;
662 }
663}
664
665void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
666 if ((address & 0xF0) != 0x80) {
667 return;
668 }
669 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
670 GBMBC7Field old = memory->mbcState.mbc7.field;
671 mbc7->field = GBMBC7FieldClearIO(value);
672 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
673 if (mbc7->state == GBMBC7_STATE_WRITE) {
674 if (mbc7->writable) {
675 memory->sramBank[mbc7->address * 2] = mbc7->sr >> 8;
676 memory->sramBank[mbc7->address * 2 + 1] = mbc7->sr;
677 }
678 mbc7->sr = 0x1FFFF;
679 mbc7->state = GBMBC7_STATE_NULL;
680 } else {
681 mbc7->state = GBMBC7_STATE_IDLE;
682 }
683 }
684 if (!GBMBC7FieldIsSK(old) && GBMBC7FieldIsSK(value)) {
685 if (mbc7->state > GBMBC7_STATE_IDLE && mbc7->state != GBMBC7_STATE_READ) {
686 mbc7->sr <<= 1;
687 mbc7->sr |= GBMBC7FieldGetIO(value);
688 ++mbc7->srBits;
689 }
690 switch (mbc7->state) {
691 case GBMBC7_STATE_IDLE:
692 if (GBMBC7FieldIsIO(value)) {
693 mbc7->state = GBMBC7_STATE_READ_COMMAND;
694 mbc7->srBits = 0;
695 mbc7->sr = 0;
696 }
697 break;
698 case GBMBC7_STATE_READ_COMMAND:
699 if (mbc7->srBits == 2) {
700 mbc7->state = GBMBC7_STATE_READ_ADDRESS;
701 mbc7->srBits = 0;
702 mbc7->command = mbc7->sr;
703 }
704 break;
705 case GBMBC7_STATE_READ_ADDRESS:
706 if (mbc7->srBits == 8) {
707 mbc7->state = GBMBC7_STATE_COMMAND_0 + mbc7->command;
708 mbc7->srBits = 0;
709 mbc7->address = mbc7->sr;
710 if (mbc7->state == GBMBC7_STATE_COMMAND_0) {
711 switch (mbc7->address >> 6) {
712 case 0:
713 mbc7->writable = false;
714 mbc7->state = GBMBC7_STATE_NULL;
715 break;
716 case 3:
717 mbc7->writable = true;
718 mbc7->state = GBMBC7_STATE_NULL;
719 break;
720 }
721 }
722 }
723 break;
724 case GBMBC7_STATE_COMMAND_0:
725 if (mbc7->srBits == 16) {
726 switch (mbc7->address >> 6) {
727 case 0:
728 mbc7->writable = false;
729 mbc7->state = GBMBC7_STATE_NULL;
730 break;
731 case 1:
732 mbc7->state = GBMBC7_STATE_WRITE;
733 if (mbc7->writable) {
734 int i;
735 for (i = 0; i < 256; ++i) {
736 memory->sramBank[i * 2] = mbc7->sr >> 8;
737 memory->sramBank[i * 2 + 1] = mbc7->sr;
738 }
739 }
740 break;
741 case 2:
742 mbc7->state = GBMBC7_STATE_WRITE;
743 if (mbc7->writable) {
744 int i;
745 for (i = 0; i < 256; ++i) {
746 memory->sramBank[i * 2] = 0xFF;
747 memory->sramBank[i * 2 + 1] = 0xFF;
748 }
749 }
750 break;
751 case 3:
752 mbc7->writable = true;
753 mbc7->state = GBMBC7_STATE_NULL;
754 break;
755 }
756 }
757 break;
758 case GBMBC7_STATE_COMMAND_SR_WRITE:
759 if (mbc7->srBits == 16) {
760 mbc7->srBits = 0;
761 mbc7->state = GBMBC7_STATE_WRITE;
762 }
763 break;
764 case GBMBC7_STATE_COMMAND_SR_READ:
765 if (mbc7->srBits == 1) {
766 mbc7->sr = memory->sramBank[mbc7->address * 2] << 8;
767 mbc7->sr |= memory->sramBank[mbc7->address * 2 + 1];
768 mbc7->srBits = 0;
769 mbc7->state = GBMBC7_STATE_READ;
770 }
771 break;
772 case GBMBC7_STATE_COMMAND_SR_FILL:
773 if (mbc7->srBits == 16) {
774 mbc7->sr = 0xFFFF;
775 mbc7->srBits = 0;
776 mbc7->state = GBMBC7_STATE_WRITE;
777 }
778 break;
779 default:
780 break;
781 }
782 } else if (GBMBC7FieldIsSK(old) && !GBMBC7FieldIsSK(value)) {
783 if (mbc7->state == GBMBC7_STATE_READ) {
784 mbc7->sr <<= 1;
785 ++mbc7->srBits;
786 if (mbc7->srBits == 16) {
787 mbc7->srBits = 0;
788 mbc7->state = GBMBC7_STATE_NULL;
789 }
790 }
791 }
792}